JP2009260302A - Semiconductor package - Google Patents

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JP2009260302A
JP2009260302A JP2009063929A JP2009063929A JP2009260302A JP 2009260302 A JP2009260302 A JP 2009260302A JP 2009063929 A JP2009063929 A JP 2009063929A JP 2009063929 A JP2009063929 A JP 2009063929A JP 2009260302 A JP2009260302 A JP 2009260302A
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Prior art keywords
sealing resin
chip
wiring board
semiconductor
semiconductor chip
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Japanese (ja)
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Takashi Fujita
貴志 藤田
Kazuki Nishijima
一樹 西嶋
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Toppan Inc
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Toppan Printing Co Ltd
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Priority to JP2009063929A priority Critical patent/JP2009260302A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package which can improve the mounting ability and mounting reliability by making a deflection in mounting of a semiconductor chip small. <P>SOLUTION: The package includes: a multilayer wiring substrate 3; a semiconductor chip 1 connected onto the multilayer wiring substrate 3 through a solder bump 2; and a sealing resin positioned between the multilayer wiring substrate 3 and semiconductor chip 1. The sealing resins 4, 5 have a first chip sealing resin 4 filled into a clearance between the multilayer 3 and semiconductor chip 1 and a second chip sealing resin 5 positioned between the surrounding of the semiconductor chip 1 and multilayer wiring substrate 3 facing to the surrounding. The first chip sealing resin 4 and second chip sealing resin 5 have an elastic modulus different to each other respectively. Alternatively, the first chip sealing resin 4 and second chip sealing resin 5 have a linear expansion coefficient different to each other respectively. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、はんだバンプ（バンプ電極）を介して多層配線基板上に半導体チップを実装した半導体パッケージに関する。   The present invention relates to a semiconductor package in which a semiconductor chip is mounted on a multilayer wiring board via solder bumps (bump electrodes).

半導体チップを多層配線基板上に実装する方法は、接点数の増大、または、信号遅延の問題により、ワイヤーボンディング接続から、はんだバンプを介するフリップチップ接続に移行してきている。
フリップチップ接続では、図３に示すように、配線基板３と、配線基板３上に複数のバンプ電極２を介して接続された半導体チップ１と、配線基板３と半導体チップ１との間に設けられた封止用樹脂６とを備える半導体パッケージが製造される。
従来のようなコア層を持ち、比較的総厚が厚い多層配線基板上に半導体チップをフリップチップ接続で実装する場合は、多層配線基板はそれほど反らないが、電気特性に優れるコア層を持たず、総厚が薄い多層配線基板では、封止用樹脂を熱により硬化させる工程で、多層配線基板と半導体チップと封止用樹脂の熱膨張係数の相異から、多層配線基板が反ってしまい、実装不良または実装信頼性の低下を引き起こす（図３参照）。 The method of mounting a semiconductor chip on a multilayer wiring board has shifted from wire bonding connection to flip chip connection via solder bumps due to an increase in the number of contacts or signal delay.
In the flip-chip connection, as shown in FIG. 3, the wiring board 3, the semiconductor chip 1 connected to the wiring board 3 via a plurality of bump electrodes 2, and the wiring board 3 and the semiconductor chip 1 are provided. A semiconductor package including the sealing resin 6 thus manufactured is manufactured.
When mounting a semiconductor chip on a multilayer wiring board having a conventional core layer and a relatively large total thickness by flip chip connection, the multilayer wiring board is not warped so much, but has a core layer with excellent electrical characteristics. However, in a multilayer wiring board with a thin total thickness, the multilayer wiring board warps due to the difference in thermal expansion coefficients of the multilayer wiring board, the semiconductor chip, and the sealing resin in the process of curing the sealing resin by heat. This causes a mounting failure or a decrease in mounting reliability (see FIG. 3).

上記実装性、実装信頼性の問題を解決するため、はんだバンプエリア周辺部のはんだバンプを大きくする方法が提案されている（特許文献１参照）。しかし、この方法では、必要以上に大きいはんだバンプが必要になり、多ピン、狭ピッチ化に逆向するといった問題がある。   In order to solve the above problems of mounting property and mounting reliability, a method of enlarging solder bumps around the solder bump area has been proposed (see Patent Document 1). However, this method requires a solder bump that is larger than necessary, and there is a problem that it is counterproductive to multi-pin and narrow pitch.

特開平１１−７４３１２JP-A-11-74312

本発明は、上述のような半導体チップと多層配線基板と封止用樹脂の熱膨張係数の相異から発生する反り問題を解決するためになされたものであり、多ピン、狭ピッチ化に逆向することなく、実装時の反りを小さくすることで、実装性、実装信頼性を向上させることができる半導体パッケージを提供することを課題とするものである。   The present invention has been made in order to solve the problem of warping caused by the difference in thermal expansion coefficients of the semiconductor chip, the multilayer wiring board, and the sealing resin as described above. Accordingly, it is an object of the present invention to provide a semiconductor package that can improve mountability and mounting reliability by reducing warpage during mounting.

上記課題を解決するためになされた請求項１に係る発明は、配線基板と、前記配線基板上に複数のバンプ電極を介して接続された半導体チップと、前記配線基板と前記半導体チップとの間に設けられた封止用樹脂とを備える半導体パッケージであって、前記封止用樹脂は、前記配線基板と前記半導体チップとの間隙に充填された第一のチップ封止用樹脂と、前記第一のチップ封止用樹脂の外側で前記半導体チップの外周部とこの外周部に対向する前記配線基板箇所との間に設けられた第二のチップ封止用樹脂とを備え、前記第一のチップ封止用樹脂と前記第二のチップ封止用樹脂は互いに異なる弾性率を有していることを特徴とする半導体パッケージである。   The invention according to claim 1, which has been made to solve the above problems, includes a wiring board, a semiconductor chip connected to the wiring board via a plurality of bump electrodes, and the wiring board and the semiconductor chip. A sealing resin provided on the semiconductor chip, wherein the sealing resin includes a first chip sealing resin filled in a gap between the wiring substrate and the semiconductor chip; A second chip sealing resin provided between the outer peripheral portion of the semiconductor chip and the wiring board portion facing the outer peripheral portion outside the one chip sealing resin, The semiconductor package is characterized in that the chip sealing resin and the second chip sealing resin have different elastic moduli.

次に請求項２に係る発明は、配線基板と、前記配線基板上に複数のバンプ電極を介して接続された半導体チップと、前記配線基板と前記半導体チップとの間に設けられた封止用樹脂とを備える半導体パッケージであって、前記封止用樹脂は、前記配線基板と前記半導体チップとの間隙に充填された第一のチップ封止用樹脂と、前記第一のチップ封止用樹脂の外側で前記半導体チップの外周部とこの外周部に対向する前記配線基板箇所との間に設けられた第二のチップ封止用樹脂とを備え、前記第一のチップ封止用樹脂と前記第二のチップ封止用樹脂は互いに異なる線膨張係数を有していることを特徴とする半導体パッケージである。   Next, the invention according to claim 2 is a sealing substrate provided between a wiring substrate, a semiconductor chip connected to the wiring substrate via a plurality of bump electrodes, and the wiring substrate and the semiconductor chip. A semiconductor package comprising a resin, wherein the sealing resin includes a first chip sealing resin filled in a gap between the wiring substrate and the semiconductor chip, and the first chip sealing resin. A second chip sealing resin provided between the outer peripheral portion of the semiconductor chip and the wiring board portion facing the outer peripheral portion on the outer side of the first chip sealing resin and the The second chip sealing resin is a semiconductor package characterized by having different linear expansion coefficients.

次に請求項３に係る発明は、前記第二のチップ封止用樹脂は、前記第一のチップ封止用樹脂よりも高い弾性率を有することを特徴とする請求項１又は２記載の半導体パッケージである。   Next, the invention according to claim 3 is characterized in that the second chip sealing resin has a higher elastic modulus than the first chip sealing resin. It is a package.

次に請求項４に係る発明は、前記第二のチップ封止用樹脂は、前記第一のチップ封止用樹脂よりも高い線膨張係数を有することを特徴とする請求項１〜３記載の半導体パッケージである。   Next, the invention according to claim 4 is characterized in that the second chip sealing resin has a higher linear expansion coefficient than the first chip sealing resin. It is a semiconductor package.

次に請求項５に係る発明は、前記第二のチップ封止用樹脂と前記第一のチップ封止用樹脂の弾性率の差が１ＧＰａ以上であることを特徴とする請求項１〜４記載の半導体パッケージである。   Next, the invention according to claim 5 is characterized in that the difference in elastic modulus between the second chip sealing resin and the first chip sealing resin is 1 GPa or more. This is a semiconductor package.

次に請求項６に係る発明は、前記第二のチップ封止用樹脂と前記第一のチップ封止用樹脂の線膨張係数の差が１０ｐｐｍ以上であることを特徴とする請求項１〜４記載の半導体パッケージである。   Next, the invention according to claim 6 is characterized in that the difference in linear expansion coefficient between the second chip sealing resin and the first chip sealing resin is 10 ppm or more. It is a semiconductor package of description.

本発明では、異なる弾性率を有する２種類チップ封止用樹脂、もしくは異なる線膨張係数を有する２種類のチップ封止用樹脂、を用いて多層配線基板上に実装された半導体チップを封止することにより、半導体チップの外周部に配置されたチップ封止用樹脂が基板の反りと逆方向の応力を生じさせて、多層配線基板と半導体チップの熱膨張係数の相異に起因する基板の反りを低減させることが可能となるため、反りの生じやすいコアを有さない多層配線基板に半導体チップを実装したパッケージに特に有効である。   In the present invention, a semiconductor chip mounted on a multilayer wiring board is sealed using two types of chip sealing resins having different elastic moduli or two types of chip sealing resins having different linear expansion coefficients. As a result, the chip sealing resin disposed on the outer periphery of the semiconductor chip causes stress in the opposite direction to the warpage of the substrate, and the warpage of the substrate due to the difference in the thermal expansion coefficient between the multilayer wiring board and the semiconductor chip. Therefore, it is particularly effective for a package in which a semiconductor chip is mounted on a multilayer wiring board that does not have a core that is likely to be warped.

封止用樹脂未硬化状態での本発明半導体パッケージの断面模式図Cross-sectional schematic view of the semiconductor package of the present invention in an uncured state of the sealing resin 本発明の半導体パッケージの模式図（封止用樹脂硬化後）Schematic diagram of semiconductor package of the present invention (after curing resin for sealing) 一種類の封止用樹脂のみで構成された一般的な半導体パッケージの断面模式図（封止用樹脂硬化後）Cross-sectional schematic diagram of a general semiconductor package composed of only one type of sealing resin (after curing of the sealing resin)

図１及び図２は本発明の半導体パッケージの断面模式図である。
半導体パッケージは、多層配線基板３と、多層配線基板３上に複数のはんだバンプ２（バンプ電極）を介して接続された半導体チップ１と、多層配線基板３と半導体チップ１との間に設けられた封止用樹脂４，５とを備えている。
封止用樹脂４，５は、多層配線基板３と半導体チップ１との間隙に充填された第一のチップ封止用樹脂４と、第一のチップ封止用樹脂４の外側で半導体チップ１の外周部とこの外周部に対向する多層配線基板３箇所との間に設けられた第二のチップ封止用樹脂５とを備えている。
第一のチップ封止用樹脂４と第二のチップ封止用樹脂５は互いに異なる弾性率を有している。
あるいは、第一のチップ封止用樹脂４と第二のチップ封止用樹脂５は互いに異なる線膨張係数を有している。
ここで図１の模式図は、封止用樹脂４，５を注入した直後で封止用樹脂４，５の硬化前の状態であり、従って加熱等による反り生じていない状態を示している。本発明では、上記２種類のチップ封止用樹脂４、５の線膨張係数、もしくは硬化後の弾性率がそれぞれ異なることを特徴としている。ここで本発明での弾性率とはヤング率を意味するものとする。以下、本明細書における封止用樹脂の弾性率は、樹脂硬化後のヤング率である。 1 and 2 are schematic cross-sectional views of the semiconductor package of the present invention.
The semiconductor package is provided between the multilayer wiring board 3, the semiconductor chip 1 connected to the multilayer wiring board 3 via a plurality of solder bumps 2 (bump electrodes), and the multilayer wiring board 3 and the semiconductor chip 1. Sealing resins 4 and 5.
The sealing resins 4 and 5 are the first chip sealing resin 4 filled in the gap between the multilayer wiring board 3 and the semiconductor chip 1, and the semiconductor chip 1 outside the first chip sealing resin 4. And a second chip sealing resin 5 provided between the outer peripheral portion of the multilayer wiring board and three multilayer wiring boards facing the outer peripheral portion.
The first chip sealing resin 4 and the second chip sealing resin 5 have different elastic moduli.
Alternatively, the first chip sealing resin 4 and the second chip sealing resin 5 have different linear expansion coefficients.
Here, the schematic diagram of FIG. 1 shows a state immediately after injecting the sealing resins 4 and 5 and before the sealing resins 4 and 5 are cured, and therefore shows a state in which no warp occurs due to heating or the like. The present invention is characterized in that the two types of chip sealing resins 4 and 5 have different linear expansion coefficients or different elastic moduli after curing. Here, the elastic modulus in the present invention means Young's modulus. Hereinafter, the elastic modulus of the sealing resin in this specification is the Young's modulus after resin curing.

各封止用樹脂４，５の材料には公知の絶縁樹脂を用いることが可能である。具体的には、エポキシ樹脂に代表される熱硬化性樹脂を用いることができる。また、封止用樹脂４，５にはシリカ等のフィラーを含有したものを用いることができる。封止用樹脂の弾性率は、同じエポキシ樹脂でも添加物や、架橋の程度、フィラーの割合によっても異なるから、適宜選択することができる。   A known insulating resin can be used as the material of the sealing resins 4 and 5. Specifically, a thermosetting resin typified by an epoxy resin can be used. Moreover, what contains fillers, such as a silica, can be used for resin 4 and 5 for sealing. The elastic modulus of the sealing resin can be selected as appropriate because it varies depending on the additive, the degree of crosslinking, and the proportion of the filler even in the same epoxy resin.

本発明の半導体パッケージにおける多層配線基板３は、任意の多層配線基板を採用することができるが、コア基板を持たない多層配線基板、あるいはコア基板の膜厚が薄い薄コア基板は、剛性が低いためにリフロー時に反りが生じやすいから、本発明において特に効果を発揮する。   As the multilayer wiring board 3 in the semiconductor package of the present invention, an arbitrary multilayer wiring board can be adopted, but a multilayer wiring board without a core board or a thin core board with a thin core board has low rigidity. For this reason, warping is likely to occur during reflow, and this is particularly effective in the present invention.

図２は封止用樹脂４及び５を熱硬化した半導体パッケージの断面模式図であり、図３は、１種類の封止用樹脂６のみ用いて形成された一般的な半導体パッケージの断面模式図であり、半導体チップ１が実装された側と反対の面に反りが生じる場合の例を示している。
図３の半導体パッケージでは、半導体チップ１と封止用樹脂６と多層配線基板３との熱膨張係数の相異により、封止樹脂６を熱硬化させる工程で、半導体チップ１直下部分の多層配線基板３がせり上がり、半導体チップ１が実装された側と反対の面に反りが生じている。
一方、図２に示した本発明の半導体パッケージでは、半導体チップ１の外周部に形成された封止用樹脂５の弾性率が封止用樹脂４の弾性率よりも大きいため、基板温度が低下した際、多層配線基板３を反りとは逆方向に引っ張る力が働き、反りが低減される。
また、封止用樹脂５の線膨張係数が封止用樹脂４の線膨張係数よりも大きい場合も、基板温度が低下した際、多層配線基板５を反りとは逆方向に引っ張る力が働き、反りが低減される。 FIG. 2 is a schematic cross-sectional view of a semiconductor package obtained by thermosetting the sealing resins 4 and 5, and FIG. 3 is a schematic cross-sectional view of a general semiconductor package formed using only one type of sealing resin 6. In this example, the surface opposite to the side on which the semiconductor chip 1 is mounted is warped.
In the semiconductor package of FIG. 3, in the process of thermosetting the sealing resin 6 due to the difference in thermal expansion coefficient among the semiconductor chip 1, the sealing resin 6 and the multilayer wiring board 3, the multilayer wiring in the portion directly under the semiconductor chip 1 The substrate 3 rises and warps on the surface opposite to the side on which the semiconductor chip 1 is mounted.
On the other hand, in the semiconductor package of the present invention shown in FIG. 2, since the elastic modulus of the sealing resin 5 formed on the outer peripheral portion of the semiconductor chip 1 is larger than the elastic modulus of the sealing resin 4, the substrate temperature decreases. In this case, a force that pulls the multilayer wiring board 3 in the direction opposite to the warp works, and the warp is reduced.
Further, when the linear expansion coefficient of the sealing resin 5 is larger than the linear expansion coefficient of the sealing resin 4, when the substrate temperature is lowered, a force that pulls the multilayer wiring board 5 in the direction opposite to the warp works. Warpage is reduced.

本発明の半導体パッケージでは、半導体チップ１と多層配線基板３の間に配置された封止用樹脂４と、半導体チップ１の外周部に配置された封止用樹脂５との弾性率の差が大きいほど、また線膨張係数差が大きいほど反りの低減効果も大きいと考えられ、小さいと充分に応力が働かないため、両封止用樹脂４，５の弾性率の差は１ＧＰａ以上、線膨張係数は２０ｐｐｍ以上であることが好ましい。   In the semiconductor package of the present invention, there is a difference in elastic modulus between the sealing resin 4 disposed between the semiconductor chip 1 and the multilayer wiring board 3 and the sealing resin 5 disposed on the outer peripheral portion of the semiconductor chip 1. The larger the linear expansion coefficient difference is, the greater the effect of reducing warpage is. The smaller the stress is, the smaller the elastic modulus difference between the sealing resins 4 and 5 is 1 GPa or more. The coefficient is preferably 20 ppm or more.

＜実施例＞
以下に本発明による半導体チップ実装方法を、実施例に基づいて説明する。
多層配線基板３として、ポリイミドを絶縁層、銅を配線部とする線膨張係数が２０ｐｐｍの６層基板を用意した。 <Example>
Hereinafter, a semiconductor chip mounting method according to the present invention will be described based on examples.
As the multilayer wiring board 3, a 6-layer board having a linear expansion coefficient of 20 ppm with polyimide as an insulating layer and copper as a wiring part was prepared.

半導体チップ１と多層配線基板３とをはんだバンプ２を介して接合後、封止用樹脂４を半導体チップ１と多層配線基板３間に注入することにより封止した。次に、半導体チップ１外周部を封止用樹脂５で封止した。その後、封止樹脂４，５の熱硬化処理を行った。なお、封止用樹脂４、５はエポキシ系を用い、封止用樹脂４は硬化後の弾性率が９．５ＧＰａ、封止用樹脂５は硬化後の弾性率が１１．０ＧＰａであるものを使用した。   After the semiconductor chip 1 and the multilayer wiring board 3 were joined via the solder bumps 2, the sealing resin 4 was sealed between the semiconductor chip 1 and the multilayer wiring board 3 by injection. Next, the outer periphery of the semiconductor chip 1 was sealed with a sealing resin 5. Then, the thermosetting process of sealing resin 4 and 5 was performed. The sealing resins 4 and 5 use an epoxy system, the sealing resin 4 has an elastic modulus after curing of 9.5 GPa, and the sealing resin 5 has an elastic modulus after curing of 11.0 GPa. used.

以上のような工法により作製した本発明の半導体パッケージの多層配線基板３の平面度を測定したところ１８０μｍであった。   The flatness of the multilayer wiring board 3 of the semiconductor package of the present invention produced by the above method was measured and found to be 180 μm.

また、半導体チップ１と多層配線基板３とをはんだバンプ２を介して接合後、封止用樹脂４を半導体チップ１と多層配線基板３間に注入することにより封止した。次に、半導体チップ外周部１を封止用樹脂５で封止した。その後、封止樹脂４，５の熱硬化処理を行った。なお、封止用樹脂４、５はエポキシ系を用い、封止用樹脂４は線膨張係数が２０ｐｐｍ、封止用樹脂５は線膨張係数が３０ｐｐｍであるものを使用した。   Further, after the semiconductor chip 1 and the multilayer wiring board 3 were joined through the solder bumps 2, the sealing resin 4 was sealed between the semiconductor chip 1 and the multilayer wiring board 3 by injection. Next, the semiconductor chip outer peripheral portion 1 was sealed with a sealing resin 5. Then, the thermosetting process of sealing resin 4 and 5 was performed. The sealing resins 4 and 5 were made of epoxy, and the sealing resin 4 used was a resin having a linear expansion coefficient of 20 ppm, and the sealing resin 5 was a resin having a linear expansion coefficient of 30 ppm.

以上のような工法により作製した本発明の半導体パッケージの多層配線基板３の平面度を測定したところ１６０μｍであった。   The flatness of the multilayer wiring board 3 of the semiconductor package of the present invention produced by the above method was measured and found to be 160 μm.

＜比較例＞
実施例における封止用樹脂４と同一の樹脂材料の一種類の封止用樹脂６のみで封止を行った以外は同様の工程で多層配線基板３上にはんだバンプ２を介して半導体チップ１を実装し、半導体パッケージを作製した。当該半導体パッケージの多層配線基板３の平面度を測定したところ、４００μｍであり、本発明の実施例と比較して２倍以上の反りが生じていた。 <Comparative example>
The semiconductor chip 1 is formed on the multilayer wiring board 3 via the solder bumps 2 in the same process except that the sealing resin 6 is the same as the sealing resin 4 in the embodiment and is sealed with only one kind of the sealing resin 6. A semiconductor package was fabricated. When the flatness of the multilayer wiring board 3 of the semiconductor package was measured, it was 400 μm, and warping more than twice that of the example of the present invention occurred.

１・・・半導体チップ
２・・・はんだバンプ
３・・・多層配線基板
４・・・封止用樹脂
５・・・封止用樹脂
６・・・封止用樹脂 DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2 ... Solder bump 3 ... Multilayer wiring board 4 ... Sealing resin 5 ... Sealing resin 6 ... Sealing resin

Claims (6)

配線基板と、
前記配線基板上に複数のバンプ電極を介して接続された半導体チップと、
前記配線基板と前記半導体チップとの間に設けられた封止用樹脂と、
を備える半導体パッケージであって、
前記封止用樹脂は、前記配線基板と前記半導体チップとの間隙に充填された第一のチップ封止用樹脂と、前記第一のチップ封止用樹脂の外側で前記半導体チップの外周部とこの外周部に対向する前記配線基板箇所との間に設けられた第二のチップ封止用樹脂とを備え、
前記第一のチップ封止用樹脂と前記第二のチップ封止用樹脂は互いに異なる弾性率を有している、
ことを特徴とする半導体パッケージ。 A wiring board;
A semiconductor chip connected via a plurality of bump electrodes on the wiring board;
A sealing resin provided between the wiring substrate and the semiconductor chip;
A semiconductor package comprising:
The sealing resin includes a first chip sealing resin filled in a gap between the wiring board and the semiconductor chip, and an outer peripheral portion of the semiconductor chip outside the first chip sealing resin. A second chip sealing resin provided between the wiring board part facing the outer peripheral part,
The first chip sealing resin and the second chip sealing resin have different elastic moduli,
A semiconductor package characterized by that. 配線基板と、
前記配線基板上に複数のバンプ電極を介して接続された半導体チップと、
前記配線基板と前記半導体チップとの間に設けられた封止用樹脂と、
を備える半導体パッケージであって、
前記封止用樹脂は、前記配線基板と前記半導体チップとの間隙に充填された第一のチップ封止用樹脂と、前記第一のチップ封止用樹脂の外側で前記半導体チップの外周部とこの外周部に対向する前記配線基板箇所との間に設けられた第二のチップ封止用樹脂とを備え、
前記第一のチップ封止用樹脂と前記第二のチップ封止用樹脂は互いに異なる線膨張係数を有している、
ことを特徴とする半導体パッケージ。 A wiring board;
A semiconductor chip connected via a plurality of bump electrodes on the wiring board;
A sealing resin provided between the wiring substrate and the semiconductor chip;
A semiconductor package comprising:
The sealing resin includes a first chip sealing resin filled in a gap between the wiring board and the semiconductor chip, and an outer peripheral portion of the semiconductor chip outside the first chip sealing resin. A second chip sealing resin provided between the wiring board part facing the outer peripheral part,
The first chip sealing resin and the second chip sealing resin have different linear expansion coefficients,
A semiconductor package characterized by that. 前記第二のチップ封止用樹脂は、前記第一のチップ封止用樹脂よりも高い弾性率を有することを特徴とする請求項１又は２記載の半導体パッケージ。   3. The semiconductor package according to claim 1, wherein the second chip sealing resin has a higher elastic modulus than the first chip sealing resin. 4. 前記第二のチップ封止用樹脂は、前記第一のチップ封止用樹脂よりも高い線膨張係数を有することを特徴とする請求項１〜３に何れか１項記載の半導体パッケージ。   4. The semiconductor package according to claim 1, wherein the second chip sealing resin has a higher coefficient of linear expansion than the first chip sealing resin. 5. 前記第二のチップ封止用樹脂と前記第一のチップ封止用樹脂の弾性率の差が１ＧＰａ以上であることを特徴とする請求項１〜４に何れか１項記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein a difference in elastic modulus between the second chip sealing resin and the first chip sealing resin is 1 GPa or more. 前記第二のチップ封止用樹脂と前記第一のチップ封止用樹脂の線膨張係数の差が１０ｐｐｍ以上であることを特徴とする請求項１〜５に何れか１項記載の半導体パッケージ。   6. The semiconductor package according to claim 1, wherein a difference in linear expansion coefficient between the second chip sealing resin and the first chip sealing resin is 10 ppm or more.
JP2009063929A 2008-03-28 2009-03-17 Semiconductor package Pending JP2009260302A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8653676B2 (en) 2011-10-04 2014-02-18 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11220077A (en) * 1997-10-15 1999-08-10 Toshiba Corp Semiconductor device and manufacture of the semiconductor device
JPH11274375A (en) * 1998-03-26 1999-10-08 Mitsubishi Electric Corp Semiconductor device and its manufacture
JP2000164610A (en) * 1998-11-30 2000-06-16 Ngk Spark Plug Co Ltd Semiconductor device and its manufacture
JP2000299414A (en) * 1999-02-12 2000-10-24 Shin Etsu Chem Co Ltd Flip-chip type semiconductor device
JP2006024657A (en) * 2004-07-07 2006-01-26 Matsushita Electric Ind Co Ltd Semiconductor device
JP2007149931A (en) * 2005-11-28 2007-06-14 Renesas Technology Corp Semiconductor device, and method of manufacturing same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11220077A (en) * 1997-10-15 1999-08-10 Toshiba Corp Semiconductor device and manufacture of the semiconductor device
JPH11274375A (en) * 1998-03-26 1999-10-08 Mitsubishi Electric Corp Semiconductor device and its manufacture
JP2000164610A (en) * 1998-11-30 2000-06-16 Ngk Spark Plug Co Ltd Semiconductor device and its manufacture
JP2000299414A (en) * 1999-02-12 2000-10-24 Shin Etsu Chem Co Ltd Flip-chip type semiconductor device
JP2006024657A (en) * 2004-07-07 2006-01-26 Matsushita Electric Ind Co Ltd Semiconductor device
JP2007149931A (en) * 2005-11-28 2007-06-14 Renesas Technology Corp Semiconductor device, and method of manufacturing same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8653676B2 (en) 2011-10-04 2014-02-18 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
US8945985B2 (en) 2011-10-04 2015-02-03 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same

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