JP2009260295A - Soi基板の作製方法 - Google Patents
Soi基板の作製方法 Download PDFInfo
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- JP2009260295A JP2009260295A JP2009061101A JP2009061101A JP2009260295A JP 2009260295 A JP2009260295 A JP 2009260295A JP 2009061101 A JP2009061101 A JP 2009061101A JP 2009061101 A JP2009061101 A JP 2009061101A JP 2009260295 A JP2009260295 A JP 2009260295A
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- single crystal
- crystal semiconductor
- substrate
- semiconductor layer
- insulating film
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- 239000007791 liquid phase Substances 0.000 description 1
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- 239000012071 phase Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
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- 239000013077 target material Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- QQQSFSZALRVCSZ-UHFFFAOYSA-N triethoxysilane Chemical compound CCO[SiH](OCC)OCC QQQSFSZALRVCSZ-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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Abstract
【解決手段】単結晶半導体基板の表面に絶縁膜を形成し、絶縁膜を介して単結晶半導体基板にイオンビームを照射することにより、単結晶半導体基板中に脆化領域を形成し、絶縁膜上に接合層を形成し、接合層を間に挟んで単結晶半導体基板と向かい合うように、支持基板を貼り合わせ、熱処理を行うことにより、脆化領域に沿って単結晶半導体基板を分割して、単結晶半導体層が接着された支持基板と単結晶半導体基板の一部とに分離し、単結晶半導体層に残存する脆化領域に対して第1のドライエッチング処理を行い、第1のエッチング処理が行われた単結晶半導体層の表面に対して、第2のドライエッチング処理を行い、単結晶半導体層に対してレーザ光を照射する。
【選択図】図1
Description
本実施の形態では、単結晶半導体基板を劈開して、単結晶半導体層が接着された支持基板と単結晶半導体基板とに分離し、支持基板に接着された単結晶半導体層の表面に対して第1のエッチング処理及び第2のエッチング処理が行われた単結晶半導体層の表面にレーザ光を照射するSOI基板の製造方法について、図面を参照して説明する。また、本実施の形態では、ガラス基板等耐熱温度が低い基板に単結晶半導体層を設けることを目的の一とするSOI基板の製造方法についても合わせて説明する。
本実施の形態では、実施の形態1で示したSOI基板の構成とは異なるSOI基板の構成を示す。なお、本実施の形態において、上記実施の形態1と同様の部分には同じ符号を付し、詳細な説明を省略する。
本実施の形態では、高性能及び高信頼性な半導体素子を有する半導体装置を、歩留まりよく作製することを目的とした半導体装置の作製方法の一例としてCMOS(相補型金属酸化物半導体:Complementary Metal Oxide Semiconductor)に関して図7及び図8を用いて説明する。なお、実施の形態1及び実施の形態2と同一部分又は同様な機能を有する部分の繰り返しの説明は省略する。
実施の形態3において、TFTの作製方法を説明したが、TFTの他、容量、抵抗などTFTと共に各種の半導体素子を形成することで、高付加価値の半導体装置を作製することができる。以下、図面を参照しながら半導体装置の具体的な態様を説明する。
本実施の形態では、本発明の一形態のSOI基板を用いた表示装置について図11及び図12を参照して説明する。
本発明の一形態に係るSOI基板を用いてトランジスタ等の半導体装置を作製し、この半導体装置を用いてさまざまな電子機器を完成することができる。本発明の一形態に係るSOI基板に設けられた単結晶半導体層は結晶欠陥が低減されているため、活性層として用いることで、電気的特性が向上した半導体素子を製造することができる。また、当該単結晶半導体層は結晶欠陥が低減されているため、ゲート絶縁層との界面において、局在準位密度を低減させることが可能となる。さらに、単結晶半導体層が高い平坦性を有するため、単結晶半導体層上に、薄く、且つ高い絶縁耐圧を有するゲート絶縁層を形成することができ、作製される半導体素子の移動度の向上、S値の向上または短チャネル効果抑制を実現することができる。すなわち、本発明の一形態に係るSOI基板を用いることで、電流駆動能力が高く、かつ信頼性の高い半導体素子を作製することが可能になる。その結果、最終製品としての電子機器をスループット良く、良好な品質で作製することができる。この半導体素子を用いて、さまざまな半導体装置を作製することができる。本実施の形態では、図面を用いて具体的な例を説明する。なお、本実施の形態において、上記実施の形態と同様の部分には同じ符号を付し、詳しい説明を省略する。
102 絶縁膜
102a 絶縁膜
102b 絶縁膜
103 イオンビーム
104 脆化領域
105 絶縁膜
106 単結晶半導体基板
107 レーザ光
111 支持基板
112 単結晶半導体層
113 自然酸化膜
114 自然酸化膜
115 絶縁膜
205 単結晶半導体層
206 単結晶半導体層
207 ゲート絶縁層
208 ゲート電極層
209 ゲート電極層
210 不純物元素
211 マスク
212a n型不純物領域
213 不純物元素
214 マスク
215a p型不純物領域
215b p型不純物領域
216a 側壁絶縁層
216c 側壁絶縁層
217 不純物元素
218 マスク
219a n型不純物領域
219b n型不純物領域
220a n型不純物領域
221 チャネル形成領域
222 不純物元素
223 マスク
224a p型不純物領域
225a p型不純物領域
226 チャネル形成領域
227 絶縁膜
228 絶縁層
229a 配線層
231 薄膜トランジスタ
232 薄膜トランジスタ
302 単結晶半導体層
320 単結晶半導体層
322 走査線
323 信号線
324 画素電極
325 TFT
327 層間絶縁膜
328 電極
329 柱状スペーサ
330 配向膜
332 対向基板
333 対向電極
233a ゲート絶縁層
334 配向膜
335 液晶層
340 チャネル形成領域
341 高濃度不純物領域
401 選択用トランジスタ
402 表示制御用トランジスタ
403 半導体膜
404 半導体膜
405 走査線
406 信号線
407 電流供給線
408 画素電極
410 電極
411 電極
412 ゲート電極
413 電極
427 層間絶縁膜
428 隔壁層
429 EL層
430 対向電極
431 対向基板
432 樹脂層
451 チャネル形成領域
452 高濃度不純物領域
500 マイクロプロセッサ
501 演算回路
502 演算回路制御部
503 命令解析部
504 制御部
505 タイミング制御部
506 レジスタ
507 レジスタ制御部
508 バスインターフェース
509 専用メモリ
510 メモリインターフェース
511 RFCPU
512 アナログ回路部
513 デジタル回路部
514 共振回路
515 整流回路
516 定電圧回路
517 リセット回路
518 発振回路
519 復調回路
520 変調回路
521 RFインターフェース
522 制御レジスタ
523 クロックコントローラ
524 インターフェース
525 中央処理ユニット
526 ランダムアクセスメモリ
527 専用メモリ
528 アンテナ
529 容量部
530 電源管理回路
700 携帯電話
701 筐体
702 筐体
703 表示部
704 スピーカ
705 マイクロフォン
706 操作キー
707 ポインティングデバイス
708 カメラ用レンズ
709 外部接続端子
710 イヤホン端子
711 キーボード
712 外部メモリスロット
713 裏面カメラ
714 ライト
901 筐体
902 支持台
903 表示部
904 スピーカ部
905 ビデオ入力端子
911 筐体
912 表示部
913 キーボード
914 外部接続ポート
915 ポインティングデバイス
921 筐体
922 表示部
923 操作キー
924 センサ部
931 筐体
932 表示部
933 レンズ
934 操作キー
935 シャッターボタン
941 本体
942 表示部
943 筐体
944 外部接続ポート
945 リモコン受信部
946 受像部
947 バッテリー
948 音声入力部
949 操作キー
950 接眼部
Claims (4)
- 単結晶半導体基板の表面に絶縁膜を形成し、
前記絶縁膜を介して前記単結晶半導体基板にイオンビームを照射することにより、前記単結晶半導体基板中に脆化領域を形成し、
前記絶縁膜上に接合層を形成し、
前記接合層を間に挟んで前記単結晶半導体基板と向かい合うように、支持基板を貼り合わせ、
熱処理を行うことにより、前記脆化領域に沿って前記単結晶半導体基板を分割して、単結晶半導体層が接着された前記支持基板と単結晶半導体基板の一部とに分離し、
前記単結晶半導体層に残存する脆化領域に対して第1のドライエッチング処理を行い、
前記第1のエッチング処理が行われた前記単結晶半導体層の表面に対して、第2のドライエッチング処理を行い、
前記単結晶半導体層に対してレーザ光を照射することを特徴とするSOI基板の作製方法。 - 単結晶半導体基板の表面に絶縁膜を形成し、
前記絶縁膜を介して前記単結晶半導体基板にイオンビームを照射することにより、前記単結晶半導体基板中に脆化領域を形成し、
前記絶縁膜上に接合層を形成し、
前記接合層を間に挟んで前記単結晶半導体基板と向かい合うように、支持基板を貼り合わせ、
熱処理を行うことにより、前記脆化領域に沿って前記単結晶半導体基板を分割して、単結晶半導体層が接着された前記支持基板と単結晶半導体基板の一部とに分離し、
前記単結晶半導体層に残存する脆化領域を第1のドライエッチング処理により除去し、
前記単結晶半導体層表面に形成された酸化膜を第2のドライエッチング処理により除去し、
前記酸化膜が除去された単結晶半導体層に対してレーザ光を照射することを特徴とするSOI基板の作製方法。 - 請求項1又は請求項2において、
第1のエッチング処理は、前記単結晶半導体層表面に形成された酸化膜を除去した後に、前記酸化膜が除去された単結晶半導体層に残存する脆化領域を除去することで行うことを特徴とするSOI基板の作製方法。 - 請求項1乃至請求項3のいずれか一において、
レーザ光を照射した後に、薄膜化処理を行うことを特徴とするSOI基板の作製方法。
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US8003483B2 (en) | 2011-08-23 |
US8383487B2 (en) | 2013-02-26 |
US20110287605A1 (en) | 2011-11-24 |
JP5486828B2 (ja) | 2014-05-07 |
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