JP2009164208A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Semiconductor device and manufacturing method of semiconductor device Download PDF

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JP2009164208A
JP2009164208A JP2007339952A JP2007339952A JP2009164208A JP 2009164208 A JP2009164208 A JP 2009164208A JP 2007339952 A JP2007339952 A JP 2007339952A JP 2007339952 A JP2007339952 A JP 2007339952A JP 2009164208 A JP2009164208 A JP 2009164208A
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layer
semiconductor device
connection
paste
gap
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Goro Ideta
吾朗 出田
Katsuaki Suganuma
克昭 菅沼
Keunsoo Kim
槿銖 金
Doseop Kim
道燮 金
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To suppress formation of a void as a connection defect caused by trapping of a gas in a connection layer by eliminating the need of working, such as, grooving on the reverse surface of a semiconductor element, even when a semiconductor is connected using a conductive adhesive producing an extremely large amount of gas. <P>SOLUTION: A connection layer for connecting the semiconductor element 1 and a base material 2c has a laminated structure of an air gap layer 13 and a bonding layer 7, and consequently, a gas can be dissipated efficiently d to the outside of the connection layer in a process of connection. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置および半導体装置の製造方法に関し、より特定的には実装時の加熱により接続層に発生し、半導体装置の動作特性に影響を与えうる接続欠陥の発生を抑制する半導体装置および半導体装置の製造方法に関する。   The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly, a semiconductor device that suppresses generation of a connection defect that occurs in a connection layer due to heating during mounting and can affect the operating characteristics of the semiconductor device, and The present invention relates to a method for manufacturing a semiconductor device.

昨今、ＲｏＨＳ指令に対応して、電子機器の基板実装における鉛フリー化が進展している。高耐熱性が要求されるために鉛含有はんだの使用が継続されている、半導体パッケージ組立における内部接続用の金属材料にも、鉛フリー化が求められつつある。   In recent years, in response to the RoHS directive, lead-free electronic board mounting is progressing. The use of lead-containing solder for which high heat resistance is required has continued to require lead-free metal materials for internal connection in semiconductor package assembly.

しかし、基板実装時の加熱に対する耐熱性を持ち、かつ半導体素子の特性を損なわない４００℃未満の温度で接合が可能な鉛フリー金属材料は、現時点では見出されていない。半導体素子を、それを固定するための基材に搭載する際には、一般に金属として銀を含むペースト（銀ペースト）等の導電性接着剤がボンディング材料として用いられている。   However, no lead-free metal material that can be bonded at a temperature of less than 400 ° C. that has heat resistance to heating during mounting on the substrate and does not impair the characteristics of the semiconductor element has not been found at present. When a semiconductor element is mounted on a base material for fixing it, a conductive adhesive such as a paste containing silver as a metal (silver paste) is generally used as a bonding material.

上述の例では、銀ペースト等の導電性接着剤を用いて、半導体素子を固定するための基材に半導体素子をダイボンディングする。その方法は、基材の一方の主表面上に銀ペースト等の導電性接着剤を塗布した後、塗布した導電性接着剤の上層側に固定させたい半導体素子を重ね、導電性接着剤中の溶剤を加熱によって気化させて除去することにより接続するといったものである。   In the above example, the semiconductor element is die-bonded to a base material for fixing the semiconductor element using a conductive adhesive such as silver paste. In that method, after applying a conductive adhesive such as silver paste on one main surface of the substrate, a semiconductor element to be fixed on the upper layer side of the applied conductive adhesive is stacked, The connection is made by evaporating and removing the solvent by heating.

接着時の加熱により銀ペースト中に含まれる溶剤が気化するために多量のガス（アウトガス）が発生する。このアウトガスが、接続層内部に貯留すると大きな接続欠陥であるボイドを生じる。そのため、実装させたい半導体素子と接続層との接着面積が大幅に減少する結果、接着強度を低下させる可能性がある。また、ボイドが大きくなると、ボイド部分には電流や熱が流れることができないため、局所的に電気抵抗や熱抵抗が高まることになる。その結果、ボイドの上部や周辺部分において半導体素子の温度が上昇してしまう可能性がある。   A large amount of gas (outgas) is generated because the solvent contained in the silver paste is vaporized by heating at the time of bonding. When this outgas is stored inside the connection layer, a void which is a large connection defect is generated. Therefore, the adhesion area between the semiconductor element to be mounted and the connection layer is greatly reduced, and as a result, the adhesion strength may be lowered. In addition, when the void becomes large, current and heat cannot flow through the void portion, so that electric resistance and thermal resistance are locally increased. As a result, there is a possibility that the temperature of the semiconductor element rises in the upper part of the void and in the peripheral part.

この問題を解決するために、半導体素子の、基材と固定させる際に接着させる一方の接続面に溝加工を施す。すると、この溝が、接続層の溶剤を気化させて除去する際に発生するアウトガスの放散通路として機能するため、アウトガスが接続層内部に貯留するのを防ぎ、接続欠陥の発生量を低減するといった手法がある。この手法は、たとえば特開平０６−３１４７１８号公報「半導体集積回路ペレット」に記載されている。
特開平０６−３１４７１８号公報 In order to solve this problem, a groove is formed on one connection surface of the semiconductor element to be bonded when the semiconductor element is fixed to the substrate. Then, since this groove functions as a diffusion path for the outgas generated when the solvent of the connection layer is vaporized and removed, it prevents the outgas from being stored inside the connection layer, and reduces the generation amount of connection defects. There is a technique. This technique is described in, for example, “Semiconductor integrated circuit pellet” of Japanese Patent Laid-Open No. 06-314718.
Japanese Patent Laid-Open No. 06-314718

しかしながら、銀ペーストを鉛フリーの半導体接続材料の候補にすると、電気抵抗率が高いため、やはり発熱が大きくなる問題や、電気特性の低下を招く可能性がある問題を抱えている。そこで、銀ナノ粒子を応用した接続技術が開発され始めている。しかし、これに対して上述の、半導体素子の接続面に溝加工を施して加熱時に発生するアウトガスを放出する方法を採用しようとしても、放出しきれないという問題がある。これは以下の理由によると考えられる。すなわち、一般的な銀ペーストの場合、接続層を形成する接着剤の役割を持つ銀ペースト中の溶剤の比率は５０ｖｏｌ％程度であるため、アウトガスの放出も比較的容易に行なえる。ところが、金属ナノ粒子を含むペーストの場合は、金属成分の存在比率が１０ｖｏｌ％程度と少なく、ペースト成分のほとんどがガス化して放散される。このため、半導体素子の接続面に部分的に施した溝のみでは十分なガス放散経路を確保できない。このことにより、発生したガスを除去しきれず、接続層内部に接続欠陥としてのボイドとして残存してしまうのである。   However, when silver paste is used as a lead-free candidate for a semiconductor connection material, it has a high electrical resistivity, so that it also has a problem of increasing heat generation and a possibility of causing a decrease in electrical characteristics. Therefore, connection technology using silver nanoparticles has been developed. However, there is a problem that even if it is attempted to adopt the above-described method of grooving the connection surface of the semiconductor element to release the outgas generated during heating, the semiconductor element cannot be released. This is considered to be due to the following reason. That is, in the case of a general silver paste, since the ratio of the solvent in the silver paste having the role of an adhesive forming the connection layer is about 50 vol%, outgas can be released relatively easily. However, in the case of a paste containing metal nanoparticles, the abundance ratio of the metal component is as low as about 10 vol%, and most of the paste component is gasified and diffused. For this reason, it is not possible to ensure a sufficient gas diffusion path only with the grooves partially formed on the connection surface of the semiconductor element. As a result, the generated gas cannot be removed and remains as a void as a connection defect inside the connection layer.

本発明は上述の問題に鑑みなされたものである。その目的は、半導体素子と基材との接続を行なう場合において、接続層内部にトラップされて形成される接続欠陥としてのボイドの発生を抑制する、半導体装置およびその製造方法を提供することである。   The present invention has been made in view of the above problems. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that suppress the generation of voids as connection defects formed by being trapped inside the connection layer when the semiconductor element and the base material are connected. .

本発明の半導体装置は、主表面を有する基材と、半導体素子と、基材と半導体素子との間にこれらを接続するための、接続層とを備える。その接続層は、その中に連続した空隙が存在する空隙層と、空隙層中よりも連続した空隙が相対的に少ない接合層とを含んだ積層体である。また、上述の半導体装置の製造方法としては、主表面を有する基材を準備する工程と、基材の主表面上に接続層を介して半導体素子を接続する工程とを備える。そして上述の半導体素子を接続する工程は、接続層を形成する工程を含み、接続層を形成する工程には、上述の空隙層を形成する工程と、空隙層と積層される上述の接合層を形成する工程とをさらに含むことを特徴とする。   The semiconductor device of the present invention includes a base material having a main surface, a semiconductor element, and a connection layer for connecting them between the base material and the semiconductor element. The connection layer is a laminate including a void layer having continuous voids therein and a bonding layer having relatively fewer continuous voids than in the void layer. Moreover, as a manufacturing method of the above-mentioned semiconductor device, the process of preparing the base material which has a main surface, and the process of connecting a semiconductor element via a connection layer on the main surface of a base material are provided. The step of connecting the semiconductor element includes a step of forming a connection layer, and the step of forming the connection layer includes the step of forming the above-described void layer and the above-described bonding layer laminated with the void layer. And a forming step.

本発明における、接続層として空隙層と接合層とを形成しながら接続を行なうといった半導体装置の製造方法によれば、アウトガスの発生が極めて多量なペーストである導電性接着剤を用いて半導体素子の接続を行なう場合においても、半導体素子の裏面に溝加工などの加工が不要である。その結果、本発明における製造方法にて製造した、接続層として連続した空隙が存在する空隙層と、連続した空隙が空隙層よりも相対的に少ない接合層とを含んだ構造を備える半導体装置は、接合層にアウトガスがトラップされている可能性を小さくすることができる。   According to the manufacturing method of a semiconductor device in which the connection is performed while forming the gap layer and the bonding layer as the connection layer in the present invention, the conductive element of the semiconductor element is formed by using the conductive adhesive which is a paste with a very large amount of outgas generation. Even in the case of connection, it is not necessary to perform groove processing or the like on the back surface of the semiconductor element. As a result, a semiconductor device that is manufactured by the manufacturing method according to the present invention and has a structure including a void layer in which continuous voids exist as connection layers and a bonding layer in which the continuous voids are relatively smaller than the void layer. The possibility that outgas is trapped in the bonding layer can be reduced.

以下、図面を参照しながら、本発明の実施の形態が説明される。なお、各実施の形態において、同一の機能を果たす部位には同一の参照符号が付されており、その説明は、特に必要がなければ、繰り返さない。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each embodiment, portions having the same function are denoted by the same reference numerals, and the description thereof will not be repeated unless particularly necessary.

（実施の形態１）
図１は、本発明の実施の形態１における半導体装置の配置を示すための、接続工程完了前の状態を示す概略図である。また、図２は、本発明の実施の形態１における半導体装置の構成を示すための、接続工程完了後の状態を示す概略図である。本発明の実施の形態１における半導体装置１００ｂは、半導体素子１を基材２に接続するための接続層が、空隙層１３と、接合層７との積層構造となっていることが特徴である。また、本発明の実施の形態１における半導体装置１００ｂの製造方法では、まず、基材２の一方の主表面上に空隙層１３を形成する。そして、空隙層１３の、基材２と反対側の主表面上に、図１にて半導体装置の固定前の構造１００ａが示すように、工程完了後に接合層７となるペースト６を供給する。これにより、図２に示すように、半導体素子１と基材２とを接続する接続層として、空隙層１３と接合層７とが、半導体素子１から基材２に向かう方向に見ると互いに隣接する積層構造を形成することができる。 (Embodiment 1)
FIG. 1 is a schematic diagram showing a state before completion of a connection process for showing the arrangement of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a schematic diagram showing the state after the completion of the connection process for showing the configuration of the semiconductor device according to the first embodiment of the present invention. The semiconductor device 100b according to the first embodiment of the present invention is characterized in that the connection layer for connecting the semiconductor element 1 to the base material 2 has a laminated structure of the gap layer 13 and the bonding layer 7. . In the method for manufacturing the semiconductor device 100b according to the first embodiment of the present invention, first, the void layer 13 is formed on one main surface of the substrate 2. Then, on the main surface of the gap layer 13 opposite to the base member 2, as shown in the structure 100a before fixing the semiconductor device in FIG. As a result, as shown in FIG. 2, the gap layer 13 and the bonding layer 7 are adjacent to each other when viewed in the direction from the semiconductor element 1 to the base 2 as a connection layer for connecting the semiconductor element 1 and the base 2. A laminated structure can be formed.

このような製造方法を用いることにより、次に述べるような効果が考えられる。すなわち、工程完了後に接合層７となるペースト６に含まれる溶剤の気化により発生したアウトガスは、ペースト６に隣接する配置となっている、上述の空隙層１３の内部の空隙を通路として移動できる。その結果、空隙層１３の外部にアウトガスを放出させることが可能となる。   By using such a manufacturing method, the following effects can be considered. That is, the outgas generated by the vaporization of the solvent contained in the paste 6 that becomes the bonding layer 7 after the completion of the process can move using the voids inside the above-described void layer 13 arranged adjacent to the paste 6 as a passage. As a result, it is possible to discharge outgas to the outside of the gap layer 13.

上述の連続した空隙は、その幅が最大およそ１０μｍのもので、空隙層１３とはたとえば、平均粒径が１μｍの銀の粉と平均粒径が０．１μｍの銀の粉とを結合材としての揮発性溶剤とともに混合させることにより準備したペースト６を加熱、たとえば焼結させることにより固化させて生成した、厚さが１０μｍの接続層の一部である。この空隙層１３の内部には、接続層の端部まで連続した空隙が多数存在することになる。なお、上述のとおり、連続した空隙の幅を最大およそ１０μｍ以下となるように形成することにより、上述の連続した空隙が、接続時における熱抵抗の原因となることを抑制する。直径が１０μｍ以下の空隙であれば局所的なヒートスポット発生の原因にはならないと考えられる。   The above-mentioned continuous voids have a maximum width of about 10 μm, and the void layer 13 is made of, for example, silver powder having an average particle diameter of 1 μm and silver powder having an average particle diameter of 0.1 μm as a binder. This is a part of the connecting layer having a thickness of 10 μm formed by solidifying the paste 6 prepared by mixing together with the volatile solvent of, for example, heating, sintering. A large number of voids that continue to the end of the connection layer exist inside the void layer 13. Note that, as described above, the continuous gap is formed to have a maximum width of about 10 μm or less, thereby suppressing the above-described continuous gap from causing thermal resistance at the time of connection. It is considered that a void having a diameter of 10 μm or less does not cause local heat spot generation.

また、本発明の実施の形態１における半導体装置１００ｂにおいては、空隙層１３の厚さが、接合層７の厚さよりも大きいことが好ましい。これは、接続時にペースト６に含まれる結合材としての溶剤が、気化する際に発生するアウトガスの通路としての連続した空隙は、その有効面積が大きいほど効率よくアウトガスを外部に放散できる。したがって、空隙層１３の厚さを接合層７の厚さよりも大きくしておくことが好ましい。   In the semiconductor device 100b according to the first embodiment of the present invention, the thickness of the gap layer 13 is preferably larger than the thickness of the bonding layer 7. This is because, as the effective area of a continuous void as a passage of outgas generated when the solvent as the binder contained in the paste 6 is vaporized at the time of connection, the outgas can be efficiently diffused to the outside. Therefore, it is preferable to make the thickness of the gap layer 13 larger than the thickness of the bonding layer 7.

また、本発明の実施の形態１における半導体装置１００ｂは、空隙層１３と接合層７とがそれぞれ１層ずつ存在する２層のみの構造となっている。   In addition, the semiconductor device 100b according to the first embodiment of the present invention has a structure of only two layers in which the gap layer 13 and the bonding layer 7 are each one layer.

また、本発明の実施の形態１における半導体装置１００ｂは、接続層を形成する金属粉の材料に関して、銀、金または銅を成分に含めている。半導体素子１と基材２とを良好に接続させるためには、上述の材料の金属粉を用いることが好ましい。   Moreover, the semiconductor device 100b in Embodiment 1 of this invention contains silver, gold | metal | money, or copper in the component regarding the material of the metal powder which forms a connection layer. In order to connect the semiconductor element 1 and the base material 2 satisfactorily, it is preferable to use the metal powder of the above-described material.

また、上述の銀、金、銅のいずれかを含む組成により構成される金属粉は、少なくとも一部の平均粒径が０．１μｍ以下であり、かつ、接続層を形成するペースト６中における金属粉の存在比率が５ｖｏｌ％以上３０ｖｏｌ％以下と、従来より小さい割合で構成することを特徴とする。また、金属粉の粒径が０．１μｍ以下になると、低温焼成が可能となるといった効果を生むことができる。すなわち、ミクロンオーダーの一般的なサイズの金属粉を用いる場合の融点よりも低い温度にて金属粉が溶融するようになる特別な現象が起こる。そのため、上述のとおり、ペースト６を構成する金属粉は少なくとも一部の粒径を０．１μｍ以下にすることが好ましい。   Moreover, the metal powder comprised by the composition containing any one of the above-mentioned silver, gold | metal | money, copper is a metal in the paste 6 which has at least one part average particle diameter of 0.1 micrometer or less, and forms a connection layer. It is characterized in that the abundance ratio of the powder is 5 vol% or more and 30 vol% or less, which is smaller than the conventional ratio. Moreover, when the particle size of the metal powder is 0.1 μm or less, an effect that low-temperature firing is possible can be produced. That is, a special phenomenon occurs in which the metal powder is melted at a temperature lower than the melting point when a metal powder having a general size of the micron order is used. Therefore, as described above, it is preferable that at least a part of the metal powder constituting the paste 6 has a particle size of 0.1 μm or less.

半導体素子１は、たとえばＩＧＢＴ（Insulated Gate Bipolar Transistor)やＭＯＳＦＥＴ(Metal Oxide Semiconductor Field Effect Transistor）やバイポーラトランジスタなどの集積回路である。また、基材２は、たとえば半導体素子１と基板とを機械的に接続する役割を果たすリードフレームや、セラミック基板、樹脂のプリント基板などである。   The semiconductor element 1 is an integrated circuit such as an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a bipolar transistor. The base material 2 is, for example, a lead frame that serves to mechanically connect the semiconductor element 1 and the substrate, a ceramic substrate, a resin printed substrate, or the like.

図３は、本発明の実施の形態１における半導体装置の製造方法を示すフローチャートである。図４は、基材の一方の主表面上に、空隙層を形成させるためにペーストを供給した状態を示す概略図である。また、図５は、基材の一方の主表面上に、空隙層を形成させる系を加熱した状態を示す概略図である。続いて、本実施の形態における半導体装置の製造方法について、図３、図４、図５および上述の図１および図２を用いて説明する。   FIG. 3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a schematic view showing a state in which paste is supplied to form a void layer on one main surface of the substrate. FIG. 5 is a schematic view showing a heated state of a system for forming a void layer on one main surface of the substrate. Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIGS. 3, 4, and 5 and FIGS. 1 and 2 described above.

まず、上述のとおり、予め基材２の一方の主表面上に、空隙層１３を形成しておく。その方法としてはまず、ペーストの準備工程（Ｓ３１）を行なう。具体的にはたとえば、平均粒径１μｍの銀の粉および平均粒径０．１μｍの銀の粉の混合粉を揮発性溶剤と混合したペースト６を準備する。次にこのペーストの基材への供給工程（Ｓ３２）を実施する。具体的にはペースト６を、図４に示すように基材２の一方の主表面上に供給する。そのうえで、空隙層の形成（Ｓ３３）を行なう。これは図５に示すように、たとえば加熱して溶剤を揮発させて銀の粉を焼結させることにより、上述のペースト６を空隙層１３とさせる。この空隙層１３の主表面上には障害物が存在しないため、溶剤を揮発させる際に発生したガスは空隙層１３の上方に自由に放散される。この結果、この空隙層１３にはガスが放散された軌跡として、連続した空隙が形成されることになる。   First, as described above, the gap layer 13 is formed in advance on one main surface of the substrate 2. First, a paste preparation step (S31) is performed. Specifically, for example, a paste 6 is prepared by mixing a mixed powder of silver powder having an average particle diameter of 1 μm and silver powder having an average particle diameter of 0.1 μm with a volatile solvent. Next, a supply step (S32) of this paste to the base material is performed. Specifically, the paste 6 is supplied onto one main surface of the substrate 2 as shown in FIG. Then, a void layer is formed (S33). As shown in FIG. 5, for example, the paste 6 is made into the gap layer 13 by heating to volatilize the solvent and sinter the silver powder. Since there are no obstacles on the main surface of the void layer 13, the gas generated when the solvent is volatilized is freely dissipated above the void layer 13. As a result, continuous voids are formed in the void layer 13 as a trajectory in which gas is diffused.

空隙層１３を形成した後、接合層７を形成することにより、接続層を形成する。そのために、上述した空隙層１３の形成に続いてペーストの空隙層表面上への供給工程（Ｓ３４）を行なう。これは具体的には、上述の空隙層１３の、基材２と反対側の主表面上に、たとえば、先に準備した平均粒径１μｍの銀の粉と平均粒径０．１μｍの銀の粉との混合粉を揮発性溶剤と混合したペースト６を供給する。なお、ここで半導体素子１の基材２と対向する表面上にペースト６を供給しても良い。ここで、銀の粉の粒径は少なくとも一部が０．１μｍであればよく、たとえば平均粒径１μｍの銀の粉と混合させずに平均粒径０．１μｍの銀の粉のみを金属粉として準備してペースト６を形成することも可能である。また、ペースト６を供給する量は、先のペーストの基材への供給工程（Ｓ３２）にて供給したペーストの量よりも少ないことが好ましい。このことにより、効率よくアウトガスを外部に放散することができる。次に、半導体素子と基材との重ね合わせ工程（Ｓ３５）に進む。これは上述のペースト６を供給した面の上に半導体素子１を重ね合わせるという工程である。最後に加熱による接続工程（Ｓ３６）を行なう。すなわち加熱してペースト６に含まれる溶剤を揮発させて銀の粉を焼結させ、接合層７を形成するものである。以上の工程により、図２における１００ｂに示すような構成の半導体装置の製造が完了する。   After forming the gap layer 13, the bonding layer 7 is formed to form a connection layer. For this purpose, a paste supplying step (S34) onto the surface of the void layer is performed following the formation of the void layer 13 described above. Specifically, on the main surface on the opposite side of the base material 2 of the above-described gap layer 13, for example, silver powder having an average particle diameter of 1 μm and silver having an average particle diameter of 0.1 μm previously prepared are used. A paste 6 obtained by mixing powder mixed with powder with a volatile solvent is supplied. In addition, you may supply the paste 6 on the surface facing the base material 2 of the semiconductor element 1 here. Here, the particle size of the silver powder may be at least partially 0.1 μm. For example, only silver powder having an average particle size of 0.1 μm is mixed with metal powder without mixing with silver powder having an average particle size of 1 μm. It is also possible to prepare the paste 6 to be prepared as follows. Moreover, it is preferable that the quantity which supplies the paste 6 is less than the quantity of the paste supplied in the supply process (S32) to the base material of the previous paste. As a result, the outgas can be efficiently diffused to the outside. Next, it progresses to the superimposition process (S35) of a semiconductor element and a base material. This is a process of superposing the semiconductor element 1 on the surface supplied with the paste 6 described above. Finally, a connection step by heating (S36) is performed. That is, the bonding layer 7 is formed by heating and volatilizing the solvent contained in the paste 6 to sinter the silver powder. Through the above-described steps, the manufacture of the semiconductor device having the configuration as indicated by 100b in FIG. 2 is completed.

なお、本実施の形態１において、半導体素子１と基材２とを工程（Ｓ３５）にて重ね合わせる際に、供給したペースト６の一部が半導体素子１や空隙層１３の端部からはみ出すことが考えられる。図６は、供給したペーストの一部が重ね合わせの際にはみ出した場合の、接続工程完了後の半導体装置の外観を示す概略図である。加熱による接続工程（Ｓ３６）を行なうことにより、図６の半導体装置の構成１００ｂに示すように接合層７の一部が半導体素子１や空隙層１３の主表面に対してはみ出した状態となる場合がある。しかし、ペースト６のはみ出した部分の加熱により形成された接合層７の端部が、空隙層１３の側面の全面を覆わない限り、空隙層１３の側面のうち、接合層７の端部に覆われていない箇所に存在する連続した空隙を通って、アウトガスを放散させることが可能である。   In the first embodiment, when the semiconductor element 1 and the base material 2 are superposed in the step (S35), a part of the supplied paste 6 protrudes from the end of the semiconductor element 1 or the gap layer 13. Can be considered. FIG. 6 is a schematic view showing the external appearance of the semiconductor device after the connection process is completed when a part of the supplied paste protrudes during superposition. When the connecting step (S36) by heating is performed, a part of the bonding layer 7 protrudes from the main surfaces of the semiconductor element 1 and the gap layer 13 as shown in the configuration 100b of the semiconductor device in FIG. There is. However, unless the end of the bonding layer 7 formed by heating the protruding portion of the paste 6 covers the entire side surface of the gap layer 13, the end of the bonding layer 7 is covered among the side surfaces of the gap layer 13. It is possible to dissipate the outgas through continuous voids present at undisclosed locations.

ここでは、銀の粉を焼結させて接続層を形成する場合について述べたが、これに限るものではなく、上述のとおり、金や銅の粉を用いた場合や、銀、金、または銅の粉を金属粉の組成に含ませた場合でも良好な接続ができ、同様の効果を得ることができる。また、金属粉の平均粒径についても上述の数値に限るものではなく、任意の粒径を使用可能である。また、金属粉の少なくとも一部の粒径を０．１μｍ以下となるように準備することがさらに好ましい。少なくとも一部の粒径を０．１μｍ以下とすることにより、上述のとおり、低温焼成が可能となるといった効果を生むことができる。すなわち、ミクロンオーダーの一般的なサイズの金属粉を用いる場合の融点よりも低い温度にて金属粉が溶融するようになる特別な現象が起こる。   Here, the case where the silver powder is sintered to form the connection layer is described. However, the present invention is not limited to this, and as described above, when gold or copper powder is used, silver, gold, or copper is used. Even when this powder is included in the composition of the metal powder, good connection can be made and the same effect can be obtained. Further, the average particle size of the metal powder is not limited to the above-mentioned numerical value, and any particle size can be used. Moreover, it is more preferable to prepare at least a part of the particle size of the metal powder to be 0.1 μm or less. By setting at least a part of the particle size to 0.1 μm or less, it is possible to produce an effect that low-temperature firing is possible as described above. That is, a special phenomenon occurs in which the metal powder is melted at a temperature lower than the melting point when a metal powder having a general size of the micron order is used.

また、本発明の実施の形態１においては、空隙層１３と接合層７との２層のみからなる構造としている。後述のように、空隙層１３と接合層７とが３層以上ずつ接続した状態からなる多層構造であっても良い。ただし、本発明の実施の形態１のように２層のみからなる構造にすることにより、工程がシンプルになり、コスト的に有利にすることができる。   In the first embodiment of the present invention, the structure is composed of only two layers of the gap layer 13 and the bonding layer 7. As will be described later, it may be a multilayer structure in which the gap layer 13 and the bonding layer 7 are connected by three or more layers. However, by using a structure composed of only two layers as in the first embodiment of the present invention, the process can be simplified and the cost can be improved.

（実施の形態２）
図７は、本発明の実施の形態２における半導体装置の配置を示すための、接続工程完了前の状態を示す概略図である。また、図８は、本発明の実施の形態２における半導体装置の構成を示すための、接続工程完了後の状態を示す概略図である。本実施の形態２における半導体装置は、図７に半導体装置の固定前の構造１００ａとして示すように、基本的には実施の形態１における半導体装置と同様の構成を備えている。しかし、本実施の実施の形態２における半導体装置１００ｂの配置は、接続層を構成する、空隙層１３と接合層７とを合計３層以上積層するとともに、接合層７の主表面のうち少なくとも一方が空隙層１３と隣接する多層構造を形成していることを特徴とする。したがって、図８に半導体装置の構成１００ｂとして示すように空隙層１３が、接合層７の一方の主表面上と、同じく接合層７の他方の主表面上の両方の面上に存在する構成となっている点においてのみ、実施の形態１と異なる。 (Embodiment 2)
FIG. 7 is a schematic diagram showing a state before the connection process is completed, for illustrating the arrangement of the semiconductor device according to the second embodiment of the present invention. FIG. 8 is a schematic diagram showing a state after the completion of the connection process for showing the configuration of the semiconductor device according to the second embodiment of the present invention. The semiconductor device according to the second embodiment basically has the same configuration as that of the semiconductor device according to the first embodiment, as shown as a structure 100a before fixing the semiconductor device in FIG. However, the arrangement of the semiconductor device 100b according to the second embodiment is such that at least one of the main surfaces of the bonding layer 7 is formed by laminating a total of three or more void layers 13 and bonding layers 7 constituting the connection layer. Forms a multilayer structure adjacent to the gap layer 13. Therefore, as shown as a semiconductor device configuration 100b in FIG. 8, the gap layer 13 is present on one main surface of the bonding layer 7 and on both surfaces of the other main surface of the bonding layer 7. This is different from the first embodiment only in this point.

本実施の実施の形態２における半導体装置の構成１００ｂは、特に図８に示すように、空隙層１３が２層存在し、２つの空隙層１３に挟まれるように、接合層７が配置されており、合計３層の接続層を構成している。   In the configuration 100b of the semiconductor device according to the second embodiment, in particular, as shown in FIG. 8, there are two gap layers 13 and the bonding layer 7 is arranged so as to be sandwiched between the two gap layers 13. Thus, a total of three connection layers are formed.

本実施の形態２における半導体装置の製造方法は、基本的には実施の形態１における半導体装置の製造方法と同様のステップを備えている。しかし、空隙層１３を、半導体素子１の一方の主表面上と、基材２の一方の主表面上との両方に予め形成させる。それら２つの空隙層１３を接合層７で接続することにより、合計３層の接続層を形成するステップが存在する点においてのみ、実施の形態１と異なる。   The manufacturing method of the semiconductor device in the second embodiment basically includes the same steps as the manufacturing method of the semiconductor device in the first embodiment. However, the air gap layer 13 is formed in advance on both one main surface of the semiconductor element 1 and one main surface of the substrate 2. The difference from the first embodiment is that there is a step of forming a total of three connection layers by connecting the two gap layers 13 with the bonding layer 7.

図９は、本発明の実施の形態２における半導体装置の製造方法を示すフローチャートである。続いて、本実施の形態における半導体装置の製造方法について、図９および上述の図７および図８を用いて説明する。   FIG. 9 is a flowchart showing a method for manufacturing a semiconductor device in the second embodiment of the present invention. Next, a method for manufacturing a semiconductor device in the present embodiment will be described with reference to FIG. 9 and FIGS. 7 and 8 described above.

まず、上述のとおり、予め半導体素子１の一方の主表面上および、基材２の一方の主表面上とに、空隙層１３を形成しておく。その方法としてはまず、ペーストの準備工程（Ｓ４１）を行なう。具体的にはたとえば、平均粒径１μｍの銀の粉および平均粒径０．１μｍの銀の粉の混合粉を揮発性溶剤と混合したペースト６を準備する。続いてペーストの半導体素子への供給工程（Ｓ４２ａ）、ペーストの基材への供給工程（Ｓ４２ｂ）を行なう。すなわち先に準備したペースト６を、半導体素子１の一方の主表面上および基材２の一方の主表面上に供給する。そのうえで、上述の工程（Ｓ４２ａ）および工程（Ｓ４２ｂ）にて供給したペースト６から、半導体素子への空隙層の形成工程（Ｓ４３ａ）および基材への空隙層の形成工程（Ｓ４３ｂ）を実施する。すなわち、たとえば加熱して溶剤を揮発させて銀の粉を焼結させることにより、上述のペースト６を空隙層１３とさせる（図５参照）。この空隙層１３の主表面上には障害物が存在しないため、溶剤を揮発させる際に発生したアウトガスは空隙層１３の上方に自由に放散される。この結果、この空隙層１３にはアウトガスが放散された軌跡として、連続した空隙が形成されることになる。なお、上述の空隙層１３の厚さは１０μｍ程度が好ましい。次に、基材へ再び、ペーストの供給工程（Ｓ４４ｂ）を行なう。具体的には先に準備したペースト６を、基材２の空隙層１３の、基材２と反対側の主表面上に供給する。なお、図９においては、基材２にペースト６を供給しているが、これは半導体素子１の空隙層１３の、半導体素子１の反対側の主表面上に供給しても良い。次に、半導体素子と基材との重ね合わせ工程（Ｓ４５）に進む。すなわち、半導体素子１の空隙層１３と、上述の基材２に供給したペースト６とを接着させ、系全体を重ね合わせる。最後に加熱による接続工程（Ｓ４６）を行なう。これは加熱してペースト６に含まれる溶剤を揮発させて銀の粉を焼結させ、接合層７を形成するものである。以上の工程により、図８における半導体装置の構成１００ｂに示すような構成の半導体装置の製造が完了する。   First, as described above, the gap layer 13 is formed in advance on one main surface of the semiconductor element 1 and one main surface of the substrate 2. First, a paste preparation step (S41) is performed. Specifically, for example, a paste 6 is prepared by mixing a mixed powder of silver powder having an average particle diameter of 1 μm and silver powder having an average particle diameter of 0.1 μm with a volatile solvent. Subsequently, a paste supplying step (S42a) to the semiconductor element and a paste supplying step (S42b) are performed. That is, the previously prepared paste 6 is supplied onto one main surface of the semiconductor element 1 and one main surface of the substrate 2. In addition, a void layer forming step (S43a) on the semiconductor element and a void layer forming step (S43b) on the substrate are performed from the paste 6 supplied in the above-described step (S42a) and step (S42b). That is, for example, by heating and volatilizing the solvent to sinter the silver powder, the above-mentioned paste 6 is made into the gap layer 13 (see FIG. 5). Since there are no obstacles on the main surface of the void layer 13, the outgas generated when the solvent is volatilized is freely dissipated above the void layer 13. As a result, continuous voids are formed in the void layer 13 as a locus of the outgas being diffused. The thickness of the gap layer 13 is preferably about 10 μm. Next, the paste supplying step (S44b) is performed again on the substrate. Specifically, the previously prepared paste 6 is supplied onto the main surface of the void layer 13 of the substrate 2 opposite to the substrate 2. In FIG. 9, the paste 6 is supplied to the substrate 2, but this may be supplied on the main surface of the void layer 13 of the semiconductor element 1 on the opposite side of the semiconductor element 1. Next, it progresses to the superimposition process (S45) of a semiconductor element and a base material. That is, the gap layer 13 of the semiconductor element 1 and the paste 6 supplied to the base material 2 are adhered, and the entire system is overlaid. Finally, a connecting step (S46) by heating is performed. This heats and volatilizes the solvent contained in the paste 6 to sinter the silver powder to form the bonding layer 7. Through the above steps, the manufacture of the semiconductor device having the configuration as shown in the configuration 100b of the semiconductor device in FIG. 8 is completed.

本実施の形態２においては、半導体装置の構成１００ｂに示すように空隙層１３が、接合層７の一方の主表面側と他方の主表面側の両側に配置された多層構造となっている。このため、空隙層１３が、接合層７の一方の主表面側のみに配置されている実施の形態１の構成に比べ、より効率よく、接合層７内で発生したアウトガスを除去することができる。   In the second embodiment, as shown in the configuration 100b of the semiconductor device, the gap layer 13 has a multilayer structure in which the bonding layer 7 is disposed on one main surface side and the other main surface side. For this reason, the outgas generated in the bonding layer 7 can be removed more efficiently than the configuration of the first embodiment in which the gap layer 13 is arranged only on one main surface side of the bonding layer 7. .

なお、本実施の形態２においても、工程（Ｓ４４ｂ）において基材２の空隙層１３に供給したペースト６を工程（Ｓ４５）において半導体素子１と重ね合わせる際に、供給したペースト６の一部が半導体素子１や空隙層１３の端部からはみ出すことが考えられる。しかし、ペースト６のはみ出した部分の加熱により形成された接合層７の端部が、空隙層１３の側面の全面を覆わない限り、空隙層１３の側面のうち、接合層７の端部に覆われていない箇所に存在する連続した空隙を通って、アウトガスを放散させることが可能である。   Also in the second embodiment, when the paste 6 supplied to the gap layer 13 of the substrate 2 in the step (S44b) is overlapped with the semiconductor element 1 in the step (S45), a part of the supplied paste 6 is partly. Protruding from the end portions of the semiconductor element 1 and the gap layer 13 can be considered. However, unless the end of the bonding layer 7 formed by heating the protruding portion of the paste 6 covers the entire side surface of the gap layer 13, the end of the bonding layer 7 is covered among the side surfaces of the gap layer 13. It is possible to dissipate the outgas through continuous voids present at undisclosed locations.

（実施の形態３）
図１０は、本発明の実施の形態３における半導体装置の配置を示すための、接続工程完了前の状態を示す概略図である。また、図１１は、本発明の実施の形態３における半導体装置の構成を示すための、接続工程完了後の状態を示す概略図である。本実施の形態３における半導体装置は、図１０に半導体装置の固定前の構造１００ａとして示すように、基本的には実施の形態２における半導体装置と同様の構成を備えている。しかし、図１１に示すように空隙層１３が、２つの接合層７のうち一方の接合層７の一方の主表面と、他方の接合層７の一方の主表面とに挟まれるように存在する構成となっている点においてのみ、実施の形態２と異なる。 (Embodiment 3)
FIG. 10 is a schematic diagram showing a state before the connection process is completed, for illustrating the arrangement of the semiconductor device according to the third embodiment of the present invention. FIG. 11 is a schematic diagram showing a state after the completion of the connection process for showing the configuration of the semiconductor device according to the third embodiment of the present invention. The semiconductor device according to the third embodiment basically has the same configuration as that of the semiconductor device according to the second embodiment, as shown as a structure 100a before fixing the semiconductor device in FIG. However, as shown in FIG. 11, the gap layer 13 exists so as to be sandwiched between one main surface of one of the two bonding layers 7 and one main surface of the other bonding layer 7. It differs from the second embodiment only in the configuration.

本実施の形態３における半導体装置の製造方法は、基本的には実施の形態２における半導体装置の製造方法と同様のステップを備えている。しかし、空隙層１３を、予め別の場所で準備しておき、半導体素子１の一方の主表面上と、基材２の一方の主表面上との両方に供給したペースト６を用いて上述の空隙層１３を挟む形となる構成に組立てるステップが存在する。この点において、実施の形態２と異なる。   The semiconductor device manufacturing method according to the third embodiment basically includes the same steps as the semiconductor device manufacturing method according to the second embodiment. However, the gap layer 13 is prepared in advance in another place, and the above-described paste 6 is supplied to both the one main surface of the semiconductor element 1 and the one main surface of the substrate 2. There is a step of assembling into a configuration in which the gap layer 13 is sandwiched. This is different from the second embodiment.

図１２は、本発明の実施の形態３における半導体装置の製造方法を示すフローチャートである。続いて、本実施の形態における半導体装置の製造方法について、図１２および上述の図１０および図１１を用いて説明する。   FIG. 12 is a flowchart showing a method for manufacturing a semiconductor device in the third embodiment of the present invention. Next, a method for manufacturing the semiconductor device in the present embodiment will be described with reference to FIG. 12 and FIGS. 10 and 11 described above.

まず、ペーストの準備工程（Ｓ５１）を実施する。具体的にはたとえば、平均粒径１μｍの銀の粉および平均粒径０．１μｍの銀の粉の混合粉を揮発性溶剤と混合したペースト６を準備する。続いて、空隙層の形成（Ｓ５２）を行なう。これは、先に別の場所で予め準備したペースト６を焼結させることにより、空隙層１３を形成する。上述の空隙層１３は、厚さが１０μｍ程度であることが好ましい。このため、仮の基板の一方の主表面上にペースト６を供給したものを焼成し、これを所望の寸法にカットすることにより形成する。続いてペーストの半導体素子への供給工程（Ｓ５３ａ）、ペーストの基材への供給工程（Ｓ５３ｂ）を行なう。すなわち先に準備したペースト６を、半導体素子１の一方の主表面上および基材２の一方の主表面上に供給する。以上の工程を終えたところで、半導体素子と素材と空隙層との重ね合わせ工程（Ｓ５４）を行なう。すなわち、上述のペースト６を介して、上述の半導体素子１と基材２の両方に、空隙層１３が挟まれる形となるように、これらを接着させ重ね合わせる。最後に加熱による接続工程（Ｓ５５）を行なう。これは加熱してペースト６に含まれる溶剤を揮発させて銀の粉を焼結させ、接合層７を形成するものである。以上の工程により、図１１における半導体装置の構成１００ｂに示すような構成の半導体装置の製造が完了する。   First, a paste preparation step (S51) is performed. Specifically, for example, a paste 6 is prepared by mixing a mixed powder of silver powder having an average particle diameter of 1 μm and silver powder having an average particle diameter of 0.1 μm with a volatile solvent. Subsequently, a void layer is formed (S52). In this method, the gap layer 13 is formed by sintering the paste 6 previously prepared in another place. The gap layer 13 described above preferably has a thickness of about 10 μm. For this reason, it forms by baking what supplied the paste 6 on one main surface of a temporary board | substrate, and cutting this into a desired dimension. Subsequently, a paste supplying step (S53a) to the semiconductor element and a paste supplying step (S53b) are performed. That is, the previously prepared paste 6 is supplied onto one main surface of the semiconductor element 1 and one main surface of the substrate 2. When the above steps have been completed, an overlapping step (S54) of the semiconductor element, the material, and the void layer is performed. That is, these are bonded and overlapped via the paste 6 so that the gap layer 13 is sandwiched between the semiconductor element 1 and the substrate 2 described above. Finally, a connecting step by heating (S55) is performed. This heats and volatilizes the solvent contained in the paste 6 to sinter the silver powder to form the bonding layer 7. Through the above steps, the manufacture of the semiconductor device having the configuration as shown in the configuration 100b of the semiconductor device in FIG. 11 is completed.

なお、本実施の形態３において形成する空隙層１３として、上述のとおりたとえば平均粒径１μｍの銀の粉および平均粒径０．１μｍの銀の粉とを混合させて準備したペーストを焼結させた部材を用いても良いが、他に以下のような部材を用いることもできる。本実施の形態３の場合、空隙層１３は、半導体素子１や基材２の主表面上に形成させるわけではなく、別の場所で独立に準備する。したがって、空隙層でさえあれば、その形成方法は上述の方法に限るものではなく、スポンジのように金属中に連続した空隙を形成できる方法であれば良い。すなわち、たとえば金属ワイヤをメッシュ状に編み合わせたシートを圧延するなどの方法で結合して製造しても良い。以上の点においても、実施の形態１および実施の形態２とは異なる。   In addition, as the void layer 13 formed in the third embodiment, as described above, for example, a paste prepared by mixing silver powder having an average particle diameter of 1 μm and silver powder having an average particle diameter of 0.1 μm is sintered. However, the following members can also be used. In the case of the third embodiment, the gap layer 13 is not formed on the main surface of the semiconductor element 1 or the base material 2 but is prepared independently at another location. Therefore, as long as there is a void layer, the formation method is not limited to the above-described method, and any method can be used as long as it can form continuous voids in a metal like a sponge. That is, for example, a sheet in which metal wires are knitted in a mesh shape may be bonded and manufactured by rolling. The above points are also different from the first and second embodiments.

実施の形態２、３においても、先の実施の形態１と同様に、本実施の形態の説明においては銀の粉を焼結させて接合層７を形成する場合について述べたが、これに限るものではなく、上述のとおり、金や銅の粉を用いた場合や、銀、金、または銅の粉を金属粉の組成に含ませた場合でも同様の効果が得られる。さらに、白金、パラジウム、ロジウムなどの貴金属粉であれば同様の効果が得られることは言うまでもない。また、金属粉の平均粒径についても上述の数値に限るものではないことは言うまでもない。すなわち、本発明の全ての実施の形態に対しては、銀、金、銅あるいは上述の貴金属を組成に含む金属粉を用いると、上記以外の金属を含む金属粉を用いた場合より安定した接続を得ることができる。   Also in the second and third embodiments, as in the first embodiment, in the description of the present embodiment, the case where the bonding layer 7 is formed by sintering silver powder is described. However, as described above, the same effect can be obtained even when gold or copper powder is used, or when silver, gold, or copper powder is included in the composition of the metal powder. Furthermore, it goes without saying that the same effect can be obtained with noble metal powders such as platinum, palladium and rhodium. Moreover, it cannot be overemphasized that it is not restricted to the above-mentioned numerical value also about the average particle diameter of metal powder. That is, for all the embodiments of the present invention, when using metal powder containing silver, gold, copper, or the above-mentioned noble metal in the composition, a more stable connection than when using metal powder containing a metal other than the above is used. Can be obtained.

また、図１３は、実施の形態３と同様の半導体装置の配置を示すが、基材２の一方の主表面上の全面にペーストを施した場合の、接続工程完了前の状態を示す概略図である。図１４は、基材２の全面にペーストを施して実施の形態３と同様の配置とした場合における半導体装置の構成を示すための、接続工程完了後の状態を示す概略図である。上述の実施の形態３においては、図１０および図１１に示すように、基材２の一方の主表面上に供給するペースト６は、基材２の主表面上全面ではなく、基材２の主表面上のうち、接続されて半導体素子１に対向する部分のみとなっている。しかし、図１３の半導体装置の固定前の構造１００ａに示すように、基材２の一方の主表面上全面にペースト６の供給を行なうこともできる。この場合には、ペースト６が空隙層１３の側面上に廻りこむ可能性が大きいと考えられる。また、先の実施の形態１でも述べたとおり、工程（Ｓ５３ａ）において半導体素子１の一方の主表面上に供給したペースト６についても、工程（Ｓ５４）において半導体素子１と空隙層１３との重ね合わせを行なった際には、上述のように空隙層１３の側面上にペースト６がはみ出す可能性がある。その結果、接続工程完了後には図１４の半導体装置の構成１００ｂに示すように接合層７の一部が半導体素子１や空隙層１３の主表面に対してはみ出した状態となる場合がある。この場合においても、ペースト６のはみ出した部分の加熱により形成された接合層７の端部が、空隙層１３の側面の全面を覆わない限り、空隙層１３の側面のうち、接合層７の端部に覆われていない箇所に存在する連続した空隙を通って、アウトガスを放散させることが可能である。   FIG. 13 shows the arrangement of the semiconductor device similar to that of the third embodiment, but is a schematic diagram showing the state before the completion of the connecting step when the paste is applied to the entire surface of one main surface of the substrate 2. It is. FIG. 14 is a schematic diagram showing a state after the completion of the connection process for showing the configuration of the semiconductor device in the case where paste is applied to the entire surface of the base material 2 to obtain the same arrangement as in the third embodiment. In the above-described third embodiment, as shown in FIGS. 10 and 11, the paste 6 supplied onto one main surface of the base material 2 is not the entire surface of the main surface of the base material 2 but the base material 2. Of the main surface, only the portion that is connected and faces the semiconductor element 1 is provided. However, as shown in the structure 100a before fixing the semiconductor device in FIG. 13, the paste 6 can be supplied to the entire surface of one main surface of the substrate 2. In this case, it is considered that there is a high possibility that the paste 6 will wrap around the side surface of the gap layer 13. As described in the first embodiment, the paste 6 supplied on one main surface of the semiconductor element 1 in the step (S53a) is also overlapped with the semiconductor element 1 and the gap layer 13 in the step (S54). When the alignment is performed, the paste 6 may protrude from the side surface of the gap layer 13 as described above. As a result, after the connection process is completed, a part of the bonding layer 7 may protrude from the main surfaces of the semiconductor element 1 and the gap layer 13 as shown in the configuration 100b of the semiconductor device in FIG. Even in this case, as long as the end portion of the bonding layer 7 formed by heating the protruding portion of the paste 6 does not cover the entire side surface of the gap layer 13, the end of the bonding layer 7 among the side surfaces of the gap layer 13. It is possible to dissipate outgas through a continuous gap existing in a place not covered with the part.

今回開示された実施の形態は全ての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上述した実施の形態ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内での全ての変更が含まれることが意図される。   The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above-described embodiment but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

本発明の半導体装置および半導体装置の製造方法は、半導体装置の実装技術の改善に特に適している。   The semiconductor device and the method for manufacturing the semiconductor device of the present invention are particularly suitable for improving the mounting technology of the semiconductor device.

本発明の実施の形態１における半導体装置の配置を示すための、接続工程完了前の状態を示す概略図である。It is the schematic which shows the state before completion of a connection process for showing arrangement | positioning of the semiconductor device in Embodiment 1 of this invention. 本発明の実施の形態１における半導体装置の構成を示すための、接続工程完了後の状態を示す概略図である。It is the schematic which shows the state after completion of a connection process for showing the structure of the semiconductor device in Embodiment 1 of this invention. 本発明の実施の形態１における半導体装置の製造方法を示すフローチャートである。3 is a flowchart showing a method for manufacturing the semiconductor device in the first embodiment of the present invention. 基材の一方の主表面上に、空隙層を形成させるためにペーストを供給した状態を示す概略図である。It is the schematic which shows the state which supplied the paste in order to form a space | gap layer on one main surface of a base material. 基材の一方の主表面上に、空隙層を形成させる系を加熱した状態を示す概略図である。It is the schematic which shows the state which heated the type | system | group which forms a space | gap layer on one main surface of a base material. 供給したペーストの一部が重ね合わせの際にはみ出した場合の、接続工程完了後の半導体装置の外観を示す概略図である。It is the schematic which shows the external appearance of the semiconductor device after the completion of a connection process when a part of supplied paste protrudes at the time of superposition. 本発明の実施の形態２における半導体装置の配置を示すための、接続工程完了前の状態を示す概略図である。It is the schematic which shows the state before completion of a connection process for showing arrangement | positioning of the semiconductor device in Embodiment 2 of this invention. 本発明の実施の形態２における半導体装置の構成を示すための、接続工程完了後の状態を示す概略図である。It is the schematic which shows the state after completion of a connection process for showing the structure of the semiconductor device in Embodiment 2 of this invention. 本発明の実施の形態２における半導体装置の製造方法を示すフローチャートである。It is a flowchart which shows the manufacturing method of the semiconductor device in Embodiment 2 of this invention. 本発明の実施の形態３における半導体装置の配置を示すための、接続工程完了前の状態を示す概略図である。It is the schematic which shows the state before completion of a connection process for showing arrangement | positioning of the semiconductor device in Embodiment 3 of this invention. 本発明の実施の形態３における半導体装置の構成を示すための、接続工程完了後の状態を示す概略図である。It is the schematic which shows the state after completion of a connection process for showing the structure of the semiconductor device in Embodiment 3 of this invention. 本発明の実施の形態３における半導体装置の製造方法を示すフローチャートである。It is a flowchart which shows the manufacturing method of the semiconductor device in Embodiment 3 of this invention. 実施の形態３と同様の半導体装置の配置を示すが、基材の一方の主表面上の全面にペーストを施した場合の、接続工程完了前の状態を示す概略図である。FIG. 10 is a schematic view showing a state before completion of a connection process in the case where paste is applied to the entire surface on one main surface of a base material, although the arrangement of the semiconductor device is the same as that of the third embodiment. 基材の全面にペーストを施して実施の形態３と同様の配置とした場合における半導体装置の構成を示すための、接続工程完了後の状態を示す概略図である。It is the schematic which shows the state after the completion of a connection process for showing the structure of the semiconductor device in the case where paste is applied to the entire surface of the base material to obtain the same arrangement as in the third embodiment. 従来の技術により組立てた半導体装置の概略図で、接続層に接続欠陥が多数発生した状態を示す概略図である。It is the schematic of the semiconductor device assembled by the prior art, and is the schematic which shows the state where many connection defects generate | occur | produced in the connection layer. 従来の改良技術により組立てた半導体装置の概略図で、接続欠陥を捕捉する溝加工が接続面に施されている状態を示す概略図である。It is the schematic of the semiconductor device assembled with the conventional improvement technique, and is the schematic which shows the state by which the groove process which catches a connection defect is given to the connection surface.

符号の説明Explanation of symbols

１ 半導体素子、２ 基材、３ 従来技術による接続層、４ 接続欠陥としてのボイド、５ 従来技術により一方の主表面上に溝加工を施した半導体素子、６ ペースト、７ 接合層、１３ 空隙層、１００ａ 半導体装置の固定前の構造を示す概略図、１００ｂ 半導体装置の構成を示す概略図。   DESCRIPTION OF SYMBOLS 1 Semiconductor element, 2 base material, 3 Connection layer by conventional technology, 4 Void as a connection defect, 5 Semiconductor device which gave groove processing on one main surface by conventional technology, 6 Paste, 7 Joining layer, 13 Void layer , 100a Schematic showing the structure before fixing the semiconductor device, 100b Schematic showing the configuration of the semiconductor device.

Claims (12)

主表面を有する基材と、
半導体素子と、
前記基材と前記半導体素子との間にこれらを接続するための接続層とを備え、
前記接続層は、その中に連続した空隙が存在する空隙層と、前記空隙層中よりも連続した空隙が相対的に少ない接合層とを含んだ積層体であることを特徴とする、半導体装置。 A substrate having a main surface;
A semiconductor element;
A connection layer for connecting them between the base material and the semiconductor element;
The connection layer is a laminate including a void layer in which continuous voids are present and a bonding layer having relatively fewer continuous voids than in the void layer. . 前記連続した空隙の最大幅が１０μｍ以下であることを特徴とする、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a maximum width of the continuous gap is 10 μm or less. 前記接続層は、前記空隙層の厚さが前記接合層の厚さより大きいことを特徴とする、請求項１または２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the connection layer has a thickness of the gap layer larger than a thickness of the bonding layer. 前記接続層は、前記空隙層と前記接合層とが合計３層以上積層するとともに、前記接合層の主表面のうち少なくとも一方が前記空隙層と隣接する多層構造であることを特徴とする、請求項１〜３のいずれか１項に記載の半導体装置。   The connection layer has a multilayer structure in which a total of three or more layers of the gap layer and the bonding layer are laminated, and at least one of the main surfaces of the bonding layer is adjacent to the gap layer. Item 4. The semiconductor device according to any one of Items 1 to 3. 前記接続層は、前記空隙層と、前記接合層との２層のみからなることを特徴とする、請求項１〜３のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the connection layer includes only two layers of the gap layer and the bonding layer. 前記空隙層および前記接合層は、金属粉と結合材とを混合させたペーストを、前記金属粉の焼結または前記結合材の硬化によって固化することにより形成されることを特徴とする、請求項１〜５のいずれか１項に記載の半導体装置。   The gap layer and the bonding layer are formed by solidifying a paste obtained by mixing a metal powder and a binder by sintering the metal powder or curing the binder. The semiconductor device according to any one of 1 to 5. 前記金属粉は、銀、金、または銅を含むことを特徴とする、請求項６に記載の半導体装置。   The semiconductor device according to claim 6, wherein the metal powder includes silver, gold, or copper. 前記金属粉は、少なくとも一部の粒径が０.１μｍ以下であることを特徴とする、請求項６または７に記載の半導体装置。   8. The semiconductor device according to claim 6, wherein at least a part of the metal powder has a particle size of 0.1 [mu] m or less. 前記接続層を形成するペースト中における前記金属粉の存在比率が５ｖｏｌ％以上３０ｖｏｌ％以下であることを特徴とする、請求項６〜８のいずれか１項に記載の半導体装置。   9. The semiconductor device according to claim 6, wherein an abundance ratio of the metal powder in the paste forming the connection layer is 5 vol% or more and 30 vol% or less. 主表面を有する基材を準備する工程と、
前記基材の前記主表面上に接続層を介して半導体素子を接続する工程とを備え、
前記半導体素子を接続する工程は、接続層を形成する工程を含み、
前記接続層を形成する工程には
連続した空隙が存在する空隙層を形成する工程および、
前記空隙層と積層され、連続した空隙が前記空隙層よりも相対的に少ない接合層を形成する工程を含むことを特徴とする、半導体装置の製造方法。 Preparing a substrate having a main surface;
Connecting a semiconductor element on the main surface of the base material via a connection layer,
The step of connecting the semiconductor elements includes a step of forming a connection layer,
The step of forming the connection layer includes a step of forming a void layer in which continuous voids exist, and
A method for manufacturing a semiconductor device, comprising: a step of forming a bonding layer which is laminated with the gap layer and has relatively few continuous gaps than the gap layer. 前記空隙層を形成する工程を行なった後に、前記接合層を形成する工程を行なうことにより、前記接続層を形成することを特徴とする、請求項１０に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 10, wherein the connection layer is formed by performing a step of forming the bonding layer after performing the step of forming the gap layer. 少なくとも一部の粒径が０．１μｍ以下である金属粉と結合材とを混合させたペーストを前記空隙層上に形成する工程と、
前記結合材を除去する工程と、
前記金属粉を焼結させて接合層を構成する工程とを備えることを特徴とする、請求項１０または１１に記載の半導体装置の製造方法。 Forming a paste on which the metal powder having a particle size of 0.1 μm or less and a binder are mixed on the gap layer;
Removing the binder;
The method for manufacturing a semiconductor device according to claim 10, further comprising a step of sintering the metal powder to form a bonding layer.
JP2007339952A 2007-12-28 2007-12-28 Semiconductor device and manufacturing method of semiconductor device Pending JP2009164208A (en)

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