JP2005093698A - Semiconductor module for electric power - Google Patents

Semiconductor module for electric power Download PDF

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JP2005093698A
JP2005093698A JP2003324696A JP2003324696A JP2005093698A JP 2005093698 A JP2005093698 A JP 2005093698A JP 2003324696 A JP2003324696 A JP 2003324696A JP 2003324696 A JP2003324696 A JP 2003324696A JP 2005093698 A JP2005093698 A JP 2005093698A
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power semiconductor
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module
voltage
withstand voltage
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JP4154671B2 (en
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Yasushi Abe
康 阿部
Kiyoaki Sasagawa
清明 笹川
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Power Conversion In General (AREA)
  • Inverter Devices (AREA)
  • Electronic Switches (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an element occurrence loss in a power semiconductor element module and to shorten a switching time. <P>SOLUTION: For example, reversed parallel circuits of an IGBT chip Q1 (Q2, Q3 and Q4) of a withstand voltage of 1,200 V and a diode chip D1, (D2, D3 and D4) of an equal withstand voltage of 1,200 V are paired, and four pairs are connected in series, whereby a semiconductor module of a withstand voltage of 4,500 V can easily be obtained which has a lower loss and a higher speed than in a parallel connection method. At this time, in order to balance the switching timing of each IGBT chip, mutual magnetic connection is preferable by cores Tc1, Tc2, Tc3, and Tc4. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

この発明は、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）やＭＯＳＦＥＴ（金属酸化膜半導体電界効果トランジスタ）のような電圧駆動型半導体素子のモジュール内部の構造に関する。   The present invention relates to a structure inside a module of a voltage-driven semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

図４に、一般的な電力用半導体モジュール（単に、モジュールともいう）の内部等価回路例を示す。ＱはＩＧＢＴチップ、Ｄｉはダイオードチップ、Ｇ，Ｃ，ＥはそれぞれＩＧＢＴチップのゲート，コレクタ，エミッタ端子を示す。これは、ＩＧＢＴ，ダイオードともに各１チップで構成する例で、それぞれのチップが必要な耐圧を有している。   FIG. 4 shows an internal equivalent circuit example of a general power semiconductor module (also simply referred to as a module). Q is an IGBT chip, Di is a diode chip, G, C, and E are gate, collector, and emitter terminals of the IGBT chip, respectively. This is an example in which both the IGBT and the diode are each constituted by one chip, and each chip has a necessary withstand voltage.

図５に、例えば特許文献１に示されているような、半導体素子モジュールの内部構成例を示す。図示のように、金属ベース板１０とＩＧＢＴのコレクタ電位となるコレクタ導体１１との間を、絶縁基板１２によって絶縁し、このコレクタ導体１１にＩＧＢＴチップ１３のコレクタと、ダイオードチップ１４のカソードを電気的に接着する。また、ＩＧＢＴチップ１３のエミッタとダイオードチップ１４のアノードを、ワイヤボンディングによって接続し、図４の回路を構成する。   FIG. 5 shows an example of the internal configuration of a semiconductor element module as disclosed in Patent Document 1, for example. As shown in the figure, an insulating substrate 12 insulates between the metal base plate 10 and the collector conductor 11 serving as the collector potential of the IGBT, and the collector conductor 11 is electrically connected to the collector of the IGBT chip 13 and the cathode of the diode chip 14. Glue together. Further, the emitter of the IGBT chip 13 and the anode of the diode chip 14 are connected by wire bonding to constitute the circuit of FIG.

また、素子１チップでは電流容量が不足する場合は、ＩＧＢＴとダイオードのチップを並列に接続する。図６は２並列の例で、Ｑ１，Ｑ２はＩＧＢＴチップ、Ｄ１，Ｄ２はダイオードチップ、Ｇ，Ｃ，ＥはそれぞれＩＧＢＴチップのゲート，コレクタ，エミッタ端子を示す。このときのモジュールの内部構成は図７のようになり、例えば特許文献２により公知である。つまり、図５に対し、1組のＩＧＢＴチップ１３とダイオードチップ１４を並列に接続し、半導体モジュールの定格電圧を変えるときは、ＩＧＢＴチップとダイオードチップを定格電圧となるように選定する。
特開２００３−００７９６９号公報（第４−５頁、図１） 特開平１０−１６３４１６号公報（第３−４頁、図１） If the current capacity of the element 1 chip is insufficient, the IGBT and diode chips are connected in parallel. FIG. 6 shows an example of two parallel arrangements, Q1 and Q2 are IGBT chips, D1 and D2 are diode chips, and G, C, and E are gate, collector, and emitter terminals of the IGBT chip, respectively. The internal configuration of the module at this time is as shown in FIG. That is, with respect to FIG. 5, when a set of IGBT chip 13 and diode chip 14 are connected in parallel and the rated voltage of the semiconductor module is changed, the IGBT chip and the diode chip are selected to have the rated voltage.
JP 2003-007969 A (page 4-5, FIG. 1) JP-A-10-163416 (page 3-4, FIG. 1)

従来のモジュール構成では、１つの半導体チップで必要な素子電圧定格を得ることができないため、半導体チップの数は電流容量によって並列接続数を増やすようにしている。しかし、素子電圧定格が増加するにつれ、素子発生損失やスイッチング時間が増大し、冷却装置の大型化，制御性能の低下などの問題が発生する。   In the conventional module configuration, since the required element voltage rating cannot be obtained with one semiconductor chip, the number of semiconductor chips is increased in parallel connection by the current capacity. However, as the element voltage rating increases, element generation loss and switching time increase, and problems such as an increase in the size of the cooling device and a decrease in control performance occur.

したがって、この発明の課題は、素子発生損失やスイッチング時間を低減することにある。   Therefore, an object of the present invention is to reduce element generation loss and switching time.

このような課題を解決するために、請求項１の発明では、樹脂ケースと金属ベース板とを組み合わせたパッケージに、電圧駆動型半導体チップ素子とこれに逆並列に接続されたダイオードチップ素子とを組とするパワー半導体チップを各絶縁基板にマウントし、外部導出端子を組み込んで構成した電力用半導体モジュールにおいて、前記パワー半導体チップを、必要とする素子定格電圧よりも低い耐圧のチップで構成し、電力用半導体モジュールとして必要な素子定格電圧になるように前記パワー半導体チップを複数個直列接続し、これらを同時にスイッチングさせることで、見かけ上の耐圧を増加させたことを特徴とする。   In order to solve such a problem, in the invention of claim 1, a voltage drive type semiconductor chip element and a diode chip element connected in reverse parallel to the voltage drive type semiconductor chip element are provided in a package in which a resin case and a metal base plate are combined. In a power semiconductor module configured by mounting a power semiconductor chip to be assembled on each insulating substrate and incorporating an external lead-out terminal, the power semiconductor chip is configured with a chip having a withstand voltage lower than a required element rated voltage, A plurality of the power semiconductor chips are connected in series so as to have an element rated voltage required as a power semiconductor module, and these are simultaneously switched to increase the apparent withstand voltage.

この請求項１の発明においては、前記複数個直列接続されたパワー半導体チップのスイッチングタイミングのばらつきを抑制し、各素子電圧をバランスさせるために、各チップのゲート線またはエミッタ線をコアを介して互いに磁気結合し、かつこれらのコアをモジュール内に内蔵することができる（請求項２の発明）。   According to the first aspect of the present invention, in order to suppress variations in switching timing of the plurality of power semiconductor chips connected in series and balance each element voltage, the gate line or emitter line of each chip is connected via a core. These cores can be magnetically coupled to each other, and these cores can be built in the module (invention of claim 2).

この発明によれば、必要な耐圧以下の電圧駆動型半導体素子チップを、必要な耐圧が得られるように複数直列接続することで、トータルのスイッチング損失を低減し、高周波スイッチングを可能とする。このとき、これら複数個のスイッチングタイミングをバランスさせるため、コアによって磁気結合させ、かつ、これらのコアをモジュール内に内蔵させることで、低損失，高性能を維持しつつ小型化を実現する。   According to the present invention, a plurality of voltage-driven semiconductor element chips having a required breakdown voltage or lower are connected in series so as to obtain a required breakdown voltage, thereby reducing the total switching loss and enabling high-frequency switching. At this time, in order to balance the plurality of switching timings, the cores are magnetically coupled, and these cores are built in the module, thereby realizing miniaturization while maintaining low loss and high performance.

図１はこの発明の実施の形態を示す構成図である。図１（ａ）は図４と同じく、素子モジュールの内部等価回路を示し、図１（ｂ）はこのような基本チップを複数直列接続した全体構成を示す。使用する素子は例えば１２００Ｖ耐圧以下のＩＧＢＴとし、４直列接続して４５００Ｖ耐圧の半導体モジュールとしている。これは、１２００Ｖ耐圧以下のＩＧＢＴは、３３００Ｖ耐圧以上の高耐圧モジュールと比較すると、スイッチング時間が１／１０程度であり、同じ耐圧となるように複数の素子を直列接続しても、１／３程度の損失とすることができるためである。   FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 1A shows an internal equivalent circuit of the element module, as in FIG. 4, and FIG. 1B shows an overall configuration in which a plurality of such basic chips are connected in series. An element to be used is, for example, an IGBT having a withstand voltage of 1200 V or less, and a 4500 V withstand voltage semiconductor module is connected in series. This is because an IGBT with a withstand voltage of 1200 V or less has a switching time of about 1/10 compared to a high withstand voltage module with a withstand voltage of 3300 V or more, and even if a plurality of elements are connected in series so as to have the same withstand voltage, 1/3 It is because it can be set as a loss of a grade.

図１（ｂ）において、Ｑ１，Ｑ２，Ｑ３，Ｑ４は１２００Ｖ耐圧のＩＧＢＴチップ、Ｄ１，Ｄ２，Ｄ３，Ｄ４は同じく１２００Ｖ耐圧のダイオードチップ、Ｔｃ１，Ｔｃ２，Ｔｃ３，Ｔｃ４はスイッチングタイミングをバランスさせるためのコア、Ｇ１，Ｇ２，Ｇ３，Ｇ４はＩＧＢＴチップのゲート端子、Ｃ，ＥはそれぞれＩＧＢＴチップのコレクタ，エミッタ端子を示している。各チップ素子のゲート端子Ｇ１，Ｇ２，Ｇ３，Ｇ４に同じタイミングの信号を入力し、同時にスイッチングすることで、モジュールの見かけ上の耐圧を４８００Ｖ（１２００Ｖ×４）とすることができ、１つの４５００Ｖ耐圧ＩＧＢＴモジュールと等価なものとすることができる。   In FIG. 1B, Q1, Q2, Q3, and Q4 are 1200V withstand voltage IGBT chips, D1, D2, D3, and D4 are similarly 1200V withstand voltage diode chips, and Tc1, Tc2, Tc3, and Tc4 are for balancing the switching timing. , G1, G2, G3, and G4 are gate terminals of the IGBT chip, and C and E are collector and emitter terminals of the IGBT chip, respectively. By inputting signals of the same timing to the gate terminals G1, G2, G3, and G4 of each chip element and switching them simultaneously, the apparent withstand voltage of the module can be set to 4800V (1200V × 4), and one 4500V It can be equivalent to a withstand voltage IGBT module.

コアＴｃ１，Ｔｃ２，Ｔｃ３，Ｔｃ４は４チップ素子のゲート線を磁気結合させるものであり、スイッチング時のゲート電流値を一致させるように動作する。図２に、ターンオフ時の各チップ波形を示す。図２（ａ），（ｂ）はコア無しの場合，図２（ｃ），（ｄ）はコア有りの場合を示す。   The cores Tc1, Tc2, Tc3, and Tc4 are for magnetically coupling the gate lines of the four-chip elements, and operate so as to match the gate current values at the time of switching. FIG. 2 shows each chip waveform at the time of turn-off. 2A and 2B show the case without a core, and FIGS. 2C and 2D show the case with a core.

いま、図２において、例えばＱ１のターンオフタイミングが、（ａ）のように他の３素子Ｑ２，Ｑ３，Ｑ４よりも早いと仮定すると、コアが無い場合は早くターンオフしたＱ１の素子電圧が（ｂ）のように他の素子よりも大きい電圧が印加されて過電圧となり、素子破壊を招くおそれがある。   In FIG. 2, for example, assuming that the turn-off timing of Q1 is earlier than that of the other three elements Q2, Q3, and Q4 as shown in FIG. ), A voltage higher than that of other elements is applied to cause overvoltage, which may cause element destruction.

これに対しコアが有る場合は、（ｃ）のようにゲート電流が一致し、これによって素子電圧を（ｄ）のようにバランスさせることが可能となる。なお、このようにコアを用いてタイミングを一致させる技術は、出願人が先に提案した例えば、特開２００２−２０４５７８号公報により公知である。また、コアでゲートを磁気結合させる代わりに、エミッタを磁気結合させても良い。   On the other hand, when there is a core, the gate currents coincide with each other as shown in (c), thereby making it possible to balance the device voltage as shown in (d). A technique for matching the timing using the core in this way is known from, for example, Japanese Patent Application Laid-Open No. 2002-204578 previously proposed by the applicant. Further, instead of magnetically coupling the gate with the core, the emitter may be magnetically coupled.

図３に、図１のモジュールの内部構成例を示す。   FIG. 3 shows an example of the internal configuration of the module shown in FIG.

これは、ＩＧＢＴチップ１３とダイオードチップ１４を逆並列接続した回路1組を１枚の導体１１にマウントし、このセットを4個絶縁基板１２に設置する。このとき、各導体が異なる電位を有するため、必要な絶縁距離を持たせる。これらチップ同士をワイヤボンディングによって接続し、コアＴｃ１，Ｔｃ２，Ｔｃ３，Ｔｃ４を絶縁基板１２上に設置し、図１の回路を構成する。これらを金属ベース板１０にマウントして、Ｑ１のコレクタとＱ４のエミッタの電位、また各素子のゲートとエミッタ電位に外部端子を設け、外囲（外周）を樹脂ケースで覆うことによって、見かけ上の耐圧４８００Ｖの半導体モジュールを構成することができる。   In this method, a set of circuits in which an IGBT chip 13 and a diode chip 14 are connected in antiparallel are mounted on one conductor 11, and four sets are installed on an insulating substrate 12. At this time, since each conductor has a different potential, a necessary insulation distance is provided. These chips are connected to each other by wire bonding, and the cores Tc1, Tc2, Tc3, and Tc4 are installed on the insulating substrate 12 to constitute the circuit of FIG. By mounting these on the metal base plate 10, external terminals are provided for the potential of the collector of Q1 and the emitter of Q4, and the gate and emitter potential of each element, and the outer periphery (outer periphery) is covered with a resin case. A semiconductor module having a withstand voltage of 4800 V can be configured.

この発明の実施の形態を説明する説明図Explanatory drawing explaining embodiment of this invention この発明の作用を従来例と比較して説明するための波形図Waveform diagram for explaining the operation of the present invention in comparison with the conventional example 図１の場合の内部構造例を示す構造図Structure diagram showing an example of the internal structure in the case of FIG. 従来のモジュールの等価回路図Equivalent circuit diagram of conventional module 図４のモジュール内部構造例図Example of module internal structure in FIG. 従来の２チップ並列モジュールの等価回路図Equivalent circuit diagram of conventional 2-chip parallel module 図６のモジュール内部構造例図FIG. 6 shows an example of the internal structure of the module.

符号の説明Explanation of symbols

１０…金属ベース板、１１…コレクタ導体、１２…絶縁基板、１３…ＩＧＢＴチップ、１４…ダイオードチップ、１５…ゲート導体、Ｔｃ１，Ｔｃ２，Ｔｃ３，Ｔｃ４…コア。
DESCRIPTION OF SYMBOLS 10 ... Metal base plate, 11 ... Collector conductor, 12 ... Insulating substrate, 13 ... IGBT chip, 14 ... Diode chip, 15 ... Gate conductor, Tc1, Tc2, Tc3, Tc4 ... Core.

Claims (2)

樹脂ケースと金属ベース板とを組み合わせたパッケージに、電圧駆動型半導体素子とこれに逆並列接続されたダイオードチップ素子とを組とするパワー半導体チップを各絶縁基板にマウントし、外部導出端子を組み込んで構成した電力用半導体モジュールにおいて、
前記パワー半導体チップを、必要とする素子定格電圧よりも低い耐圧のチップで構成し、電力用半導体モジュールとして必要な素子定格電圧になるように前記パワー半導体チップを複数個直列接続し、これらを同時にスイッチングさせることで、見かけ上の耐圧を増加させたことを特徴とする電力用半導体モジュール。 A power semiconductor chip consisting of a voltage-driven semiconductor element and a diode chip element connected in reverse parallel to this is mounted on each insulating substrate in a package that combines a resin case and a metal base plate, and an external lead-out terminal is incorporated In the power semiconductor module composed of
The power semiconductor chip is configured with a chip having a withstand voltage lower than a required element rated voltage, and a plurality of the power semiconductor chips are connected in series so as to have a required element rated voltage as a power semiconductor module. A power semiconductor module characterized in that an apparent withstand voltage is increased by switching. 前記複数個直列接続されたパワー半導体チップのスイッチングタイミングのばらつきを抑制し、各素子電圧をバランスさせるために、各チップのゲート線またはエミッタ線をコアを介して互いに磁気結合し、かつこれらのコアをモジュール内に内蔵したことを特徴とする請求項１に記載の電力用半導体モジュール。
In order to suppress variations in switching timing of the plurality of power semiconductor chips connected in series and balance each element voltage, the gate lines or emitter lines of the chips are magnetically coupled to each other via the cores, and these cores The power semiconductor module according to claim 1, wherein the module is built in the module.
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JP2009095074A (en) * 2007-10-04 2009-04-30 Fuji Electric Systems Co Ltd Semiconductor switching circuit
EP2348635A3 (en) * 2010-01-19 2015-06-10 The Boeing Company Electromagnetic interference-resistant control device

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JPH07221264A (en) * 1994-02-04 1995-08-18 Hitachi Ltd Power semiconductor module and inverter device using it
JPH09172139A (en) * 1995-12-20 1997-06-30 Mitsubishi Electric Corp Semiconductor device
JP2002204578A (en) * 2001-01-09 2002-07-19 Fuji Electric Co Ltd Control device for series-connected voltage-driven semiconductor device

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JPH0738013A (en) * 1993-07-22 1995-02-07 Origin Electric Co Ltd Composite base member and power semiconductor device
JPH07221264A (en) * 1994-02-04 1995-08-18 Hitachi Ltd Power semiconductor module and inverter device using it
JPH09172139A (en) * 1995-12-20 1997-06-30 Mitsubishi Electric Corp Semiconductor device
JP2002204578A (en) * 2001-01-09 2002-07-19 Fuji Electric Co Ltd Control device for series-connected voltage-driven semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009095074A (en) * 2007-10-04 2009-04-30 Fuji Electric Systems Co Ltd Semiconductor switching circuit
EP2348635A3 (en) * 2010-01-19 2015-06-10 The Boeing Company Electromagnetic interference-resistant control device

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