JP2009049074A - 電界効果トランジスタ及び電界効果トランジスタの製造方法 - Google Patents
電界効果トランジスタ及び電界効果トランジスタの製造方法 Download PDFInfo
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Abstract
【解決手段】 基板上にゲート絶縁膜を介して形成されたゲート電極と、基板の第1の深さまで形成された、不純物を含有する不純物拡散領域と、第1の深さよりも深い第2の深さまで、基板に形成された、不活性物質を含有する不活性物質含有領域と、第2の深さよりも深い第3の深さまで、基板に形成された、不純物の拡散を抑制する拡散抑制物質を含有する拡散抑制領域と、を有し、基板はシリコンからなり、不活性物質は、シリコン以上に重い物質からなり、不活性物質は、ゲルマニウムである。
【選択図】図1
Description
本発明の第1の実施例において、図1から図6までの図は、n型MISトランジスタ10の構造及びn型MISトランジスタ10の製造方法を詳細に説明するものである。なお、MIS(Metal Insulator Semiconductor)トランジスタとは電界効果トランジスタのことをいう。第1の実施例におけるn型MISトランジスタ10の構造及び製造方法は、エクステンション領域17の下側、つまり第1の深さよりも深い第2の深さにおいてアモルファス領域14と結晶との界面が形成されることを特徴とする。そのため、アモルファス領域14内にエクステンション領域17が形成された後に拡散が発生するだけの熱負荷が印加されると、アモルファス領域14と結晶との界面に拡散抑制物質が偏析する。拡散抑制物質の偏析は、その界面における点欠陥を消費するため、エクステンション領域17におけるn型不純物の拡散が抑制される。エクステンション領域17におけるn型不純物の拡散が抑制されるため、エクステンション領域17における不純物濃度分布を急峻にすることができる。
本発明の第2の実施例において、図7から図12までの図は、p型MISトランジスタ30の構造及びp型MISトランジスタ30の製造方法を詳細に説明するものである。なお、MISトランジスタとは電界効果トランジスタのことをいう。第2の実施例におけるp型MISトランジスタ30の製造方法は、エクステンション領域37の下側、つまり第1の深さよりも深い第2の深さにおいてアモルファス領域34と結晶との界面が形成されることを特徴とする。そのため、アモルファス領域34内にエクステンション領域37が形成された後に拡散が発生するだけの熱負荷が印加されると、アモルファス領域34と結晶との界面に拡散抑制物質が偏析する。拡散抑制物質の偏析は、その界面における点欠陥を消費するため、エクステンション領域37におけるp型不純物の拡散が抑制される。エクステンション領域37におけるp型不純物の拡散が抑制されるため、エクステンション領域37における不純物濃度分布を急峻にすることができる。
(付記1)
基板上にゲート絶縁膜を介して形成されたゲート電極と、
前記基板の第1の深さまで形成された、不純物を含有する不純物拡散領域と、
前記第1の深さよりも深い第2の深さまで、前記基板に形成された、不活性物質を含有する不活性物質含有領域と、
前記第2の深さよりも深い第3の深さまで、前記基板に形成された、前記不純物の拡散を抑制する拡散抑制物質を含有する拡散抑制領域と、
を有することを特徴とする電界効果トランジスタ。
(付記2)
前記基板はシリコンからなり、前記不活性物質は、前記シリコン以上に重い物質からなることを特徴とする付記1に記載の電界効果トランジスタ。
(付記3)
前記不活性物質は、ゲルマニウムであることを特徴とする付記1又は付記2に記載の電界効果トランジスタ。
(付記4)
前記拡散抑制物質は、炭素であることを特徴とする付記1乃至付記3の何れかに記載の電界効果トランジスタ。
(付記5)
前記不純物はリン、砒素、ボロン、フッ化ボロン、又はクラスターボロンのいずれかであることを特徴とする付記1乃至付記4の何れかに記載の電界効果トランジスタ。
(付記6)
基板の第1の深さまでアモルファス領域を形成する工程と、
不純物の拡散を抑制する拡散抑制物質を含有する拡散抑制領域を、前記第1の深さより深い第2の深さまで、前記基板に形成する工程と、
前記不純物を有する不純物拡散領域を、前記第1の深さよりも浅い第3の深さまで、前記基板に形成する工程と、
前記基板を熱処理する工程と、
を含むことを特徴とする電界効果トランジスタの製造方法。
(付記7)
前記アモルファス領域は、前記不活性物質をイオン注入して形成することを特徴とする付記6に記載の電界効果トランジスタの製造方法。
(付記8)
前記基板はシリコンからなり、前記不活性物質は、前記シリコン以上に重い物質からなることを特徴とする付記6又は付記7に記載の電界効果トランジスタの製造方法。
(付記9)
前記不活性物質は、ゲルマニウムであることを特徴とする付記6乃至付記8の何れかに記載の電界効果トランジスタの製造方法。
(付記10)
前記拡散抑制物質は、炭素であることを特徴とする付記6乃至付記9の何れかに記載の電界効果トランジスタの製造方法。
(付記11)
前記不純物はリン又はボロンであることを特徴とする付記6乃至付記10のいずれかに記載の電界効果トランジスタの製造方法。
11 p型シリコン基板
12 ゲート絶縁膜
13 ゲート電極
14 アモルファス領域
14a 不活性物質含有領域
15 ポケット領域
16 拡散抑制領域
17 エクステンション領域
18 サイドウォール
19a 不純物濃度が高いソース領域
19b 不純物濃度が高いドレイン領域
20 シリサイド層
21 リンの濃度分布
22 インジウムの濃度分布
23 リンの濃度分布
24 炭素の濃度分布
25 アモルファス領域の形成範囲
26a ソース領域
26b ドレイン領域
30 p型MISトランジスタ
31 n型シリコン基板
32 ゲート絶縁膜
33 ゲート電極
34 アモルファス領域
34a 不活性物質含有領域
35 ポケット領域
36 拡散抑制領域
37 エクステンション領域
38 サイドウォール
39a 不純物濃度が高いソース領域
39b 不純物濃度が高いドレイン領域
40 シリサイド層
41 アンチモンの濃度分布
42 ボロンの濃度分布
43 ボロンの濃度分布
44 ボロンの濃度分布
45 炭素の濃度分布
46 アモルファス領域の形成範囲
47a ソース領域
47b ドレイン領域
50 活性領域
60 素子分離領域
Claims (10)
- 基板上にゲート絶縁膜を介して形成されたゲート電極と、
前記基板の第1の深さまで形成された、不純物を含有する不純物拡散領域と、
前記第1の深さよりも深い第2の深さまで、前記基板に形成された、不活性物質を含有する不活性物質含有領域と、
前記第2の深さよりも深い第3の深さまで、前記基板に形成された、前記不純物の拡散を抑制する拡散抑制物質を含有する拡散抑制領域と、
を有することを特徴とする電界効果トランジスタ。 - 前記基板はシリコンからなり、前記不活性物質は、前記シリコン以上に重い物質からなることを特徴とする請求項1に記載の電界効果トランジスタ。
- 前記不活性物質は、ゲルマニウムであることを特徴とする請求項1又は請求項2に記載の電界効果トランジスタ。
- 前記拡散抑制物質は、炭素であることを特徴とする請求項1乃至請求項3の何れかに記載の電界効果トランジスタ。
- 前記不純物はリン、砒素、ボロン、フッ化ボロン、又はクラスターボロンのいずれかであることを特徴とする請求項1乃至請求項4の何れかに記載の電界効果トランジスタ。
- 基板の第4の深さまでアモルファス領域を形成する工程と、
不純物の拡散を抑制する拡散抑制物質を含有する拡散抑制領域を、前記第4の深さよりも深い第5の深さまで、前記基板に形成する工程と、
前記第4の深さよりも浅い第6の深さまで、前記基板に前記不純物を有する不純物拡散領域を形成する工程と、
前記基板を熱処理する工程と、
を含むことを特徴とする電界効果トランジスタの製造方法。 - 前記アモルファス領域は、前記不活性物質をイオン注入して形成することを特徴とする請求項6に記載の電界効果トランジスタの製造方法。
- 前記基板はシリコンからなり、前記不活性物質は、前記シリコン以上に重い物質からなることを特徴とする請求項6又は請求項7に記載の電界効果トランジスタの製造方法。
- 前記不活性物質は、ゲルマニウムであることを特徴とする請求項6乃至請求項8の何れかに記載の電界効果トランジスタの製造方法。
- 前記拡散抑制物質は、炭素であることを特徴とする請求項6乃至請求項9の何れかに記載の電界効果トランジスタの製造方法。
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US12/171,676 US7892933B2 (en) | 2007-08-15 | 2008-07-11 | Semiconductor device and method of manufacturing semiconductor device |
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JP5159708B2 (ja) * | 2009-06-17 | 2013-03-13 | パナソニック株式会社 | 半導体装置及びその製造方法 |
US8470700B2 (en) * | 2010-07-22 | 2013-06-25 | Globalfoundries Singapore Pte. Ltd. | Semiconductor device with reduced contact resistance and method of manufacturing thereof |
US8884341B2 (en) | 2011-08-16 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits |
US9064796B2 (en) * | 2012-08-13 | 2015-06-23 | Infineon Technologies Ag | Semiconductor device and method of making the same |
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