JP2009032720A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP2009032720A JP2009032720A JP2007192026A JP2007192026A JP2009032720A JP 2009032720 A JP2009032720 A JP 2009032720A JP 2007192026 A JP2007192026 A JP 2007192026A JP 2007192026 A JP2007192026 A JP 2007192026A JP 2009032720 A JP2009032720 A JP 2009032720A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- semiconductor device
- recess
- positioning mark
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
- H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
- H01L2224/211—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01011—Sodium [Na]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01018—Argon [Ar]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0106—Neodymium [Nd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
【解決手段】外部接続用パッド23とヴィア形成用の位置決めマーク22が形成された半導体チップ20と、複数のヴィア14を有する非感光性樹脂を成分とする絶縁層12と、ヴィア14を介して外部接続用パッド23と電気的に接続されるとともに少なくとも一部が絶縁層12上に形成された配線15と、を備える。絶縁層12は、位置決めマーク23上の部分に凹部13が形成されている。凹部13の底面は、絶縁層12のみである。
【選択図】図1
Description
を含むことを特徴とする。
10 配線基板
11 支持基板
12、16、18 絶縁層
13、13´ 凹部
14 ヴィア
15、17、19 配線
20 半導体チップ
21 半導体活性層
22 位置決めマーク
23 外部接続用パッド
120 ICチップ
122 ソルダーレジスト
123 位置決めマーク
124 パッド
130 コア基板
131 位置決めマーク
132 凹部
134 接着材料
136 無電解めっき膜
137 電解めっき膜
138 トランジション層
150、151 層間樹脂絶縁層
158、159 導体回路
160、161 バイアホール
170 ソルダーレジスト層
171 開口
172 ニッケルめっき層
174 金めっき層
176 半田バンプ
Claims (13)
- 半導体活性層側に外部接続用パッドとヴィア形成用の少なくとも1つ以上の位置決めマークとが形成された半導体チップと、
前記外部接続用パッドと整合する位置に形成された複数のヴィアを有する非感光性樹脂を成分とする絶縁層と、
前記ヴィアを介して前記外部接続用パッドと電気的に接続されるとともに少なくとも一部が前記絶縁層上に形成された配線と、
を備え、
前記絶縁層は、前記位置決めマーク上の部分に凹部が形成されていることを特徴とする半導体装置。 - 前記凹部の底面は、前記絶縁層のみであることを特徴とする請求項1記載の半導体装置。
- 前記凹部の底面は、前記位置決めマークに到達していることを特徴とする請求項1記載の半導体装置。
- 前記凹部の底面は、前記半導体活性層に到達していないことを特徴とする請求項3記載の半導体装置。
- 前記凹部にも配線が形成されていることを特徴とする請求項1乃至4のいずれか一に記載の半導体装置。
- 前記絶縁層は、フィラーを含有していることを特徴とする請求項1乃至5のいずれか一に記載の半導体装置。
- 前記絶縁層は、半透明又は不透明であることを特徴とする請求項1乃至6のいずれか一に記載の半導体装置。
- 前記凹部の径は、前記ヴィアの径よりも大きいことを特徴とする請求項1乃至7のいずれか一に記載の半導体装置。
- 前記凹部の底面は、前記位置決めマークを包含していることを特徴とする請求項1乃至8のいずれか一に記載の半導体装置。
- 半導体活性層側に外部接続用パッドとヴィア形成用の位置決めマークとが形成された半導体チップ上に、非感光性樹脂を成分とする絶縁層を形成する工程と、
第1のレーザ照射により前記位置決めマーク上の前記絶縁層を除去することで、前記絶縁層に凹部を形成する工程と、
前記位置決めマークを基準として第2のレーザ照射により前記絶縁層の前記外部接続用パッドと整合する位置にヴィアを形成する工程と、
前記ヴィアを介して前記外部接続用パッドと電気的に接続するとともに少なくとも一部が前記絶縁層上に形成された配線を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記凹部を形成する工程では、前記凹部の底面にて位置決めマークが露出しないように前記凹部を形成することを特徴とする請求項10記載の半導体装置の製造方法。
- 前記凹部を形成する工程では、前記凹部の底面にて位置決めマークが露出するように前記凹部を形成することを特徴とする請求項10記載の半導体装置の製造方法。
- 前記凹部を形成する工程では、前記凹部の底面にて前記半導体活性層が露出しないように前記凹部を形成することを特徴とする請求項10記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007192026A JP5263918B2 (ja) | 2007-07-24 | 2007-07-24 | 半導体装置及びその製造方法 |
CNA2008101343249A CN101355064A (zh) | 2007-07-24 | 2008-07-24 | 半导体装置及其制造方法 |
US12/178,683 US7999401B2 (en) | 2007-07-24 | 2008-07-24 | Semiconductor device and method of manufacturing same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007192026A JP5263918B2 (ja) | 2007-07-24 | 2007-07-24 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009032720A true JP2009032720A (ja) | 2009-02-12 |
JP5263918B2 JP5263918B2 (ja) | 2013-08-14 |
Family
ID=40294557
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007192026A Expired - Fee Related JP5263918B2 (ja) | 2007-07-24 | 2007-07-24 | 半導体装置及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7999401B2 (ja) |
JP (1) | JP5263918B2 (ja) |
CN (1) | CN101355064A (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015211134A (ja) * | 2014-04-25 | 2015-11-24 | 新光電気工業株式会社 | 配線基板、及び配線基板の製造方法 |
WO2018085262A1 (en) * | 2016-11-07 | 2018-05-11 | Corning Incorporated | Delayed via formation in electronic devices |
WO2018181552A1 (ja) * | 2017-03-31 | 2018-10-04 | 国立研究開発法人産業技術総合研究所 | ウェハ上のアライメントマークを用いる半導体パッケージの製造方法 |
JP2020161608A (ja) * | 2019-03-26 | 2020-10-01 | Tdk株式会社 | 電子部品内蔵回路基板及びその製造方法 |
JP2020161607A (ja) * | 2019-03-26 | 2020-10-01 | Tdk株式会社 | 電子部品内蔵回路基板及びその製造方法 |
WO2021205685A1 (ja) * | 2020-04-09 | 2021-10-14 | 株式会社村田製作所 | 集合基板の製造方法及び集合基板 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9087847B2 (en) | 2012-08-14 | 2015-07-21 | Bridge Semiconductor Corporation | Thermally enhanced interconnect substrate with embedded semiconductor device and built-in stopper and method of making the same |
US8901435B2 (en) | 2012-08-14 | 2014-12-02 | Bridge Semiconductor Corporation | Hybrid wiring board with built-in stopper, interposer and build-up circuitry |
US9000587B1 (en) * | 2013-03-12 | 2015-04-07 | Maxim Integrated Products, Inc. | Wafer-level thin chip integration |
US9411234B2 (en) | 2014-10-01 | 2016-08-09 | Seagate Technology Llc | Writer pole formation |
JP7046639B2 (ja) * | 2018-02-21 | 2022-04-04 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
CN111524873B (zh) | 2019-02-01 | 2022-05-13 | 台达电子企业管理(上海)有限公司 | 嵌入式封装模块及其封装方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0936522A (ja) * | 1995-07-14 | 1997-02-07 | Fuji Kiko Denshi Kk | プリント配線板における回路形成方法 |
JP2001332863A (ja) * | 2000-02-25 | 2001-11-30 | Ibiden Co Ltd | 多層プリント配線板の製造方法 |
JP2002224878A (ja) * | 2000-10-26 | 2002-08-13 | Toshiba Corp | レーザ加工方法、レーザ加工装置および半導体装置の製造方法 |
JP2002263877A (ja) * | 2001-03-09 | 2002-09-17 | Toshiba Corp | レーザ加工装置 |
JP2002361464A (ja) * | 2001-05-31 | 2002-12-18 | Mitsubishi Electric Corp | レーザ加工方法および装置 |
JP2004172491A (ja) * | 2002-11-21 | 2004-06-17 | Rohm Co Ltd | 半導体装置の製造方法 |
JP2005340785A (ja) * | 2004-04-30 | 2005-12-08 | Hitachi Via Mechanics Ltd | プリント基板およびプリント基板の加工方法並びにプリント基板の製造方法 |
JP2007150002A (ja) * | 2005-11-29 | 2007-06-14 | Tdk Corp | 半導体ic内蔵基板及びその製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07249558A (ja) * | 1994-03-09 | 1995-09-26 | Nikon Corp | 位置合わせ方法 |
US6303459B1 (en) * | 1999-11-15 | 2001-10-16 | Taiwan Semiconductor Manufacturing Company | Integration process for Al pad |
EP1990833A3 (en) * | 2000-02-25 | 2010-09-29 | Ibiden Co., Ltd. | Multilayer printed circuit board and multilayer printed circuit board manufacturing method |
US20020102812A1 (en) * | 2001-01-31 | 2002-08-01 | Jeenh-Bang Yeh | Method for improving alignment precision in forming color filter array |
US7507633B2 (en) * | 2006-03-07 | 2009-03-24 | International Business Machines Corproation | Method and structure for improved alignment in MRAM integration |
JP5076407B2 (ja) * | 2006-09-05 | 2012-11-21 | ミツミ電機株式会社 | 半導体装置及びその製造方法 |
-
2007
- 2007-07-24 JP JP2007192026A patent/JP5263918B2/ja not_active Expired - Fee Related
-
2008
- 2008-07-24 US US12/178,683 patent/US7999401B2/en not_active Expired - Fee Related
- 2008-07-24 CN CNA2008101343249A patent/CN101355064A/zh active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0936522A (ja) * | 1995-07-14 | 1997-02-07 | Fuji Kiko Denshi Kk | プリント配線板における回路形成方法 |
JP2001332863A (ja) * | 2000-02-25 | 2001-11-30 | Ibiden Co Ltd | 多層プリント配線板の製造方法 |
JP2002224878A (ja) * | 2000-10-26 | 2002-08-13 | Toshiba Corp | レーザ加工方法、レーザ加工装置および半導体装置の製造方法 |
JP2002263877A (ja) * | 2001-03-09 | 2002-09-17 | Toshiba Corp | レーザ加工装置 |
JP2002361464A (ja) * | 2001-05-31 | 2002-12-18 | Mitsubishi Electric Corp | レーザ加工方法および装置 |
JP2004172491A (ja) * | 2002-11-21 | 2004-06-17 | Rohm Co Ltd | 半導体装置の製造方法 |
JP2005340785A (ja) * | 2004-04-30 | 2005-12-08 | Hitachi Via Mechanics Ltd | プリント基板およびプリント基板の加工方法並びにプリント基板の製造方法 |
JP2007150002A (ja) * | 2005-11-29 | 2007-06-14 | Tdk Corp | 半導体ic内蔵基板及びその製造方法 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015211134A (ja) * | 2014-04-25 | 2015-11-24 | 新光電気工業株式会社 | 配線基板、及び配線基板の製造方法 |
WO2018085262A1 (en) * | 2016-11-07 | 2018-05-11 | Corning Incorporated | Delayed via formation in electronic devices |
WO2018181552A1 (ja) * | 2017-03-31 | 2018-10-04 | 国立研究開発法人産業技術総合研究所 | ウェハ上のアライメントマークを用いる半導体パッケージの製造方法 |
JPWO2018181552A1 (ja) * | 2017-03-31 | 2019-11-14 | 国立研究開発法人産業技術総合研究所 | ウェハ上のアライメントマークを用いる半導体パッケージの製造方法 |
US11056410B2 (en) | 2017-03-31 | 2021-07-06 | National Institute Of Advanced Industrial Science And Technology | Method of manufacturing semiconductor package using alignment mark on wafer |
JP2020161608A (ja) * | 2019-03-26 | 2020-10-01 | Tdk株式会社 | 電子部品内蔵回路基板及びその製造方法 |
JP2020161607A (ja) * | 2019-03-26 | 2020-10-01 | Tdk株式会社 | 電子部品内蔵回路基板及びその製造方法 |
JP7272046B2 (ja) | 2019-03-26 | 2023-05-12 | Tdk株式会社 | 電子部品内蔵回路基板及びその製造方法 |
JP7302224B2 (ja) | 2019-03-26 | 2023-07-04 | Tdk株式会社 | 電子部品内蔵回路基板 |
WO2021205685A1 (ja) * | 2020-04-09 | 2021-10-14 | 株式会社村田製作所 | 集合基板の製造方法及び集合基板 |
Also Published As
Publication number | Publication date |
---|---|
CN101355064A (zh) | 2009-01-28 |
US7999401B2 (en) | 2011-08-16 |
US20090026636A1 (en) | 2009-01-29 |
JP5263918B2 (ja) | 2013-08-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5263918B2 (ja) | 半導体装置及びその製造方法 | |
JP6373574B2 (ja) | 回路基板及びその製造方法 | |
US10043726B2 (en) | Embedded component substrate with a metal core layer having an open cavity and pad electrodes at the bottom of the cavity | |
JP5188426B2 (ja) | 半導体装置及びその製造方法、電子装置 | |
KR100736635B1 (ko) | 베어칩 내장형 인쇄회로기판 및 그 제조 방법 | |
JP5164362B2 (ja) | 半導体内臓基板およびその製造方法 | |
US20100288535A1 (en) | Electronic component-embedded printed circuit board comprising cooling member and method of manufacturing the same | |
JP2008300507A (ja) | 配線基板とその製造方法 | |
JP3938921B2 (ja) | 半導体ic内蔵モジュールの製造方法 | |
KR20100050457A (ko) | 핀 인터페이스를 갖는 다층의 배선 요소 | |
US9324580B2 (en) | Process for fabricating a circuit substrate | |
JP2007318098A (ja) | 回路装置および回路装置の製造方法 | |
TWI585926B (zh) | 設有加強層及整合雙路由電路之半導體組體及製作方法 | |
WO2011024939A1 (ja) | 半導体装置およびその製造方法 | |
KR20100065635A (ko) | 집적회로 패키지 내장 인쇄회로기판 및 그 제조방법 | |
JP2008091639A (ja) | 電子装置およびその製造方法 | |
JP2008091640A (ja) | 電子装置およびその製造方法 | |
JP2016192475A5 (ja) | ||
JP2008205123A (ja) | 電子部品内蔵型配線基板及びその実装部品 | |
JPWO2009101904A1 (ja) | 半導体装置及びその製造方法 | |
JP5599860B2 (ja) | 半導体パッケージ基板の製造方法 | |
JP2006134914A (ja) | 電子部品内蔵モジュール | |
KR100722615B1 (ko) | 플립칩 패키지 기판의 제조방법 | |
KR101257457B1 (ko) | 집적회로 칩이 내장된 인쇄회로기판의 제조 방법 | |
KR101148601B1 (ko) | 아이씨 모듈 및 이의 제조 방법과 아이씨 모듈을 이용한 임베디드 인쇄회로기판 및 이의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100514 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20111111 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20111122 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120123 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120807 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120910 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130402 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130426 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 5263918 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |