JP2008300607A - Chip resistor - Google Patents

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JP2008300607A
JP2008300607A JP2007144760A JP2007144760A JP2008300607A JP 2008300607 A JP2008300607 A JP 2008300607A JP 2007144760 A JP2007144760 A JP 2007144760A JP 2007144760 A JP2007144760 A JP 2007144760A JP 2008300607 A JP2008300607 A JP 2008300607A
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thick film
electrode
resistor
surface electrode
electrodes
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JP5329773B2 (en
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Takahiro Matsui
貴弘 松井
Hisakazu Nagata
久和 永田
Seiji Karasawa
誠治 唐澤
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Koa Corp
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Koa Corp
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Priority to PCT/JP2008/060251 priority patent/WO2008149876A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/003—Thick film resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/148—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals embracing or surrounding the resistive element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/006—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistor chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/02—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistors with envelope or housing

Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip resistor that has a high resistance against sulfide gas, with no increase of manufacturing processes. <P>SOLUTION: The chip resistor includes a pair of thick film upper surface electrodes 22 and 23 arranged respectively on the upper and lower surfaces of a ceramics substrate 11, a pair of thick film lower surface electrodes 14 and 15, a thick film resistor 16 arranged to bridge between the pair of thick film upper surface electrodes, a protective film 17 which covers the thick film resistor, end face electrodes 18 and 19 which are arranged on the end surfaces of the ceramics substrate to connect the thick film upper surface electrode and the thick film lower surface electrode, and plated layers 20 and 21 which cover the portion of the thick film upper surface electrode that is not covered with the protective film, the end face electrode, and the thick film lower surface electrode. The metal material contained in the thick film upper surface electrodes 22 and 23 contains Ag as main component, with Pd and Au contained as well. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、厚膜角形チップ抵抗器に係り、特に硫化ガスに対して耐性を高めた電極の構成に関する。   The present invention relates to a thick film rectangular chip resistor, and more particularly to a configuration of an electrode having improved resistance to sulfur gas.

厚膜角形チップ抵抗器においては、図３に示すように、セラミックス基板１１の上下面にそれぞれ配置した一対の厚膜上面電極１２，１３と一対の厚膜下面電極１４，１５と、一対の厚膜上面電極１２，１３間にまたがって配置した厚膜抵抗体１６と、抵抗体１６を覆う保護膜１７と、セラミックス基板１１の端面に配置した厚膜上面電極１２，１３と厚膜下面電極１４，１５とを接続する端面電極１８，１９と、保護膜１７に覆われていない厚膜上面電極１２，１３の部分と端面電極１８，１９と厚膜下面電極１４，１５とを覆うメッキ層２０，２１とを備えている。   In the thick film rectangular chip resistor, as shown in FIG. 3, a pair of thick film upper surface electrodes 12, 13 and a pair of thick film lower surface electrodes 14, 15 respectively disposed on the upper and lower surfaces of the ceramic substrate 11, and a pair of thicknesses. The thick film resistor 16 disposed between the film upper surface electrodes 12 and 13, the protective film 17 covering the resistor 16, the thick film upper surface electrodes 12 and 13 and the thick film lower surface electrode 14 disposed on the end surface of the ceramic substrate 11. , 15, and the plating layer 20 covering the thick film upper surface electrodes 12, 13 not covered with the protective film 17, the end surface electrodes 18, 19 and the thick film lower surface electrodes 14, 15. , 21.

厚膜上面電極１２，１３または厚膜下面電極１４，１５の材料として、一般にＡｇ系材料またはＡｇ−Ｐｄ系材料が用いられる。しかしながら、そのような厚膜チップ抵抗器を硫化ガスが含まれる雰囲気で使用した場合に、特に上面電極１２，１３のＡｇ系材料が硫化銀を形成し、導通不良や断線が生じる場合があるという課題がある。そのような課題に対して、例えば以下の特許文献１，２，３により対応案が提案されている。
特開平７−１６９６０１号公報 特開平７−１７６４０２号公報 特開２００２−０６４００３号公報 As a material for the thick film upper surface electrodes 12 and 13 or the thick film lower surface electrodes 14 and 15, an Ag-based material or an Ag—Pd-based material is generally used. However, when such a thick film chip resistor is used in an atmosphere containing sulfide gas, the Ag-based material of the upper surface electrodes 12 and 13 may form silver sulfide, which may cause poor conduction or disconnection. There are challenges. For example, the following patent documents 1, 2, and 3 have proposed countermeasures against such problems.
Japanese Patent Laid-Open No. 7-169601 JP 7-176402 A JP 2002-064003 A

特許文献１では、第１上面電極層２の一部に重なるように、厚膜Ａｇペーストを用いて形成した第２上面電極層５を設けることが提案されている（要約参照）。第２上面電極層５は、保護層６の上面の一部に重なるように形成されているので、第１上面電極層２は硫化ガスに浸食されることなく、断線を起こしにくくなることが記載されている。   In Patent Document 1, it is proposed to provide a second upper surface electrode layer 5 formed using a thick film Ag paste so as to overlap a part of the first upper surface electrode layer 2 (see summary). Since the second upper surface electrode layer 5 is formed so as to overlap a part of the upper surface of the protective layer 6, it is described that the first upper surface electrode layer 2 is not eroded by the sulfurized gas and hardly breaks. Has been.

特許文献２では、アルミナ基板１上の銀系厚膜による第一上面電極層３と、第一上面電極層３を完全に覆う貴金属系薄膜による第二上面電極層４、第二上面電極層４の一部に重なるルテニウム系の抵抗層２を設けることが提案されている。ここで、貴金属系薄膜は、金−レジネートを用いており（００１０欄）、これにより第１上面電極層３の硫化が妨げられることが記載されている。   In Patent Document 2, a first upper surface electrode layer 3 made of a silver-based thick film on an alumina substrate 1, a second upper surface electrode layer 4 made of a noble metal thin film that completely covers the first upper surface electrode layer 3, and a second upper surface electrode layer 4. It has been proposed to provide a ruthenium-based resistance layer 2 that overlaps a portion of the above. Here, it is described that the noble metal-based thin film uses gold-resinate (column 0010), which prevents the first upper surface electrode layer 3 from being sulfided.

特許文献３では、保護層４０とメッキ層２６の接する部分の下層であって、上面電極層２２の上面に、上面電極保護層２３が形成され、この上面電極保護層２３は、耐硫化特性に優れた材質、例えば、パラジウムが５．０％以上含有した銀系厚膜により形成されていることが提案されている。これにより、上面電極層２２に、耐硫化特性のない材質を使用しても、上面電極層２２が硫化されることがないので、断線等チップ抵抗器の故障を引き起こす危険性をなくすことができることが記載されている（０００７欄）。   In Patent Document 3, an upper surface electrode protective layer 23 is formed on the upper surface of the upper surface electrode layer 22, which is a lower layer of a portion where the protective layer 40 and the plating layer 26 are in contact with each other. It has been proposed to be formed of an excellent material, for example, a silver-based thick film containing 5.0% or more of palladium. As a result, even if a material having no sulfidation resistance is used for the upper electrode layer 22, the upper electrode layer 22 is not sulfided, so that the risk of causing a failure of the chip resistor such as disconnection can be eliminated. Is described (column 0007).

しかしながら、上記特許文献に記載の方法では、いずれもＡｇ系の電極を硫化から保護する電極保護層（特許文献１では第２上面電極層５、特許文献２では第２上面電極層４、特許文献３では上面電極保護層２３）を形成するものである。従って、上面電極の層数が増えるため、製造工程が増えてしまい、製造コストが上昇するという課題がある。   However, in each of the methods described in the above patent documents, an electrode protective layer that protects the Ag-based electrode from sulfidation (the second upper electrode layer 5 in Patent Document 1, the second upper electrode layer 4 in Patent Document 2, and the patent document). 3 is to form the upper surface electrode protective layer 23). Therefore, since the number of layers of the upper surface electrode increases, there is a problem that the manufacturing process increases and the manufacturing cost increases.

本発明は上述した事情に基づいてなされたもので、製造工程を増加させることなく、硫化ガスに対して高い耐性を有するチップ抵抗器を提供することを目的とする。   The present invention has been made based on the above-described circumstances, and an object of the present invention is to provide a chip resistor having high resistance to sulfurized gas without increasing the number of manufacturing steps.

本発明のチップ抵抗器は、セラミックス基板の上下面にそれぞれ配置した一対の厚膜上面電極と、一対の厚膜下面電極と、前記一対の厚膜上面電極間にまたがって配置した厚膜抵抗体と、前記厚膜抵抗体を覆う保護膜と、前記セラミックス基板の端面に配置した前記厚膜上面電極と前記厚膜下面電極とを接続する端面電極と、前記保護膜に覆われていない前記厚膜上面電極の部分と前記端面電極と前記厚膜下面電極とを覆うメッキ層とを備えたチップ抵抗器において、前記厚膜上面電極に含まれる金属材料が、Ａｇを主成分とし、更にＰｄとＡｕを含むことを特徴とする。   The chip resistor of the present invention includes a pair of thick film upper surface electrodes disposed on the upper and lower surfaces of the ceramic substrate, a pair of thick film lower surface electrodes, and a thick film resistor disposed across the pair of thick film upper surface electrodes. A protective film covering the thick film resistor, an end surface electrode connecting the thick film upper surface electrode and the thick film lower surface electrode disposed on the end surface of the ceramic substrate, and the thickness not covered by the protective film In a chip resistor comprising a film upper surface electrode portion, a plating layer covering the end surface electrode and the thick film lower surface electrode, the metal material contained in the thick film upper surface electrode is mainly composed of Ag, and further Pd It is characterized by containing Au.

本発明のチップ抵抗器によれば、厚膜上面電極に含まれる金属材料が、Ａｇを主成分とし、更にＰｄとＡｕを含むことで、硫化ガスに対する耐性を高め、Ａｇ系材料を主体とする厚膜上面電極の硫化の進行をきわめて良好に抑制することができる。すなわち、本発明の厚膜上面電極の構成によれば、硫化試験において硫化雰囲気に曝しても、厚膜上面電極に変色すら生ぜず、外観上の変化が認められない。従って、電極ペースト材料の組成を変更するのみで、工程を増加させることなく、硫化ガスに対して高い耐性を有するチップ抵抗器を提供することができる。   According to the chip resistor of the present invention, the metal material contained in the thick film upper surface electrode contains Ag as a main component and further contains Pd and Au, thereby improving the resistance to the sulfide gas and mainly using the Ag-based material. The progress of sulfidation of the thick film upper surface electrode can be suppressed very well. That is, according to the structure of the thick film upper surface electrode of the present invention, even if it is exposed to the sulfurizing atmosphere in the sulfidation test, the thick film upper surface electrode is not even discolored and no change in appearance is recognized. Therefore, it is possible to provide a chip resistor having high resistance to the sulfide gas without changing the number of steps only by changing the composition of the electrode paste material.

また、厚膜抵抗体の焼成に際して、通常のＡｇ系またはＡｇ−Ｐｄ系電極であると、厚膜抵抗体の部分にＡｇ成分が拡散し、抵抗値変化の原因になるが、ＡｕとＰｄを含むＡｇ系電極であると、Ａｇの厚膜抵抗体への拡散が抑制され、抵抗値変化を抑制できる。従って、電極ペースト材料の組成を変更するのみで、抵抗値の高い安定性を有するチップ抵抗器を提供することができる。   Further, when the thick film resistor is fired, if it is a normal Ag-based or Ag-Pd-based electrode, the Ag component diffuses into the thick film resistor and causes a change in the resistance value. When the Ag-based electrode is included, diffusion of Ag into the thick film resistor is suppressed, and a change in resistance value can be suppressed. Therefore, it is possible to provide a chip resistor having a high resistance value and stability only by changing the composition of the electrode paste material.

以下、本発明の一実施形態について、添付図面を参照して説明する。図１は本発明のチップ抵抗器を示し、図２はその製造工程を示す。なお、各図中、同一または相当する部材または要素には、同一の符号を付して説明する。   Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 shows a chip resistor of the present invention, and FIG. 2 shows its manufacturing process. In addition, in each figure, the same code | symbol is attached | subjected and demonstrated to the same or equivalent member or element.

本発明のチップ抵抗器は、厚膜上面電極２２，２３の金属材料がＡｇを主成分とし、更にＰｄとＡｕを含む点を除いて、従来技術のチップ抵抗器と異なるものではない。すなわち、図１に示すように、アルミナセラミックス基板１１の上下面に配置した一対の厚膜上面電極２２，２３と一対の厚膜下面電極１４，１５と、一対の上面電極２２，２３間にまたがって配置した酸化ルテニウム系厚膜抵抗体１６とを備えている。ここで、厚膜上面電極２２，２３に含まれる金属材料が、Ａｇを主成分とし、Ｐｄが１５〜２５ｗｔ％、Ａｕが１〜２０ｗｔ％含まれることが好ましい。このように、抵抗体１６と直接接続される上面電極２２，２３にのみ、金属材料が、Ａｇを主成分とし、更にＰｄとＡｕを含む電極材料を用い、厚膜下面電極１４，１５には、従来どおりＡｕを含まないＡｇ系またはＡｇ−Ｐｄ系の電極材料が用いられる。   The chip resistor of the present invention is not different from the chip resistor of the prior art except that the metal material of the thick film upper surface electrodes 22 and 23 is mainly composed of Ag and further contains Pd and Au. That is, as shown in FIG. 1, the pair of thick film upper surface electrodes 22, 23 and the pair of thick film lower surface electrodes 14, 15 disposed on the upper and lower surfaces of the alumina ceramic substrate 11 and the pair of upper surface electrodes 22, 23 are straddled. And a ruthenium oxide thick film resistor 16 disposed in the same manner. Here, it is preferable that the metal material contained in the thick film upper surface electrodes 22 and 23 contains Ag as a main component, Pd is 15 to 25 wt%, and Au is 1 to 20 wt%. As described above, only the upper surface electrodes 22 and 23 directly connected to the resistor 16 are made of a metal material containing Ag as a main component and further including Pd and Au. As usual, an Ag-based or Ag-Pd-based electrode material not containing Au is used.

さらに、このチップ抵抗器では、厚膜抵抗体１６を覆う保護膜１７と、アルミナセラミックス基板１１の端面に配置した厚膜上面電極２２，２３と厚膜下面電極１４，１５とを接続する端面電極１８，１９とを備える。また、保護膜１７に覆われていない厚膜上面電極２２，２３の部分と、端面電極１８，１９と、厚膜下面電極１４，１５とを被覆するメッキ層２０，２１とを備える。保護膜１７は、ガラス系絶縁材料の第１保護コート１７ａと、エポキシ樹脂系絶縁材料の第２保護コート１７ｂとの二層から構成される。端面電極１８，１９は、スパッタリングにより形成したＮｉの薄膜から構成される。メッキ層２０，２１は、Ｎｉ等の下地メッキ層とＳｎ等のメッキ層とから構成される。   Further, in this chip resistor, the protective film 17 that covers the thick film resistor 16, the end face electrodes that connect the thick film upper surface electrodes 22, 23 and the thick film lower face electrodes 14, 15 disposed on the end face of the alumina ceramic substrate 11. 18 and 19. The thick film upper surface electrodes 22 and 23 not covered with the protective film 17, the end surface electrodes 18 and 19, and the plated layers 20 and 21 covering the thick film lower surface electrodes 14 and 15 are provided. The protective film 17 includes two layers of a first protective coat 17a made of a glass-based insulating material and a second protective coat 17b made of an epoxy resin-based insulating material. The end face electrodes 18 and 19 are made of a Ni thin film formed by sputtering. The plating layers 20 and 21 are composed of a base plating layer such as Ni and a plating layer such as Sn.

従って、図示するように、保護膜１７とメッキ層２０の境界部分Ａが厚膜上面電極２２上に位置し、保護膜１７とメッキ層２１の境界部分Ｂが上面電極２３上に位置する。これにより、保護膜１７とメッキ層２０，２１の境界部分Ａ，Ｂから硫化ガスが浸入するが、その浸入部分に本発明の厚膜上面電極を用いることで、効果的に硫化の進行を抑制することができる。   Therefore, as shown in the drawing, the boundary portion A between the protective film 17 and the plating layer 20 is located on the thick film upper surface electrode 22, and the boundary portion B between the protective film 17 and the plating layer 21 is located on the upper surface electrode 23. As a result, the sulfide gas enters from the boundary portions A and B between the protective film 17 and the plating layers 20 and 21. By using the thick film upper surface electrode of the present invention at the intrusion portion, the progress of sulfidation is effectively suppressed. can do.

次に、厚膜上面電極２２，２３に含まれる金属材料が、Ａｇを主成分とし、Ｐｄが１５〜２５ｗｔ％、Ａｕが１〜２０ｗｔ％含まれることが硫化ガスに対する耐性向上の点で好ましい根拠について説明する。これは以下に述べる実験結果に基づくものである。   Next, it is preferable that the metal material contained in the thick film upper surface electrodes 22 and 23 contains Ag as a main component, Pd is 15 to 25 wt%, and Au is 1 to 20 wt% from the viewpoint of improving resistance to sulfur gas. Will be described. This is based on the experimental results described below.

まず、上面電極材料として、有機成分１７〜２０ｗｔ％とガラス成分２〜３ｗｔ％と残部下表の金属成分からなる電極材料ペーストを準備する。この電極材料ペーストを試料１〜１１のセラミックス基板上に印刷焼成し、硫黄が含まれる液体中で約１００℃に加熱し、３０００時間浸漬してその変化を観察した。なお、有機成分は焼成時にほとんど消失するので、電極材料における金属成分の配合割合は、下表のとおりとなり、外観の観察結果も下表のとおりである。   First, an electrode material paste comprising an organic component of 17 to 20 wt%, a glass component of 2 to 3 wt%, and the balance of the metal components shown below is prepared as the upper electrode material. This electrode material paste was printed and fired on the ceramic substrates of Samples 1 to 11, heated to about 100 ° C. in a liquid containing sulfur, and immersed for 3000 hours to observe the change. In addition, since an organic component almost lose | disappears at the time of baking, the compounding ratio of the metal component in an electrode material becomes as the following table, and the observation result of an external appearance is also as the following table.

Figure 2008300607
Figure 2008300607

試料１はＡｇ１００ｗｔ％であり、試料２はＡｇ９５ｗｔ％とＰｄ５ｗｔ％であり、試料３はＡｇ９０ｗｔ％とＰｄ１０ｗｔ％であり、試料４はＡｇ８５ｗｔ％とＰｄ１５ｗｔ％であり、試料５はＡｇ８０ｗｔ％とＰｄ２０ｗｔ％である。試料１のＡｇ１００ｗｔ％のものは、硫化試験でかなり黒く変色し、Ｐｄの比率が上昇するに従い、変色の程度は薄くなるが、ＡｇにＰｄを２０ｗｔ％配合したものでも、変色が生じている。   Sample 1 is Ag 100 wt%, Sample 2 is Ag 95 wt% and Pd 5 wt%, Sample 3 is Ag 90 wt% and Pd 10 wt%, Sample 4 is Ag 85 wt% and Pd 15 wt%, and Sample 5 is Ag 80 wt% and Pd 20 wt%. is there. Sample 1 of Ag 100 wt% discolored quite black in the sulfidation test, and the degree of discoloration decreased as the Pd ratio increased, but discoloration occurred even when 20 wt% Pd was added to Ag.

これに対して、試料６〜１１は、Ｐｄのｗｔ％を２０％に固定し、試料６はＡｕ５ｗｔ％とＡｇ７５ｗｔ％であり、試料７はＡｕ１０ｗｔ％とＡｇ７０ｗｔ％であり、試料８はＡｕ１５ｗｔ％とＡｇ６５ｗｔ％であり、試料９はＡｕ２０ｗｔ％とＡｇ６０ｗｔ％であり、試料１０はＡｕ２５ｗｔ％とＡｇ５５ｗｔ％であり、試料１１はＡｕ３０ｗｔ％とＡｇ５０ｗｔ％である。Ａｕを５ｗｔ％含む試料６では、同じＰｄ２０ｗｔ％の試料５と比較して、変色が著しく低減した。すなわち、Ａｕを配合することで、変色を抑制できることが判明した。Ａｕを５ｗｔ％よりも少なくした試料は示していないが、Ａｕを配合していれば変色の抑制効果があるため、Ａｕは１ｗｔ％以上含まれていればよい。   In contrast, Samples 6 to 11 have Pd wt% fixed at 20%, Sample 6 is Au 5 wt% and Ag 75 wt%, Sample 7 is Au 10 wt% and Ag 70 wt%, and Sample 8 is Au 15 wt%. Ag 65 wt%, sample 9 is Au 20 wt% and Ag 60 wt%, sample 10 is Au 25 wt% and Ag 55 wt%, and sample 11 is Au 30 wt% and Ag 50 wt%. In the sample 6 containing 5 wt% Au, the discoloration was remarkably reduced as compared with the sample 5 having the same Pd of 20 wt%. That is, it has been found that discoloration can be suppressed by blending Au. A sample in which Au is less than 5 wt% is not shown, but if Au is blended, there is an effect of suppressing discoloration. Therefore, Au should be contained in an amount of 1 wt% or more.

また、Ａｕを２０ｗｔ％以上配合しても、変色に大きな改善が見られないため、主に材料コストの観点から、Ａｕは２０ｗｔ％以下とすることが好ましい。また、上記の硫化試験の結果から、Ｐｄの配合量は１５〜２５ｗｔ％が好ましく、係る観点から、電極ペーストの金属材料が、Ａｇを主成分とし、Ｐｄが１５〜２５ｗｔ％、Ａｕが１〜２０ｗｔ％含まれることが硫化ガスに対する耐性向上の点で好ましい。更に、材料コストの観点等から、十分な変色抑制効果が得られる範囲として、より好ましいＡｕの配合範囲は３〜１０ｗｔ％である。   Moreover, even if Au is added in an amount of 20 wt% or more, no significant improvement is observed in discoloration. Therefore, from the viewpoint of material cost, Au is preferably 20 wt% or less. Further, from the results of the above sulfidation test, the blending amount of Pd is preferably 15 to 25 wt%. From this viewpoint, the metal material of the electrode paste is mainly composed of Ag, Pd is 15 to 25 wt%, Au is 1 to 1 The content of 20 wt% is preferable from the viewpoint of improving the resistance to sulfurized gas. Furthermore, from the viewpoint of material cost and the like, a more preferable Au blending range is 3 to 10 wt% as a range in which a sufficient discoloration suppressing effect is obtained.

次に、図２を参照して、本発明のチップ抵抗器の製造工程について説明する。
まず、（ａ）に示すように、アルミナセラミックス基板１１を準備する。図示の例はチップ抵抗器１個分を示すが、実際には多数個取りのセラミックス基板が用いられる。次に、（ｂ）に示すように、厚膜上面電極２２，２３および厚膜下面電極１４，１５を形成する。厚膜上面電極２２，２３は、有機成分とガラス成分とＡｇを主成分とし、Ｐｄが１５〜２５ｗｔ％、Ａｕが１〜２０ｗｔ％含まれ、残部がＡｇである金属成分からなる電極材料ペーストを準備し、スクリーン印刷により電極パターンを形成し、焼成することで形成する。これに対して、下面電極１４，１５は実装側の電極であり、硫化ガスが存在してもその影響を受けないので、従来どおりＡｕを含まないＡｇ系の電極材料ペーストを準備し、スクリーン印刷により電極パターンを形成し、焼成することで形成する。 Next, the manufacturing process of the chip resistor of the present invention will be described with reference to FIG.
First, as shown in (a), an alumina ceramic substrate 11 is prepared. Although the illustrated example shows one chip resistor, a multi-piece ceramic substrate is actually used. Next, as shown in (b), thick film upper surface electrodes 22 and 23 and thick film lower surface electrodes 14 and 15 are formed. The thick film upper surface electrodes 22 and 23 are electrode material pastes composed of a metal component mainly composed of an organic component, a glass component, and Ag, Pd of 15 to 25 wt%, Au of 1 to 20 wt%, and the balance of Ag. It prepares, forms an electrode pattern by screen printing, and forms by baking. On the other hand, the lower surface electrodes 14 and 15 are mounting-side electrodes and are not affected by the presence of sulfur gas. Therefore, an Ag-based electrode material paste that does not contain Au is prepared and screen printed as usual. It forms by forming an electrode pattern by baking and baking.

次に、（ｃ）に示すように、酸化ルテニウム系ペーストをスクリーン印刷し、焼成することで、厚膜上面電極２２，２３にまたがる厚膜抵抗体１６を形成する。焼成に際して、従来どおりのＡｇ系またはＡｇ−Ｐｄ系電極であると、厚膜抵抗体１６の部分にＡｇ成分が拡散し、抵抗値変化の原因になるが、ＡｕとＰｄを含むＡｇ系電極であるとＡｇの抵抗体への拡散が抑制され、抵抗値変化を抑制できる。   Next, as shown in (c), the thick film resistor 16 that straddles the thick film upper surface electrodes 22 and 23 is formed by screen-printing and baking a ruthenium oxide paste. When firing, the Ag-based or Ag-Pd-based electrode as in the past diffuses the Ag component into the thick film resistor 16 and causes a change in resistance value. However, in the Ag-based electrode containing Au and Pd, If it exists, the spreading | diffusion to the resistor of Ag will be suppressed and resistance value change can be suppressed.

次に、（ｄ）に示すように、抵抗体１６を覆うガラス材料からなる第１保護コート１７ａを形成し、必要に応じて抵抗体１６のレーザトリミングにより抵抗値を調整する。さらに、（ｅ）に示すように、エポキシ樹脂等の樹脂材料からなる第２保護コート１７ｂを形成する。これにより、第１保護コート１７ａと第２保護コート１７ｂとからなる保護膜１７が形成される。   Next, as shown in (d), a first protective coat 17a made of a glass material covering the resistor 16 is formed, and the resistance value is adjusted by laser trimming of the resistor 16 as necessary. Further, as shown in (e), a second protective coat 17b made of a resin material such as an epoxy resin is formed. Thereby, the protective film 17 composed of the first protective coat 17a and the second protective coat 17b is formed.

次に、多数個取り基板を各チップ抵抗器に対応した個片に分割し、（ｆ）に示すように、端面電極１８，１９を上面電極２２，２３と下面電極１４，１５とに接続するように形成する。端面電極１８，１９は、Ｎｉ系薄膜をスパッタリングにより形成したものである。さらに、（ｇ）に示すように、保護膜１７に覆われていない上面電極２２，２３の部分と端面電極１８，１９と下面電極１４，１５とを被覆するメッキ層２０，２１を設ける。これにより、本発明のチップ抵抗器が完成する。   Next, the multi-chip substrate is divided into pieces corresponding to the chip resistors, and the end face electrodes 18 and 19 are connected to the upper face electrodes 22 and 23 and the lower face electrodes 14 and 15 as shown in FIG. To form. The end face electrodes 18 and 19 are formed by sputtering a Ni-based thin film. Furthermore, as shown in (g), plating layers 20 and 21 are provided to cover the portions of the upper surface electrodes 22 and 23 not covered with the protective film 17, the end surface electrodes 18 and 19, and the lower surface electrodes 14 and 15. Thereby, the chip resistor of the present invention is completed.

この本発明のチップ抵抗器の製造工程は、従来はＡｇ系またはＡｇ−Ｐｄ系の電極材料ペーストを用いていたのに対し、Ｐｄが１５〜２５ｗｔ％、Ａｕが１〜２０ｗｔ％含まれ、残部がＡｇである金属成分からなる電極材料ペーストを用いる点が相違するのみで、その他の点では変わるものではない。従って、電極ペーストの組成の変更のみで、工程数を増加させることなく、硫化ガスに対して上面電極に変色すら生じない耐性の高いチップ抵抗器を製造することが可能となる。   In the manufacturing process of the chip resistor of the present invention, an Ag-based or Ag-Pd-based electrode material paste is conventionally used, whereas Pd is contained in an amount of 15 to 25 wt%, Au is contained in an amount of 1 to 20 wt%, and the balance The only difference is that an electrode material paste made of a metal component of which is Ag is used, and the other points are not changed. Therefore, it is possible to manufacture a highly resistant chip resistor that does not even cause discoloration of the upper surface electrode with respect to the sulfurized gas without changing the number of steps only by changing the composition of the electrode paste.

なお、硫化試験のデータは、試料１〜１１のものについてであるが、本発明者等はその他にも多数の試験を行っており、これらの経験から本発明が導き出されたことを付言する次第である。   In addition, although the data of the sulfidation test are those of samples 1 to 11, the present inventors have conducted many other tests, and as soon as it is added that the present invention has been derived from these experiences. It is.

これまで本発明の一実施形態について説明したが、本発明は上述の実施形態に限定されず、その技術的思想の範囲内において種々異なる形態にて実施されてよいことは言うまでもない。   Although one embodiment of the present invention has been described so far, it is needless to say that the present invention is not limited to the above-described embodiment, and may be implemented in various forms within the scope of the technical idea.

本発明の一実施形態のチップ抵抗器の断面図である。It is sectional drawing of the chip resistor of one Embodiment of this invention. 上記チップ抵抗器の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the said chip resistor. 従来のチップ抵抗器の断面図である。It is sectional drawing of the conventional chip resistor.

符号の説明Explanation of symbols

１１ アルミナセラミックス基板
１２，１３，２２，２３ 上面電極
１４，１５ 下面電極
１６ 厚膜抵抗体
１７ 保護膜
１８，１９ 端面電極
２０，２１ メッキ層 11 Alumina ceramic substrate 12, 13, 22, 23 Upper surface electrode 14, 15 Lower surface electrode 16 Thick film resistor 17 Protective film 18, 19 End surface electrode 20, 21 Plating layer

Claims (4)

セラミックス基板の上下面にそれぞれ配置した一対の厚膜上面電極と、一対の厚膜下面電極と、
前記一対の厚膜上面電極間にまたがって配置した厚膜抵抗体と、
前記厚膜抵抗体を覆う保護膜と、
前記セラミックス基板の端面に配置した前記厚膜上面電極と前記厚膜下面電極とを接続する端面電極と、
前記保護膜に覆われていない前記厚膜上面電極の部分と前記端面電極と前記厚膜下面電極とを覆うメッキ層とを備えたチップ抵抗器において、
前記厚膜上面電極に含まれる金属材料が、Ａｇを主成分とし、更にＰｄとＡｕを含むことを特徴とするチップ抵抗器。 A pair of thick film upper surface electrodes respectively disposed on the upper and lower surfaces of the ceramic substrate; a pair of thick film lower surface electrodes;
A thick film resistor disposed between the pair of thick film upper surface electrodes;
A protective film covering the thick film resistor;
An end face electrode connecting the thick film upper surface electrode and the thick film lower face electrode disposed on the end face of the ceramic substrate;
In a chip resistor comprising a portion of the thick film upper surface electrode not covered with the protective film, a plating layer covering the end surface electrode and the thick film lower surface electrode,
The chip resistor, wherein the metal material contained in the thick film upper surface electrode contains Ag as a main component and further contains Pd and Au. 前記保護膜と前記メッキ層の境界部分が、前記厚膜上面電極の上に位置することを特徴とする請求項１記載のチップ抵抗器。   The chip resistor according to claim 1, wherein a boundary portion between the protective film and the plating layer is located on the thick film upper surface electrode. 前記厚膜上面電極に含まれる金属材料が、Ｐｄが１５〜２５ｗｔ％、Ａｕが１〜２０ｗｔ％、残部がＡｇであることを特徴とする請求項１記載のチップ抵抗器。   2. The chip resistor according to claim 1, wherein the metal material contained in the thick film upper surface electrode is 15 to 25 wt% Pd, 1 to 20 wt% Au, and the balance is Ag. 前記厚膜抵抗体と直接接続される前記厚膜上面電極にのみ、金属材料が、Ａｇを主成分とし、さらにＰｄとＡｕを含む電極材料を用いたことを特徴とする請求項１記載のチップ抵抗器。   2. The chip according to claim 1, wherein only the thick film upper surface electrode directly connected to the thick film resistor is made of an electrode material containing Ag as a main component and further containing Pd and Au. Resistor.
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