JP2007027501A - Chip resistor - Google Patents

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JP2007027501A
JP2007027501A JP2005208917A JP2005208917A JP2007027501A JP 2007027501 A JP2007027501 A JP 2007027501A JP 2005208917 A JP2005208917 A JP 2005208917A JP 2005208917 A JP2005208917 A JP 2005208917A JP 2007027501 A JP2007027501 A JP 2007027501A
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layer
electrode layers
layers
resistance
pair
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JP4512004B2 (en
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Kazuhiro Murakami
和広 村上
Etsuo Naiki
悦雄 内記
Tetsuaki Matsumoto
哲明 松本
Masakuni Tateno
昌邦 立野
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Tateyama Kagaku Kogyo Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive chip resistor that can prevent gas intrusion into an internal electrode layer to avoid line disconnection, even if a chip resistor is used in ambient condition including corrosive gas. <P>SOLUTION: This chip resistor contains a pair of electrode layers formed at both ends of a square insulating substrate 1, an array of resistance layers 4 formed to flow current between the above pair of electrode layers, and a set of protection layers 6 polymerizing on all of the corresponding resistance layers 4 and the internal margins on the above pair of electrode layers. This chip resistor is a thick film chip resistor where each of the above electrode layers comprises two electrode layers. The connection electrode layers 2, 2 polymerize on the margin of the above resistance layer 4 formed just below the margin of the above protection layer 6 and consist of golden materials. The internal electrode layers 3, 3 polymerize not only on the above connection layers 2, 2 just below the margin of the above protection layer 6, but also on the margin of the above resistance layer 4 and consist of silver materials with the respective internal margins extending in pair between the internal margins of both connection electrode layers 2, 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、腐食雰囲気に対する耐性の高いチップ抵抗器に関する。   The present invention relates to a chip resistor having high resistance to a corrosive atmosphere.

チップ抵抗器は、電極層、抵抗層、及び保護層と、実装時における半田付きを高めるメッキ層を構成要素としているが、今日では、耐食性に配慮した積層構造を備えた多くのチップ抵抗器が紹介されている（例えば、下記特許文献参照。）。
特開平１１−２０４３０１号公報 Chip resistors consist of an electrode layer, a resistance layer, a protective layer, and a plating layer that enhances soldering during mounting. Today, many chip resistors with a laminated structure that takes corrosion resistance into account are available. (For example, refer to the following patent document.)
JP-A-11-204301

チップ抵抗器は、種々の材料を適正な温度で焼成し、或いはメッキした複数の層が重なり合って形成されている。一般的に、メッキ層は、導体たる電極層に形成されるが、保護膜は一般的にガラス等の絶縁体であるためにメッキ層が付着・密着しない。その様な材料並びに生成法の相異に起因して、更に、実装時や使用時の熱ストレスが与えられると、メッキ層と焼成層（保護層）との界面に隙間が生じ、拡大することとなる。当該隙間から侵入する硫化ガス等が銀系の材料からなる内部電極層に触れると、当該電極層が腐食して断線に至るという問題がある。   The chip resistor is formed by baking a variety of materials at an appropriate temperature or overlapping a plurality of plated layers. In general, the plating layer is formed on the electrode layer serving as a conductor. However, since the protective film is generally an insulator such as glass, the plating layer does not adhere and adhere to each other. Due to the difference in such materials and production methods, if thermal stress is applied during mounting or use, a gap will be created at the interface between the plating layer and the fired layer (protective layer), which will expand. It becomes. When sulfur gas or the like entering from the gap touches the internal electrode layer made of a silver-based material, there is a problem that the electrode layer corrodes and breaks.

そこで、銀にＰｄ（パラジウム）を混入すると耐硫化性は高まるものの、Ｐｄを入れすぎると比抵抗が高くなり、低い抵抗値を製造する際に不利となる。また、電極層に耐食性に優れる金系の材料を使用すると、断線を防ぐ事は出来るものの材料が高くつきコスト高となる。また、金系材料のみにより電極を構成すると銀系材料を電極に用いる場合と比較して材料コストが高くなり、その際、導通に必要不可欠な範囲で最小の電極を採用しようとすれば、抵抗器として必要な電極の半田付け性や電極強度が得られなくなるという問題がある。   Therefore, when Pd (palladium) is mixed into silver, the resistance to sulfidation increases, but when Pd is added too much, the specific resistance increases, which is disadvantageous when a low resistance value is produced. In addition, when a gold-based material having excellent corrosion resistance is used for the electrode layer, although disconnection can be prevented, the material is expensive and expensive. In addition, if an electrode is composed only of a gold-based material, the material cost is higher than when a silver-based material is used for the electrode. There is a problem that it is impossible to obtain the electrode solderability and electrode strength necessary as a container.

しかも、従来から電極層の材料として銀系の材料が用いられてきたから、今日提供されている抵抗材料としては、当該電極層を形作る銀素材への拡散を考慮した抵抗材料が主流であり、その様な材料は、抵抗に銀が拡散することで所定の抵抗特性（例えば抵抗温度特性）が得られるものとなっているので、当該主流な抵抗材料に対して前記金系の材料といった特殊な電極材料を用いると、前記拡散を考慮した材料構成が仇となり焼成後の特性制御が困難となる他、金系材料のみにより電極を採用した抵抗器と、銀系材料を用いた抵抗器を合わせて生産する場合には、多くの抵抗材料を使い分ける煩雑な管理が必要となる等、更なるコスト高を招来する。   Moreover, since silver-based materials have been used as the material for the electrode layer, the resistance material that is provided today is mainly a resistance material that considers diffusion into the silver material that forms the electrode layer. Since such a material has a predetermined resistance characteristic (for example, resistance temperature characteristic) obtained by diffusing silver into the resistance, a special electrode such as the gold-based material is used for the mainstream resistance material. If the material is used, the material structure considering the diffusion becomes dull and it becomes difficult to control the characteristics after firing. In addition, a resistor using an electrode only with a gold-based material and a resistor using a silver-based material are combined. In the case of production, it is necessary to carry out complicated management for properly using many resistance materials.

一方、電極層を保護するＮｉ系材料等のバリヤ電極層を設ける構成も実用化されているが、樹脂材料（約２００℃で硬化）を含み耐食性に優れた当該バリヤ電極層は、２００℃を超える温度の半田を用いて実装することによって当該電極層が劣化するという問題がある。   On the other hand, a configuration in which a barrier electrode layer such as a Ni-based material for protecting the electrode layer is put into practical use. However, the barrier electrode layer including a resin material (cured at about 200 ° C.) and excellent in corrosion resistance has a temperature of 200 ° C. There exists a problem that the said electrode layer deteriorates by mounting using the solder of the temperature exceeding it.

本発明は、上記実情に鑑みて為されたものであって、腐食性ガスを含む雰囲気中で使用しても内部電極層の腐食を防ぎ、断線を起こすことのない安価なチップ抵抗器の提供を目的とする。   The present invention has been made in view of the above circumstances, and provides an inexpensive chip resistor that prevents corrosion of the internal electrode layer and does not cause disconnection even when used in an atmosphere containing corrosive gas. With the goal.

上記課題を解決するために成された本発明による厚膜型チップ抵抗器は、方形状を呈する絶縁基板上の両端部に形成された対を成す電極層と、前記対を成す電極層の間に各々と導通する様に形成された一連の抵抗層と、当該抵抗層の全体及び前記両電極層上の内側端部に重合された一連の保護層とを備え、前記電極層の各々は、前記保護層の端縁の真下に形成され前記抵抗層の端部と重合する金系の材料からなる接続電極層と、前記保護層の端縁の真下において前記接続電極層と重合する（どちらが上に位置しても良い。）と共に、前記抵抗層の端部と重合し（抵抗層の端部と重合する位置は、前記保護層の端縁の真下でなくとも良い）、且つ両接続電極層の間に各々の内側端部が延出した対を成す銀系の材料からなる内部電極層とからなることを特徴とする。   In order to solve the above problems, a thick film chip resistor according to the present invention includes a pair of electrode layers formed at both ends on an insulating substrate having a square shape, and the pair of electrode layers. A series of resistance layers formed to be electrically connected to each other, and a series of protective layers polymerized on the entire resistance layers and inner end portions on both electrode layers, each of the electrode layers comprising: A connection electrode layer made of a gold-based material that is formed directly below the edge of the protective layer and that overlaps with the edge of the resistance layer, and is polymerized with the connection electrode layer immediately below the edge of the protective layer (which is And may be positioned at the end of the resistance layer (the position where it overlaps with the end of the resistance layer may not be directly below the edge of the protective layer), and both connection electrode layers And an internal electrode layer made of a silver-based material with a pair of inner end portions extending between And wherein the door.

当該構成によれば、前記接続電極層と内部電極層の重合部が、製造時（焼成時等）における両材料相互の拡散により形成された金系材料と銀系材料から成る混合層を、製造工程の態様等に応じて構成し、相互の遠隔部においては金又は銀からなる主材の独立性を残し、当該主材独自の抵抗特性を維持することもできる。前記内部電極層に重合される部分は、接続電極層の全部でも良いし、一部でも良いが、抵抗層と直接接する領域の一部は、焼成によって金が混じり合っていない内部電極層であることが望ましい。前記両接続電極層の間に延出する内部電極層の部分は、正に接続電極層の材料が混じり合わない領域が残される可能性の高い部分であって、当該領域の延出長は、求められる抵抗特性に応じ設計時において適当に定められる。   According to the said structure, the superposition | polymerization part of the said connection electrode layer and an internal electrode layer manufactures the mixed layer which consists of a gold-type material and silver-type material formed by the mutual diffusion of both materials at the time of manufacture (at the time of baking, etc.) It is configured according to the mode of the process, etc., and the independence of the main material made of gold or silver is left in the remote part of each other, and the resistance characteristic unique to the main material can be maintained. The part superposed on the internal electrode layer may be the whole or part of the connection electrode layer, but a part of the region in direct contact with the resistance layer is an internal electrode layer in which gold is not mixed by firing. It is desirable. The portion of the internal electrode layer extending between the two connection electrode layers is a portion where there is a high possibility that a region where the material of the connection electrode layer is not mixed exactly is left, and the extension length of the region is It is appropriately determined at the time of design according to the required resistance characteristics.

尚、前記銀系の材料には、Ｐｄを約５重量％から約２０重量％混入することが望ましい。仮にＰｄの混入割合が少ないと、焼成時に金系材料の層と銀系材料の層との間に亀裂が入る虞が高くなり、逆に多すぎると焼成不良の原因となる。上記各種の層は、単層であるか複層であるかを問わない。例えば前記電極層にあっては、導電ペーストの印刷焼成により形成された接続電極層や内部電極層の上に、金、銀、半田メッキ等のメッキ層とを重合した複層とする場合が多い。   The silver-based material preferably contains about 5% to about 20% by weight of Pd. If the mixing ratio of Pd is small, there is a high risk of cracking between the gold-based material layer and the silver-based material layer at the time of firing. It does not matter whether the various layers are single layers or multiple layers. For example, the electrode layer is often a multi-layer obtained by polymerizing a plating layer such as gold, silver, or solder plating on a connection electrode layer or an internal electrode layer formed by printing and baking a conductive paste. .

上記課題を解決するために成された本発明による厚膜型チップ抵抗器の製造方法は、絶縁基板上に、対をなす接続電極層となるガラスフリットを含んだ金系導電ペーストを印刷し、乾燥の後に約８００℃から９００℃で焼成する接続電極層形成工程と、当該接続電極層に重合され両接続電極層の間に延出する対を成す内部電極層となるガラスフリットを含んだ銀系導電ペーストを印刷し乾燥の後に約８００℃から９００℃で焼成する内部電極層形成工程と、前記対を成す接続電極層上であり且つ当該対を成す内部電極層上にあたる内側端部、及び当該対を成す内部電極層の間に抵抗層となるルテニウム系ペーストを印刷し乾燥の後に約８００℃から９００℃で焼成する抵抗層形成工程と、当該抵抗層の全体、及び前記対を成す接続電極層上であり且つ当該対を成す内部電極層上にあたる内側端部に重合される一連の保護層となるガラスペースト又は合成樹脂ペーストを印刷し約６００℃から７００℃（ガラスペースト）、又は約１５０℃から２５０℃（合成樹脂ペースト）で焼成する保護層形成工程を経ることを特徴とする。   In order to solve the above problems, a method of manufacturing a thick film chip resistor according to the present invention prints a gold-based conductive paste containing a glass frit to be a pair of connection electrode layers on an insulating substrate, A connection electrode layer forming step of baking at about 800 ° C. to 900 ° C. after drying, and a silver containing glass frit that forms a pair of internal electrode layers that are polymerized on the connection electrode layer and extend between the connection electrode layers An internal electrode layer forming step of printing a system conductive paste and baking it at about 800 ° C. to 900 ° C. after drying, an inner end portion on the pair of connection electrode layers and on the pair of internal electrode layers, and A resistance layer forming step of printing a ruthenium-based paste serving as a resistance layer between the internal electrode layers forming the pair and baking the paste at about 800 ° C. to 900 ° C., and the entire resistance layer and the connection forming the pair On the electrode layer In addition, a glass paste or a synthetic resin paste that is a series of protective layers to be polymerized is printed on the inner end portion corresponding to the internal electrode layer forming the pair, and about 600 ° C. to 700 ° C. (glass paste), or about 150 ° C. to 250 ° C. A protective layer forming step of baking at 0 ° C. (synthetic resin paste) is performed.

前記接続電極層と内部電極層の製造工程は相前後してもよく、例えば、絶縁基板上に、対をなす内部電極層となるガラスフリットを含んだ銀系導電ペーストを印刷し、乾燥の後に約８００℃から９００℃で焼成する内部電極層形成工程と、両内部電極層の内側を避けて当該内部電極層に重合され対を成す接続電極層となるガラスフリットを含んだ金系導電ペーストを印刷し乾燥の後に約８００℃から９００℃で焼成する接続電極層形成工程と、前記対を成す接続電極層上であり且つ当該対を成す内部電極層上にあたる内側端部、及び当該対を成す接続電極層の間に抵抗層となるルテニウム系ペーストを印刷し乾燥の後に約８００℃から９００℃で焼成する抵抗層形成工程と、当該抵抗層の全体、及び前記対を成す接続電極層上であり且つ当該対を成す内部電極層上にあたる内側端部に重合される一連の保護層となるガラスペースト又は合成樹脂ペーストを印刷し約６００℃から７００℃（ガラスペースト）、又は約１５０℃から２５０℃（合成樹脂ペースト）で焼成する保護層形成工程を経る厚膜型チップ抵抗器の製造方法としても良い。   The manufacturing process of the connection electrode layer and the internal electrode layer may be mixed. For example, a silver-based conductive paste containing a glass frit to be a pair of internal electrode layers is printed on an insulating substrate and dried. An internal electrode layer forming step of baking at about 800 ° C. to 900 ° C., and a gold-based conductive paste containing glass frit that forms a pair of connection electrode layers that are polymerized on the internal electrode layers while avoiding the inside of both internal electrode layers A connection electrode layer forming step of printing and drying and baking at about 800 ° C. to 900 ° C., an inner end portion on the pair of connection electrode layers and on the pair of internal electrode layers, and the pair A resistance layer forming step of printing a ruthenium-based paste serving as a resistance layer between the connection electrode layers and drying and then baking at about 800 ° C. to 900 ° C., the entire resistance layer, and the pair of connection electrode layers Yes and that A glass paste or a synthetic resin paste, which is a series of protective layers that are polymerized on the inner end of the internal electrode layer, is printed at about 600 ° C. to 700 ° C. (glass paste), or about 150 ° C. to 250 ° C. (synthetic resin A method of manufacturing a thick film chip resistor that undergoes a protective layer forming step of baking with a paste) may be used.

また、上記製造方法においては、出来る限り高温下での焼成過程の回数を減らすことが各層の性状維持、並びに良好な接合状態の維持を図る上で望ましいので、製造の過程において、内部電極層と接続電極層、又はそれらと抵抗パターンとを一括焼成する手法を採ってもよい。   Further, in the above manufacturing method, it is desirable to reduce the number of firing processes at a high temperature as much as possible in order to maintain the properties of each layer and maintain a good bonding state. You may take the method of baking a connection electrode layer or them, and a resistance pattern collectively.

例えば、絶縁基板上に、対をなす接続電極層となるガラスフリットを含んだ金系導電ペーストを印刷し、乾燥の後に約５００℃から７００℃で仮焼成する接続電極層形成工程と、当該接続電極層に重合され両接続電極層の間に延出する対を成す内部電極層となるガラスフリットを含んだ銀系導電ペーストを印刷し、乾燥の後に約８００℃から９００℃で前記金系導電ペーストと共に一括焼成する内部電極層形成工程と、前記対を成す接続電極層上であり且つ当該対を成す内部電極層上にあたる内側端部、及び当該対を成す内部電極層の間に抵抗層となるルテニウム系ペーストを印刷し、乾燥の後に約８００℃から９００℃で焼成する抵抗層形成工程と、当該抵抗層の全体、及び前記対を成す接続電極層上であり且つ当該対を成す内部電極層上にあたる内側端部に重合される一連の保護層となるガラスペースト又は合成樹脂ペーストを印刷し約６００℃から７００℃（ガラスペースト）、又は約１５０℃から２５０℃（合成樹脂ペースト）で焼成する保護層形成工程を経る厚膜型チップ抵抗器の製造方法を採用することもできる。   For example, a connection electrode layer forming step of printing a gold-based conductive paste containing glass frit to be a pair of connection electrode layers on an insulating substrate, and pre-baking at about 500 ° C. to 700 ° C. after drying, and the connection A silver-based conductive paste containing a glass frit that is polymerized into an electrode layer and forms a pair of internal electrode layers extending between the connection electrode layers is printed, and the gold-based conductive material is dried at about 800 ° C. to 900 ° C. after drying. An internal electrode layer forming step in which the paste is fired together with the paste; an inner end on the connecting electrode layer that forms the pair and on the internal electrode layer that forms the pair; and a resistance layer between the internal electrode layers that form the pair A resistive layer forming step of printing the ruthenium-based paste and drying at about 800 ° C. to 900 ° C. after drying, and the entire resistive layer and the internal electrode on the paired connection electrode layer On the layer Protection by printing a glass paste or synthetic resin paste, which is a series of protective layers polymerized on the inner edge, and firing at about 600 ° C. to 700 ° C. (glass paste), or about 150 ° C. to 250 ° C. (synthetic resin paste) A method of manufacturing a thick film chip resistor that undergoes a layer forming step can also be employed.

或いは、絶縁基板上に、対をなす接続電極層となるガラスフリットを含んだ金系導電ペーストを印刷し、乾燥の後に約５００℃から７００℃で仮焼成する接続電極層形成工程と、当該接続電極層に重合され両接続電極層の間に延出する対を成す内部電極層となるガラスフリットを含んだ銀系導電ペーストを印刷し、乾燥の後に約５００℃から７００℃で仮焼成する内部電極層形成工程と、前記対を成す接続電極層上であり且つ当該対を成す内部電極層上にあたる内側端部、及び当該対を成す内部電極層の間に抵抗層となるルテニウム系ペーストを印刷し、乾燥の後に約８００℃から９００℃で前記金系導電ペースト及び銀系導電ペーストと共に一括焼成する抵抗層形成工程と、当該抵抗層の全体、及び前記対を成す接続電極層上であり且つ当該対を成す内部電極層上にあたる内側端部に重合される一連の保護層となるガラスペースト又は合成樹脂ペーストを印刷し約６００℃から７００℃（ガラスペースト）、又は約１５０℃から２５０℃（合成樹脂ペースト）で焼成する保護層形成工程を経る厚膜型チップ抵抗器の製造方法を採用することもできる。   Alternatively, a connection electrode layer forming step of printing a gold-based conductive paste containing glass frit to be a pair of connection electrode layers on an insulating substrate and pre-baking at about 500 ° C. to 700 ° C. after drying, and the connection A silver-based conductive paste containing a glass frit that is polymerized into an electrode layer and forms a pair of internal electrode layers extending between the two connection electrode layers is printed, and dried and then pre-baked at about 500 ° C. to 700 ° C. Printing the ruthenium-based paste that is the resistance layer between the electrode layer forming step, the inner electrode portion that is on the paired connection electrode layer and on the paired internal electrode layer, and the paired internal electrode layer A resistance layer forming step of baking together with the gold-based conductive paste and the silver-based conductive paste at about 800 ° C. to 900 ° C. after drying, the entire resistance layer, and the paired connection electrode layers; This A glass paste or a synthetic resin paste, which is a series of protective layers that are polymerized on the inner end of the paired internal electrode layers, is printed and printed at about 600 ° C. to 700 ° C. (glass paste), or about 150 ° C. to 250 ° C. A method of manufacturing a thick film chip resistor that undergoes a protective layer forming step of baking with a resin paste) can also be employed.

更に、前記接続電極層と内部電極層の製造工程は相前後してもよく、例えば、絶縁基板上に、対をなす内部電極層となるガラスフリットを含んだ銀系導電ペーストを印刷し、乾燥の後に約５００℃から７００℃で仮焼成する内部電極層形成工程と、両内部電極層の内側を避けて当該内部電極層に重合され対を成す接続電極層となるガラスフリットを含んだ金系導電ペーストを印刷し、乾燥の後に約８００℃から９００℃で前記銀系導電ペーストと共に一括焼成する接続電極層形成工程と、前記対を成す接続電極層上であり且つ当該対を成す内部電極層上にあたる内側端部、及び当該対を成す接続電極層の間に抵抗層となるルテニウム系ペーストを印刷し、乾燥の後に約８００℃から９００℃で焼成する抵抗層形成工程と、当該抵抗層の全体、及び前記対を成す接続電極層上であり且つ当該対を成す内部電極層上にあたる内側端部に重合される一連の保護層となるガラスペースト又は合成樹脂ペーストを印刷し約６００℃から７００℃（ガラスペースト）、又は約１５０℃から２５０℃（合成樹脂ペースト）で焼成する保護層形成工程を経る厚膜型チップ抵抗器の製造方法を採用することもできる。   Furthermore, the manufacturing process of the connection electrode layer and the internal electrode layer may be mixed. For example, a silver-based conductive paste containing a glass frit serving as a pair of internal electrode layers is printed on an insulating substrate and dried. And an internal electrode layer forming step of pre-baking at about 500 ° C. to 700 ° C. and a metal system including a glass frit that forms a pair of connection electrode layers that are polymerized on the internal electrode layers while avoiding the inside of both internal electrode layers A connecting electrode layer forming step of printing the conductive paste and baking it together with the silver-based conductive paste at a temperature of about 800 ° C. to 900 ° C. after drying; and an internal electrode layer on the connecting electrode layer forming the pair and forming the pair A resistance layer forming step of printing a ruthenium-based paste serving as a resistance layer between the upper inner end portion and the pair of connection electrode layers, and baking after drying at about 800 ° C. to 900 ° C .; The entire, A glass paste or a synthetic resin paste, which is a series of protective layers that are polymerized on the inner end portions corresponding to the paired internal electrode layers and on the paired internal electrode layers, is printed at about 600 ° C. to 700 ° C. ( It is also possible to employ a method of manufacturing a thick film chip resistor that undergoes a protective layer forming step of baking at about 150 ° C. to 250 ° C. (synthetic resin paste).

或いは、前記接続電極層と内部電極層の製造工程は相前後してもよく、例えば、絶縁基板上に、対をなす内部電極層となるガラスフリットを含んだ銀系導電ペーストを印刷し、乾燥の後に約５００℃から７００℃で仮焼成する内部電極層形成工程と、両内部電極層の内側を避けて当該内部電極層に重合され対を成す接続電極層となるガラスフリットを含んだ金系導電ペーストを印刷し、乾燥の後に約５００℃から７００℃で仮焼成する接続電極層形成工程と、前記対を成す接続電極層上であり且つ当該対を成す内部電極層上にあたる内側端部、及び当該対を成す接続電極層の間に抵抗層となるルテニウム系ペーストを印刷し、乾燥の後に約８００℃から９００℃で前記銀系導電ペースト及び金系導電ペーストと共に一括焼成する抵抗層形成工程と、当該抵抗層の全体、及び前記対を成す接続電極層上であり且つ当該対を成す内部電極層上にあたる内側端部に重合される一連の保護層となるガラスペースト又は合成樹脂ペーストを印刷し約６００℃から７００℃（ガラスペースト）、又は約１５０℃から２５０℃（合成樹脂ペースト）で焼成する保護層形成工程を経る厚膜型チップ抵抗器の製造方法を採用することもできる。   Alternatively, the manufacturing process of the connection electrode layer and the internal electrode layer may be mixed, for example, by printing a silver-based conductive paste containing a glass frit to be a pair of internal electrode layers on an insulating substrate and drying. And an internal electrode layer forming step of pre-baking at about 500 ° C. to 700 ° C. and a metal system including a glass frit that forms a pair of connection electrode layers that are polymerized on the internal electrode layers while avoiding the inside of both internal electrode layers A connection electrode layer forming step of printing a conductive paste and pre-baking after drying at about 500 ° C. to 700 ° C., and an inner end portion on the pair of connection electrode layers and on the pair of internal electrode layers; And a ruthenium paste that serves as a resistance layer between the paired connection electrode layers, and after drying, at a temperature of about 800 ° C. to 900 ° C. together with the silver-based conductive paste and the gold-based conductive paste are collectively fired. And a glass paste or a synthetic resin paste that is a series of protective layers that are polymerized at the inner end portion of the entire resistance layer and the pair of connection electrode layers and the pair of internal electrode layers. It is also possible to employ a method for manufacturing a thick film chip resistor that undergoes a protective layer forming step of baking at about 600 ° C. to 700 ° C. (glass paste) or about 150 ° C. to 250 ° C. (synthetic resin paste).

本発明による厚膜型チップ抵抗器の構造によれば、方形状を呈する絶縁基板上の両端部に形成された対を成す電極層と、前記対を成す電極層の間に各々と導通する様に形成された一連の抵抗層と、当該抵抗層の全体及び前記両電極層上の内側端部に重合された一連の保護層とを備え、前記電極層の各々は、前記保護層の端縁の真下に形成され前記抵抗層の端部と重合する金系の材料からなる接続電極層と、前記保護層の端縁の真下において前記接続電極層と重合すると共に、前記抵抗層の端部と重合し、且つ両接続電極層の間に各々の内側端部が延出した対を成す銀系の材料からなる内部電極層とからなる構造によって、断線を起こすことのない安価なチップ抵抗器の提供できるのみならず、前記金系の材料といった特殊な電極材料を用いたとしても、銀系材料を用いた場合と同様に、焼成後の特性制御が容易となり、多くの抵抗材料を使い分ける煩雑な管理も不要となりコスト高となることも回避できる。また、金系の材料からなる接続電極層と銀系の材料からなる内部電極層とを併存させた構造、又は銀と金が混在している混合層を備えた構造によって、その電極は、高い耐硫化性を示すにも関らず比抵抗を小さくすることができる。   According to the structure of the thick film type chip resistor according to the present invention, a pair of electrode layers formed on both ends of the rectangular insulating substrate and a pair of electrode layers are electrically connected to each other. And a series of protective layers polymerized on the entire resistance layer and inner end portions on the two electrode layers, each of the electrode layers having an edge of the protective layer A connection electrode layer made of a gold-based material that is formed immediately below the edge of the resistance layer and is polymerized with the connection electrode layer directly below the edge of the protective layer, and an edge of the resistance layer An inexpensive chip resistor that does not cause disconnection due to a structure composed of a pair of internal electrode layers made of a silver-based material that is polymerized and that has a pair of inner end portions extending between the connection electrode layers. Not only can it be provided, but a special electrode material such as the above gold-based material was used. Even if, as in the case of using a silver-based material, it is easy to characteristic control after firing, it can be avoided that the cost becomes unnecessary even complicated management selectively using the many resistance material. In addition, the electrode is high due to a structure in which a connection electrode layer made of a gold-based material and an internal electrode layer made of a silver-based material coexist, or a structure having a mixed layer in which silver and gold are mixed. The specific resistance can be reduced in spite of sulfidation resistance.

しかも、前記銀系導電ペースト（殊に、Ｐｄを約５重量％から約２０重量％を混ぜたもの。）、金系導電ペースト、及びルテニウム系ペーストを一括焼成する抵抗パターン焼成工程を経ることによって、各ペーストを逐一焼成した場合に、銀系導電ペーストに含まれる銀が金系導電ペーストに吸収されることによって界面に生じる亀裂を防止することができる。   In addition, the silver-based conductive paste (particularly, Pd mixed with about 5 wt% to about 20 wt%), the gold-based conductive paste, and the ruthenium-based paste are subjected to a resistance pattern baking step. When each paste is baked one by one, it is possible to prevent cracks generated at the interface due to absorption of silver contained in the silver-based conductive paste into the gold-based conductive paste.

前記接続電極層と内部電極層の重合部が、焼成時における両材料相互の拡散により形成された金系材料と銀系材料から成る混合層を構成することによって、当該領域の耐食性が高まるのみならず、前記内部電極層が延出した部分の存在によって、抵抗ペーストへの銀系ペーストの拡散を考慮した抵抗特性の制御も可能となる。   If the superposed portion of the connection electrode layer and the internal electrode layer constitutes a mixed layer composed of a gold-based material and a silver-based material formed by diffusion between the two materials at the time of firing, the corrosion resistance of the region is only increased. In addition, the presence of the portion where the internal electrode layer extends makes it possible to control the resistance characteristics in consideration of the diffusion of the silver-based paste into the resistance paste.

以下、本発明による厚膜型チップ抵抗器（以下、チップ抵抗器と記す。）の実施の形態を、その製造方法と共に図面に基づき説明する。
図１に示すチップ抵抗器は、絶縁基板１と、当該絶縁基板１上に形成される、一対の接続電極層２，２及び内部電極層３，３、一連の抵抗層４、アンダーコート層７、保護層６、端面電極層８、及びメッキ層９で構成される。 Embodiments of a thick film type chip resistor (hereinafter referred to as a chip resistor) according to the present invention will be described below together with a manufacturing method thereof with reference to the drawings.
The chip resistor shown in FIG. 1 includes an insulating substrate 1, a pair of connection electrode layers 2 and 2 and internal electrode layers 3 and 3, a series of resistance layers 4 and an undercoat layer 7 formed on the insulating substrate 1. , Protective layer 6, end face electrode layer 8, and plating layer 9.

当該例におけるチップ抵抗器は、アルミナ製の絶縁基板１上に、予めＶ字状の分割溝を碁盤目状に刻設することによって等面積等形状に区画された単位領域を複数形成し、各単位領域に一つの抵抗器本体１０を、金系或いは銀系の導電ペーストや抵抗ペースト、或いはガラス等の絶縁ペーストを印刷し焼成することによって形成し、分割工程を適宜経ながら複数のチップ抵抗器を一括製造する方法で製造される（図３参照）。   The chip resistor in this example forms a plurality of unit areas equally divided into equal areas by previously engraving V-shaped dividing grooves in a grid pattern on an insulating substrate 1 made of alumina. A single resistor body 10 is formed in a unit region by printing and baking a gold-based or silver-based conductive paste or resistor paste, or an insulating paste such as glass, and a plurality of chip resistors through appropriate division processes. Is manufactured by a batch manufacturing method (see FIG. 3).

先ず、絶縁基板１の表面の両端部にガラスフリットを含む金系の導電ペーストを印刷し（絶縁基板１の端縁に至る状態で設けても良い（図１（Ａ）参照）し、金の使用量を節約する意味等も含めて当該端縁を避けて設けても良い（図１（Ｂ）参照）。）約１５０℃で乾燥処理を行う（電極層印刷／乾燥工程）。当該導電ペーストの乾燥処理を経た後に約８５０℃で前記絶縁基板１の表面に印刷した導電ペーストの焼成を行う（接続電極層焼成工程）ことによって抵抗器本体１０の対を成す接続電極層２，２が形成される。当該接続電極層２は、続いて形成される内部電極層３の腐食による断線によって抵抗層４−電極層間の導通を確保する為に形成されるものであるから、その目的に応じた導通が確保できる形状であるならば、図１（Ｃ）の方形状、又は図２（Ｃ）及び図２（Ｄ）のＴ字状の様に適宜設計変更が可能である。   First, a gold-based conductive paste containing glass frit is printed on both ends of the surface of the insulating substrate 1 (may be provided so as to reach the edge of the insulating substrate 1 (see FIG. 1A)). The edge may be provided so as to avoid the use amount and the like (see FIG. 1B).) Drying is performed at about 150 ° C. (electrode layer printing / drying step). After the conductive paste is dried, the conductive paste printed on the surface of the insulating substrate 1 is baked at about 850 ° C. (connection electrode layer baking step) to form the connection electrode layer 2, which forms a pair of the resistor main body 10. 2 is formed. Since the connection electrode layer 2 is formed in order to ensure conduction between the resistance layer 4 and the electrode layer by disconnection due to corrosion of the internal electrode layer 3 to be subsequently formed, conduction according to the purpose is ensured. If it is a shape that can be made, the design can be changed as appropriate, such as the square shape of FIG. 1C or the T shape of FIGS. 2C and 2D.

次に、当該接続電極層２，２の中央部を含む全域に重合され両接続電極層２，２の間の前記絶縁基板１上に延出する（当該部分を延出部１１と記す。）対を成す内部電極層３，３となる銀系導電ペーストを印刷し約１５０℃で乾燥処理を行う（電極層印刷／乾燥工程）。当該乾燥の後に、約８５０℃で焼成を行う（内部電極層形成工程）ことによって抵抗器本体１０の対を成す内部電極層３，３が形成される。前記銀系導電ペーストとしては、ガラスフリットを含んだ銀系導電ペースト、又はガラスフリットとパラジウム（約５重量％から約２０重量％）を含む銀系導電ペーストが挙げられる。   Next, it is polymerized over the entire region including the central portion of the connection electrode layers 2 and 2 and extends onto the insulating substrate 1 between the connection electrode layers 2 and 2 (this portion is referred to as an extension portion 11). A silver-based conductive paste to be a pair of internal electrode layers 3 and 3 is printed and dried at about 150 ° C. (electrode layer printing / drying step). After the drying, by firing at about 850 ° C. (internal electrode layer forming step), the internal electrode layers 3 and 3 forming a pair of the resistor body 10 are formed. Examples of the silver-based conductive paste include a silver-based conductive paste containing glass frit, or a silver-based conductive paste containing glass frit and palladium (about 5 wt% to about 20 wt%).

次に、当該対を成す内部電極層３，３上の内側端部、及び当該対を成す内部電極層３，３の間の絶縁基板１上に、抵抗ペースト（Ｒｕ系ペースト）を均一幅の一連の帯状に印刷し（抵抗層印刷工程）、約１５０℃下で乾燥処理の後、約８５０℃等で焼成（抵抗層乾燥／焼成工程）することによって、抵抗器本体１０の抵抗層４が形成される（抵抗層形成工程）。   Next, a resistance paste (Ru-based paste) is applied to the inner end portions of the paired internal electrode layers 3 and 3 and the insulating substrate 1 between the paired internal electrode layers 3 and 3 with a uniform width. The resistor layer 4 of the resistor body 10 is printed in a series of strips (resistance layer printing step), dried at about 150 ° C., and then fired at about 850 ° C. (resistance layer drying / firing step). It is formed (resistance layer forming step).

これら、接続電極層焼成工程及び内部電極層形成工程、並びに抵抗層印刷工程は、各々の電極層を印刷した後に約１５０℃で乾燥させ、更に約６００℃（約５００℃から７００℃）で仮焼成を行い、上記抵抗層形成工程の焼成工程において、約８５０℃（約８００℃から９００℃）下、当該抵抗層４と共に一括して焼成する場合もある。尚、上記接続電極形成工程と内部電極形成工程とは、行う順序を入れ替えても良い。   In these connection electrode layer firing step, internal electrode layer forming step, and resistance layer printing step, each electrode layer is printed and then dried at about 150 ° C., and further at about 600 ° C. (about 500 ° C. to 700 ° C.). In some cases, firing is performed together with the resistance layer 4 at about 850 ° C. (about 800 ° C. to 900 ° C.) in the firing step of the resistance layer forming step. Note that the order in which the connection electrode forming step and the internal electrode forming step are performed may be interchanged.

これらの製造態様によれば、焼成時における両材料相互の拡散により、前記接続電極層と内部電極層の重合部において、金系材料と銀系材料から成る耐食性の良い混合層５が構成され（図２参照）、相互の遠隔部や前記延出部１１においては金又は銀からなる主材の独立性を残し、各導電ペーストの主材、特に銀系ペースト独自の抵抗特性を維持し、特性制御の便宜を図ることができる。   According to these production modes, the mixed layer 5 made of a gold-based material and a silver-based material is formed in the polymerized portion of the connection electrode layer and the internal electrode layer by diffusion between the two materials during firing ( 2), the remote part of each other and the extension part 11 leave the independence of the main material made of gold or silver, maintain the resistance characteristic unique to the main material of each conductive paste, in particular the silver paste, Control convenience can be achieved.

更に、前記抵抗層４上の露出部全体を覆う様にガラスペーストを印刷し（アンダーコート層印刷工程）、約１５０℃下での乾燥処理を経て約６００℃で焼成しアンダーコート層７を形成する（アンダーコート層乾燥／焼成工程）。当該工程は、続くレーザートリミングにおける抵抗調整の便宜と共に当該抵抗器本体１０の特性の安定化を図る為に行われるものである。よって、場合によっては、図３の工程図の如く当該アンダーコート層７の形成を行わない場合もある。   Further, a glass paste is printed so as to cover the entire exposed portion on the resistance layer 4 (undercoat layer printing step), and is dried at about 150 ° C. and baked at about 600 ° C. to form an undercoat layer 7. (Undercoat layer drying / firing step). This step is performed in order to stabilize the characteristics of the resistor body 10 together with the convenience of resistance adjustment in the subsequent laser trimming. Therefore, in some cases, the undercoat layer 7 is not formed as shown in the process diagram of FIG.

更に、レーザートリミング後、ガラスペーストを、前記抵抗層４を中央にして、当該抵抗層４上に形成された前記アンダーコート層７の全面を覆い、且つ前記両内部電極層３，３上の内側端部を覆う一連の帯状に印刷（保護層印刷工程）し、約１５０℃等の所定温度で乾燥処理を行う（保護層乾燥工程）。上記保護層６の印刷の際、それらの端縁の真下には、接続電極層２及び内部電極層３、又は混合層５が存在するものとし、対を成す各々の長さは、少なくとも、前記保護層６の端縁の真下を含み、且つ当該真下の前後に前記抵抗層４の膜厚の１０倍以上長さを確保することが望ましい。   Further, after laser trimming, the glass paste covers the entire surface of the undercoat layer 7 formed on the resistance layer 4 with the resistance layer 4 in the center, and the inner side on the internal electrode layers 3 and 3. A series of strips covering the end portions are printed (protective layer printing step), and a drying process is performed at a predetermined temperature such as about 150 ° C. (protective layer drying step). When the protective layer 6 is printed, it is assumed that the connection electrode layer 2 and the internal electrode layer 3 or the mixed layer 5 exist immediately below the edges, and the length of each pair is at least as described above. It is desirable to ensure a length of 10 times or more of the film thickness of the resistance layer 4 before and after the edge of the protective layer 6 and immediately under the edge.

続いて、各々抵抗器本体１０を搭載した絶縁基板１における単位領域の電極側端面が露出する様に短冊状に分割する（一次分割工程）。   Then, it divides | segments in strip shape so that the electrode side end surface of the unit area | region in the insulated substrate 1 in which each resistor main body 10 is mounted may be exposed (primary division | segmentation process).

次に、分割された絶縁基板１に搭載された抵抗器本体１０の電極部（例えば、前記内部電極層の端部表面、内部電極層及び接続電極層の端面、並びに前記絶縁基板の裏面両端部。）を絶縁基板１の端面を経て表裏に亘って一連に覆う状態で導電ペースト（例えば、銀系導電ペースト）を印刷（端面電極層印刷工程）し、当該導電ペーストの乾燥処理（端面電極層乾燥工程）を経た後に、先に乾燥処理を経たガラスペースト（保護層）及び当該導電ペースト（端面電極層８）に対して約６００℃の焼成処理を行う（保護層・端面電極層焼成工程）。これによって前記アンダーコート層７と当該保護層６とから成る複層の保護層が形成すると共に（場合によっては単層でも良い）、端面電極層８を形成し（図３（Ｇ）参照）、その後、絶縁基板１に設けられた前記単位領域を個々に分割する（二次分割工程）。   Next, the electrode portions of the resistor main body 10 mounted on the divided insulating substrate 1 (for example, the end surface of the internal electrode layer, the end surfaces of the internal electrode layer and the connection electrode layer, and both end portions of the back surface of the insulating substrate) .) Is printed in a state where the conductive paste (for example, silver-based conductive paste) is continuously covered over the front and back surfaces through the end face of the insulating substrate 1 (end face electrode layer printing step), and the conductive paste is dried (end face electrode layer). After passing through the drying step, the glass paste (protective layer) and the conductive paste (end face electrode layer 8) that have been subjected to the dry treatment are fired at about 600 ° C. (protective layer / end face electrode layer firing step). . Thereby, a multi-layer protective layer composed of the undercoat layer 7 and the protective layer 6 is formed (in some cases, it may be a single layer), and an end face electrode layer 8 is formed (see FIG. 3G), Thereafter, the unit regions provided on the insulating substrate 1 are individually divided (secondary division step).

最後に、前記端面電極層８の露出面全体に対しメッキ層９を形成するメッキ工程（ニッケル、錫、半田メッキ等）を経て図１及び図２に示す様な個々の厚膜型チップ抵抗器が完成する。   Finally, each thick film chip resistor as shown in FIGS. 1 and 2 is subjected to a plating process (nickel, tin, solder plating, etc.) for forming a plating layer 9 on the entire exposed surface of the end face electrode layer 8. Is completed.

本発明による厚膜型チップ抵抗器は、腐食性ガスを含む雰囲気中で使用しても断線を起こすことのない安価なチップ抵抗器の提供のみならず、前記金系の材料といった特殊な電極材料を用いたとしても、重合され焼成される各種ペーストの主材の拡散を考慮した煩雑な素材管理の便宜にも寄与する。   The thick film type chip resistor according to the present invention provides not only an inexpensive chip resistor that does not break even when used in an atmosphere containing a corrosive gas, but also a special electrode material such as the gold-based material. Even if it is used, it also contributes to the convenience of complicated material management in consideration of diffusion of main materials of various pastes that are polymerized and fired.

（Ａ）：本発明による厚膜型チップ抵抗器の一例を示す縦断面図、（Ｂ）：他の一例を示す縦断面図、（Ｃ）：厚膜型チップ抵抗器（Ａ）の平面図である。(A): longitudinal sectional view showing an example of a thick film type chip resistor according to the present invention, (B): longitudinal sectional view showing another example, (C): a plan view of the thick film type chip resistor (A) It is. （Ａ）：本発明による厚膜型チップ抵抗器の一例を示す縦断面図、（Ｂ）：他の一例を示す縦断面図、（Ｃ）：他の一例を示す縦断面図、（Ｄ）：厚膜型チップ抵抗器（Ｃ）の平面図である。(A): longitudinal sectional view showing an example of a thick film type chip resistor according to the present invention, (B): longitudinal sectional view showing another example, (C): longitudinal sectional view showing another example, (D) : It is a top view of a thick film type chip resistor (C). 本発明による厚膜型チップ抵抗器の製造工程の一例を示す説明図である。It is explanatory drawing which shows an example of the manufacturing process of the thick film type chip resistor by this invention.

符号の説明Explanation of symbols

１ 絶縁基板，２ 接続電極層，３ 内部電極層，４ 抵抗層，５ 混合層，
６ 保護層，７ アンダーコート層，８ 端面電極層，９ メッキ層，
１０ 抵抗器本体，１１ 延出部， 1 insulating substrate, 2 connection electrode layer, 3 internal electrode layer, 4 resistance layer, 5 mixed layer,
6 protective layer, 7 undercoat layer, 8 end face electrode layer, 9 plating layer,
10 resistor body, 11 extension,

Claims (3)

方形状を呈する絶縁基板（１）上の両端部に形成された対を成す電極層と、前記対を成す電極層の間に各々と導通する様に形成された一連の抵抗層（４）と、当該抵抗層（４）の全体及び前記両電極層上の内側端部に重合された一連の保護層（６）とを備え、
前記電極層の各々は、
前記保護層（６）の端縁の真下に形成され前記抵抗層（４）の端部と重合する金系の材料からなる接続電極層（２，２）と、
前記保護層（６）の端縁の真下において前記接続電極層（２，２）と重合すると共に、前記抵抗層（４）の端部と重合し、且つ両接続電極層（２，２）の間に各々の内側端部が延出した対を成す銀系の材料からなる内部電極層（３，３）とからなる厚膜型チップ抵抗器。 A pair of electrode layers formed at both ends on an insulating substrate (1) having a square shape, and a series of resistance layers (4) formed to be electrically connected to each other between the pair of electrode layers; A series of protective layers (6) polymerized on the entire resistance layer (4) and inner end portions on both electrode layers,
Each of the electrode layers is
A connection electrode layer (2, 2) made of a gold-based material that is formed directly under the edge of the protective layer (6) and is polymerized with the end of the resistance layer (4);
Polymerizes with the connection electrode layer (2, 2) just below the edge of the protective layer (6), and with the end of the resistance layer (4), and both of the connection electrode layers (2, 2). A thick film chip resistor comprising a pair of internal electrode layers (3, 3) made of a silver-based material with each inner end extending between them. 前記接続電極層（２）と内部電極層（３）の重合部が、焼成時における両材料相互の拡散により形成された金系材料と銀系材料から成る混合層（５）を構成する前記請求項１に記載の厚膜型チップ抵抗器。   The overlapping part of the connection electrode layer (2) and the internal electrode layer (3) constitutes a mixed layer (5) composed of a gold-based material and a silver-based material formed by diffusion between the two materials during firing. Item 2. The thick film type chip resistor according to item 1. 前記銀系の材料に、Ｐｄを約５重量％から約２０重量％混入した前記請求項１又は請求項２のいずれかに記載の厚膜型チップ抵抗器。
3. The thick film type chip resistor according to claim 1, wherein Pd is mixed in the silver-based material in an amount of about 5 wt% to about 20 wt%.
JP2005208917A 2005-07-19 2005-07-19 Chip resistor Expired - Fee Related JP4512004B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008300607A (en) * 2007-05-31 2008-12-11 Koa Corp Chip resistor
JP2013026574A (en) * 2011-07-25 2013-02-04 Yazaki Corp Method for manufacturing conductive segment and conductive segment
JP2013053955A (en) * 2011-09-05 2013-03-21 Yazaki Corp Conductive segment
US9157783B2 (en) 2011-07-25 2015-10-13 Yazaki Corporation Method for producing conductive segment

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Publication number Priority date Publication date Assignee Title
JPH0362901A (en) * 1989-08-01 1991-03-19 Kamaya Denki Kk Chip resistor
JPH04192208A (en) * 1990-11-26 1992-07-10 Tanaka Kikinzoku Internatl Kk Conductive paste
JPH1126203A (en) * 1997-07-03 1999-01-29 Matsushita Electric Ind Co Ltd Resistor and manufacture thereof
JPH11204301A (en) * 1998-01-20 1999-07-30 Matsushita Electric Ind Co Ltd Resistor
JP2001332407A (en) * 2000-05-19 2001-11-30 Rohm Co Ltd Chip type electronic parts and method of manufacturing chip resistor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0362901A (en) * 1989-08-01 1991-03-19 Kamaya Denki Kk Chip resistor
JPH04192208A (en) * 1990-11-26 1992-07-10 Tanaka Kikinzoku Internatl Kk Conductive paste
JPH1126203A (en) * 1997-07-03 1999-01-29 Matsushita Electric Ind Co Ltd Resistor and manufacture thereof
JPH11204301A (en) * 1998-01-20 1999-07-30 Matsushita Electric Ind Co Ltd Resistor
JP2001332407A (en) * 2000-05-19 2001-11-30 Rohm Co Ltd Chip type electronic parts and method of manufacturing chip resistor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008300607A (en) * 2007-05-31 2008-12-11 Koa Corp Chip resistor
JP2013026574A (en) * 2011-07-25 2013-02-04 Yazaki Corp Method for manufacturing conductive segment and conductive segment
US9157783B2 (en) 2011-07-25 2015-10-13 Yazaki Corporation Method for producing conductive segment
JP2013053955A (en) * 2011-09-05 2013-03-21 Yazaki Corp Conductive segment

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