JP2008251059A - 不揮発性半導体記憶装置およびそのデータ消去方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 94
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims description 18
- 125000006850 spacer group Chemical group 0.000 claims description 9
- 239000010408 film Substances 0.000 description 28
- 238000004519 manufacturing process Methods 0.000 description 22
- 239000000463 material Substances 0.000 description 21
- 239000010410 layer Substances 0.000 description 18
- 239000011229 interlayer Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 229910044991 metal oxide Inorganic materials 0.000 description 9
- 150000004706 metal oxides Chemical class 0.000 description 9
- 239000013078 crystal Substances 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- -1 CuxO Chemical class 0.000 description 4
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 4
- 239000000470 constituent Substances 0.000 description 4
- 238000013500 data storage Methods 0.000 description 4
- 230000001747 exhibiting effect Effects 0.000 description 4
- 229910052748 manganese Inorganic materials 0.000 description 4
- 239000011572 manganese Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910002367 SrTiO Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910016411 CuxO Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- GNRSAWUEBMWBQH-UHFFFAOYSA-N nickel(II) oxide Inorganic materials [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 description 1
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- 239000000126 substance Substances 0.000 description 1
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Abstract
【解決手段】不揮発性半導体記憶装置は、可変抵抗素子VRと電流経路の一端および他端の間に前記可変抵抗素子が接続されたスイッチング素子TRとをそれぞれ有する複数のメモリセルMCを含み、前記複数のメモリセルの電流経路が直列接続されたメモリセル列と、前記メモリセル列の電流経路の一端に接続された第1選択素子S2と、前記メモリセル列の電流経路の他端に接続された第2選択素子S1とを複数備えたメモリセルアレイと、前記第1選択素子の電流経路の一端に電気的に接続されたビット線BLと、前記第2選択素子の電流経路の一端に電気的に接続されたソース線SLとを具備する。
【選択図】 図1
Description
S.Q.Liu、N.J.Wu、A.Ignatiev等(App,Phy,Lett,76,19(2000))
まず、この発明に係る不揮発性半導体記憶装置の概要について、図1および図2を用いて説明する。
本発明の例では、可変抵抗素子に印加する電圧の向きを変えることができ、メモリセル列単位でデータ消去(リセット)するために、例えば、可変抵抗素子とスイッチング素子とを有するメモリセルの電流経路を直列接続したメモリセル列の電流経路の一端および他端に接続された第1,第2選択素子を含むメモリセルアレイと、前記第1選択素子の電流経路の一端に電気的に接続されたビット線と、前記第2選択素子の電流経路の一端に電気的に接続されたソース線とを具備する不揮発性半導体記憶装置を提案する。
<1.全体構成>
まず、図3を用いて、この発明の第1の実施形態に係る不揮発性半導体記憶装置の全体構成を説明する。図3は、本例に係る不揮発性半導体記憶装置を示すブロック図である。
次に、メモリセルアレイ11を構成するブロックの構成例について、図3を用いて説明する。ここでは、1つのブロックBLOCK1を例に挙げて説明する。
次に、平面構造例、ビット線方向の断面構造例およびその等価回路について、図5乃至図7を用いて説明する。図5は、本例に係る不揮発性半導体記憶装置のメモリセルアレイを示す平面図である。図6は、図5中のIV−IV線に沿った断面図である。図7は、図6の等価回路図である。この説明では、上記図5中のビット線BL mに共通接続されたメモリセルMC1〜MC8,および選択トランジスタS1,S2を例に挙げて説明する。
次に、本例に係る不揮発性半導体記憶装置のデータ書き込み動作について、図8および図9を用いて説明する。この説明では、書き込みを行うメモリセル列として図8に示す書き込みメモリセル列23−mを例に挙げ、書き込みを行わないメモリセル列として、図9に示す非書き込みメモリセル列23−1を例に挙げて説明する。
次に、本例に係る不揮発性半導体記憶装置のデータ消去動作について、図10および図11を用いて説明する。この説明では、消去を行うメモリセル列として図10に示す消去メモリセル列23−mを例に挙げ、消去を行わないメモリセル列として図11に非消去メモリセル列23−1を例に挙げて説明する。
上記のように、本例では、データ書き込み動作およびデータ消去動作において、メモリセル列23−m,23−1のソース線SLに印加する電圧を共通とし、ビット線BL m,BL1に印加する電圧をビット線制御回路12により制御する。このように制御することで、メモリセル列ごとに書き込み動作および消去動作を制御することができる。
次に、本例に係る不揮発性半導体記憶装置の製造方法について、図12および図13を用いて説明する。この説明では、図6に示したビット線方向に沿って切った不揮発性半導体装置を例に挙げて説明する。
超巨大磁気抵抗や高温超伝導を示すペロブスカイト型結晶構造や2重整列ペロブスカイト型結晶構造を有するマンガンを含有する酸化物等の可変抵抗材を形成する。より具体的に、この可変抵抗材は、例えば、Pr(1−x)CaxMnO3、La(1−x)CaxMnO3、Nd(1−x)SrxMnO3(0<x<1)、Sr2FeMoO6、Sr2FeWO6等が考えられる。また、Ni,Ti,Cuなどの金属酸化物や、SrTiO3などの金属酸化物およびそれにNbなどの不純物をドープした物を使用しても良い。
この実施形態に係る不揮発性半導体記憶装置、そのデータ消去方法、およびその製造方法によれば、少なくとも下記(1)乃至(3)の効果が得られる。
次に、第2の実施形態に係る不揮発性半導体記憶装置の構成について、図15および図16を用いて説明する。この実施形態は、メモリセルのその他の構成例に関するものである。図15は、この実施形態に係る不揮発性半導体記憶装置を示す平面図である。図16は、図15中のXVI−XVI線に沿って切った断面図である。この説明において、上記第1の実施形態と重複する部分の詳細な説明を省略する。
図16に示すように、この実施形態に係る不揮発性半導体記憶装置は、可変抵抗素子VR1〜VR8が層間絶縁膜27−1中に埋め込み形成されている点で、上記第1の実施形態と相違している。この可変抵抗素子VR1〜VR8が埋め込まれた溝の深さは、電極29が埋め込まれた溝よりも浅くなるように形成されている。
次に、本例に係る不揮発性半導体記憶装置の製造方法について、図17および図18を用いて説明する。
次に、第3の実施形態に係る不揮発性半導体記憶装置について説明する。この実施形態は、縦型の不揮発性半導体記憶装置の構成例に関するものである。この説明において、上記第1の実施形態と重複する部分の詳細な説明を省略する。
構成例について、図19および図20を用いて説明する。図19は、この実施形態に係る不揮発性半導体記憶装置を示す平面図である。図20は、図19中のXX−XX線に沿って切った断面図である。
上記のように、この実施形態に係る不揮発性半導体記憶装置、そのデータ消去方法、およびその製造方法によれば、少なくとも上記(1)乃至(3)と同様の効果が得られる。
Claims (5)
- 可変抵抗素子と電流経路の一端および他端の間に前記可変抵抗素子が接続されたスイッチング素子とをそれぞれ有する複数のメモリセルを含み、前記複数のメモリセルの電流経路が直列接続されたメモリセル列と、前記メモリセル列の電流経路の一端に接続された第1選択素子と、前記メモリセル列の電流経路の他端に接続された第2選択素子とを複数備えたメモリセルアレイと、
前記第1選択素子の電流経路の一端に電気的に接続されたビット線と、
前記第2選択素子の電流経路の一端に電気的に接続されたソース線とを具備すること
を特徴とする不揮発性半導体記憶装置。 - 前記可変抵抗素子は、印加される電圧の向きによって抵抗値が変化する抵抗素子であること
を特徴とする請求項1に記載の不揮発性半導体記憶装置。 - 前記スイッチング素子は、半導体基板上に設けられたゲート絶縁膜と、ゲート絶縁膜上に設けられたゲート電極と、前記ゲート電極の側壁に設けられたスペーサと、前記ゲート電極を挟むように前記半導体基板中に隔離して設けられたソース/ドレインを備えたMOS型トランジスタであること
を特徴とする請求項1または2に記載の不揮発性半導体記憶装置。 - 前記ビット線に印加する電圧を制御するビット線制御回路と、
前記ソース線に印加する電圧を制御するソース線制御回路とを更に具備すること
を特徴とする請求項1乃至3のいずれか1項に記載の不揮発性半導体記憶装置。 - 可変抵抗素子と電流経路の一端および他端の間に前記可変抵抗素子が接続されたスイッチング素子とをそれぞれ有する複数のメモリセルを含み、前記複数のメモリセルの電流経路が直列接続されたメモリセル列と、前記メモリセル列の電流経路の一端に接続された第1選択素子と、前記メモリセル列の電流経路の他端に接続された第2選択素子とを複数備えたメモリセルアレイと、前記第1選択素子の電流経路の一端に電気的に接続されたビット線と、前記第2選択素子の電流経路の一端に電気的に接続されたソース線とを具備する不揮発性半導体記憶装置であって、
データ消去動作の際には、
前記第1,第2選択素子を選択し、
前記ソース線と前記ビット線との間に印加する電圧の向きを、データ書き込み動作の際の前記ソース線と前記ビット線との間に印加する電圧の向きと逆方向とすること
を特徴とする不揮発性半導体記憶装置のデータ消去方法。
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