JP2008153442A - 半導体装置の製造方法 - Google Patents
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Abstract
【解決手段】レーザ光20の照射に対し膜厚が薄くなるに従い反射率が小さくなる反射率調整膜17を、領域Anおよび領域Apを有する半導体基板1上に形成した後、領域An上の反射率調整膜17をエッチングする。次いで、半導体基板1にレーザ光20を照射し、領域Anのn−型半導体領域11、n+型半導体領域14に対して、アニールを行う。同様にして、反射率調整膜17を半導体基板1上に形成した後、領域Ap上の反射率調整膜17をエッチングする。次いで、半導体基板1にレーザ光20を照射し、領域Apのp−型半導体領域12、p+型半導体領域15に対して、アニールを行う。
【選択図】図7
Description
本実施の形態1における半導体装置の製造工程を図面を参照して説明する。図1〜図8は本発明の一実施の形態である半導体装置、例えばCMISの製造工程中の要部断面図である。
r=Er/E0={r0+r1exp(i2φ)}/{1+r1r0exp(i2φ)}
ここで、φは、薄膜中の通過時の光位相変化であり、φ=2π(n+ik)d/λである。
前記実施の形態1では、ゲート絶縁膜7に酸化シリコン膜を適用した場合について説明したが、本実施の形態2では、ゲート絶縁膜7にhigh−k膜を適用した場合について説明する。ゲート絶縁膜7を形成する製造工程までとは前記実施の形態1と同様であるので、ここではその説明は省略し、それ以降の製造工程について説明する。
前記実施の形態1では、不純物を活性化する工程に本発明におけるアニール処理を適用した場合について説明したが、本発明の実施の形態3では、シリサイド工程に適用する場合について説明する。
前記実施の形態1では、CMISの半導体領域(不純物拡散層)に本発明におけるアニール処理を適用した場合について説明したが、本実施の形態4では、半導体チップの所定の領域に適用する場合について説明する。
前記実施の形態1では、半導体基板としてSi基板の所定の領域に本発明におけるアニール処理を適用した場合について説明したが、本発明の実施の形態5では、SiC基板に適用した場合について説明する。
1C チップ
1W 半導体ウエハ
2 素子分離領域
3 p型ウエル
4 しきい値電圧調整層
5 n型ウエル
6 しきい値電圧調整層
7 ゲート絶縁膜
8、9 ゲート電極
10 保護膜
11 n−型半導体領域
12 p−型半導体領域
13 サイドウォール
14 n+型半導体領域
15 p+型半導体領域
16 表面保護膜
17 反射率調整膜
18 配線層間絶縁膜
19 プラグ
20 レーザ光(入射光)
20a、20b、20c 反射光
21 ニッケル膜
22、23 ニッケルシリサイド膜
Ap、An、A1、A2、A3、A4 領域
Claims (9)
- 以下の工程を含むことを特徴とする半導体装置の製造方法;
(a)光源の光の照射に対し膜厚が薄くなるに従い反射率が小さくなる反射率調整膜を、第1領域および第2領域を有する半導体基板上に形成する工程、
(b)前記第1領域上の前記反射率調整膜をエッチングする工程、
を含み、
(c)前記工程(b)の後、前記半導体基板に前記光を照射することによって、前記第1領域に対してアニールを行う工程。 - 前記光源は3μm以上の長波長レーザであり、
前記反射率調整膜は金属膜であることを特徴とする請求項1記載の半導体装置の製造方法。 - 前記反射率調整膜は前記光の波長における複素屈折率の複素成分が1以上の値を持つ膜であることを特徴とする請求項1記載の半導体装置の製造方法。
- 前記工程(c)によって、MISFETのソース・ドレインとなる半導体領域に注入された不純物を活性化することを特徴とする請求項1記載の半導体装置の製造方法。
- 前記工程(c)によって、バイポーラトランジスタのエミッタ・ベースとなる半導体領域に注入された不純物を活性化することを特徴とする請求項1記載の半導体装置の製造方法。
- 前記工程(a)の前に、前記第2領域にバイポーラトランジスタを形成し、
前記工程(b)の後に、前記第1領域にMISFETを形成することを特徴とする請求項1記載の半導体装置の製造方法。 - 前記工程(a)の前に、前記第2領域にメモリセルを形成し、
前記工程(b)の後に、前記第1領域にMISFETを形成することを特徴とする請求項1記載の半導体装置の製造方法。 - 以下の工程を含むことを特徴とする半導体装置の製造方法;
(a)半導体基板の主面上に、high−k膜を形成する工程、
(b)光源の光の照射に対し膜厚が薄くなるに従い反射率が小さくなる反射率調整膜を、前記high−k膜上に形成する工程、
(c)前記反射率調整膜をパターニングし、前記反射率調整膜からなるMISFETのゲート電極を形成する工程、
(d)前記ゲート電極をマスクとして、不純物をイオン注入することによって前記半導体基板の主面にソース・ドレインとなる半導体領域を形成する工程、
(e)前記工程(d)の後、前記半導体基板に前記光を照射することによって、アニールを行う工程。 - 以下の工程を含むことを特徴とする半導体装置の製造方法;
(a)光源の光の照射に対し膜厚が薄くなるに従い反射率が小さくなる反射率調整膜を、SiC基板上に形成する工程、
(b)不純物をイオン注入することによって前記SiC基板に半導体領域を形成する工程、
(c)前記工程(a)の後、前記半導体基板に前記光を照射することによって、アニールを行う工程。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006339994A JP2008153442A (ja) | 2006-12-18 | 2006-12-18 | 半導体装置の製造方法 |
TW096137126A TW200834739A (en) | 2006-12-18 | 2007-10-03 | Manufacture of semiconductor device |
US11/943,639 US7833866B2 (en) | 2006-12-18 | 2007-11-21 | Manufacture of semiconductor device |
KR1020070119818A KR20080056636A (ko) | 2006-12-18 | 2007-11-22 | 반도체 장치의 제조 방법 |
CN2007101868276A CN101207011B (zh) | 2006-12-18 | 2007-11-22 | 半导体器件的制造方法 |
Applications Claiming Priority (1)
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JP2010135546A (ja) * | 2008-12-04 | 2010-06-17 | Sony Corp | 半導体装置の製造方法および半導体装置 |
WO2010082476A1 (ja) | 2009-01-16 | 2010-07-22 | 昭和電工株式会社 | 半導体素子の製造方法及び半導体素子、並びに半導体装置 |
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JP2012156390A (ja) * | 2011-01-27 | 2012-08-16 | Sumitomo Heavy Ind Ltd | レーザアニール方法及びレーザアニール装置 |
JP2013016707A (ja) * | 2011-07-05 | 2013-01-24 | Hitachi Ltd | 半導体装置の製造方法 |
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Also Published As
Publication number | Publication date |
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US20080145987A1 (en) | 2008-06-19 |
KR20080056636A (ko) | 2008-06-23 |
CN101207011A (zh) | 2008-06-25 |
US7833866B2 (en) | 2010-11-16 |
TW200834739A (en) | 2008-08-16 |
CN101207011B (zh) | 2011-07-13 |
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