JP2008141157A - フラッシュメモリ素子の製造方法 - Google Patents
フラッシュメモリ素子の製造方法 Download PDFInfo
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- JP2008141157A JP2008141157A JP2007148925A JP2007148925A JP2008141157A JP 2008141157 A JP2008141157 A JP 2008141157A JP 2007148925 A JP2007148925 A JP 2007148925A JP 2007148925 A JP2007148925 A JP 2007148925A JP 2008141157 A JP2008141157 A JP 2008141157A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 54
- 230000008569 process Effects 0.000 claims abstract description 44
- 238000002955 isolation Methods 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000003860 storage Methods 0.000 claims abstract description 10
- 238000004140 cleaning Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000008859 change Effects 0.000 abstract description 10
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 238000000926 separation method Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 description 9
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000001351 cycling effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
- H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
- Non-Volatile Memory (AREA)
Abstract
【解決手段】
半導体基板100上の活性領域にトンネル絶縁膜102と電荷格納膜を形成し、その電荷格納膜の間の空間が満たされるように第1,第2の絶縁膜108,114上に第3の絶縁膜116を形成する。その第3の絶縁膜116の高さが低くなるようにエッチングを実施することで、素子分離膜のEFHの変化を抑えるように改善する。その結果、たとえばゲート形成時のエッチング工程でアクティブアタックが発生するのを抑える。
【選択図】 図1H
Description
102 トンネル絶縁膜
104 第1の導電膜
106 バッファ絶縁膜
108 第1の絶縁膜
110 トレンチ
112 側壁絶縁膜
114 第2の絶縁膜
116 第3の絶縁膜
118 第4の絶縁膜
120 第5の絶縁膜
122 素子分離膜
124 誘電体膜
126 第2の導電膜
Claims (17)
- 半導体基板上の活性領域にトンネル絶縁膜および電荷格納膜を形成するとともに、素子分離領域にトレンチを形成する工程と、
前記トレンチの一部が満たされるように第1の絶縁膜を形成する工程と、
前記トレンチが満たされるように前記第1の絶縁膜の上部に第2の絶縁膜を形成する工程と、
前記電荷格納膜の側壁と前記トレンチの一部にのみ残留するように前記第1および第2の絶縁膜を除去する工程と、
前記電荷格納膜の間の空間が満たされるように前記第1および第2の絶縁膜の上部に第3の絶縁膜を形成する工程と、
前記第3の絶縁膜の高さが低くなるように前記第3の絶縁膜をエッチングする工程と、
を含むことを特徴とするフラッシュメモリ素子の製造方法。 - 前記第1の絶縁膜を形成する前にさらに、
前記トレンチの側壁および底面を酸化させるために熱酸化工程を実施する工程を含むことを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。 - 前記熱酸化工程時に30Å〜100Åの厚さの酸化膜を形成することを特徴とする請求項2に記載のフラッシュメモリ素子の製造方法。
- 前記第1の絶縁膜は、高密度プラズマ酸化膜で形成することを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
- 前記第1の絶縁膜は、前記トレンチの側壁部分には30Å〜200Åの厚さで形成し、前記トレンチの下部領域には300Å〜2000Åの厚さで形成することを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
- 前記第2の絶縁膜は、SOG系列の酸化物で形成することを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
- 前記第1の絶縁膜と第2の絶縁膜は、湿式クリーニング工程で除去することを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
- 前記湿式クリーニング工程時にHF系列の溶液で除去することを特徴とする請求項7に記載のフラッシュメモリ素子の製造方法。
- 前記第2の絶縁膜は、前記トンネル絶縁膜の下に200Å〜1000Åの厚さで残留させることを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
- 前記湿式クリーニング工程時にエッチング速度を前記第1の絶縁膜と比較して前記第2の絶縁膜がさらに速くエッチングされるようにすることを特徴とする請求項7に記載のフラッシュメモリ素子の製造方法。
- 前記第3の絶縁膜は、高密度プラズマ酸化膜とSOG系列の酸化物が積層された構造で形成されることを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
- 前記高密度プラズマ酸化膜は、前記トレンチの側壁部分には30Å〜200Åの厚さで形成し、前記トレンチの下部領域には前記第2の絶縁膜の上部から300Å〜2000Åの厚さで形成することを特徴とする請求項11に記載のフラッシュメモリ素子の製造方法。
- 前記第3の絶縁膜の除去工程時にセル領域の前記トレンチ内に満たされた前記第3の絶縁膜のみ除去することを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
- 前記第3の絶縁膜は、湿式クリーニング工程で除去することを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
- 前記湿式クリーニング工程時にエッチング速度を前記高密度プラズマ酸化膜と比較して前記SOG系列の酸化物がさらに速くエッチングされるようにすることを特徴とする請求項11または14に記載のフラッシュメモリ素子の製造方法。
- 前記第3の絶縁膜は、HF系列の溶液で除去することを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
- 前記第3の絶縁膜の除去工程によって素子分離膜のEFHを調節することを特徴とする請求項1に記載のフラッシュメモリ素子の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2006-0121522 | 2006-12-04 | ||
KR1020060121522A KR100790296B1 (ko) | 2006-12-04 | 2006-12-04 | 플래시 메모리 소자의 제조방법 |
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JP2008141157A true JP2008141157A (ja) | 2008-06-19 |
JP5187548B2 JP5187548B2 (ja) | 2013-04-24 |
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JP2007148925A Expired - Fee Related JP5187548B2 (ja) | 2006-12-04 | 2007-06-05 | フラッシュメモリ素子の製造方法 |
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US (1) | US7659159B2 (ja) |
JP (1) | JP5187548B2 (ja) |
KR (1) | KR100790296B1 (ja) |
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US20080132016A1 (en) | 2008-06-05 |
KR100790296B1 (ko) | 2008-01-02 |
US7659159B2 (en) | 2010-02-09 |
JP5187548B2 (ja) | 2013-04-24 |
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