JP2008118152A - Semiconductor device and multilayer semiconductor device - Google Patents
Semiconductor device and multilayer semiconductor device Download PDFInfo
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- JP2008118152A JP2008118152A JP2007307513A JP2007307513A JP2008118152A JP 2008118152 A JP2008118152 A JP 2008118152A JP 2007307513 A JP2007307513 A JP 2007307513A JP 2007307513 A JP2007307513 A JP 2007307513A JP 2008118152 A JP2008118152 A JP 2008118152A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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Abstract
Description
本発明は、半導体装置と、半導体装置を多段に積層した半導体装置に係わり、特に三次元実装可能にすることで集積度を向上に関する。 The present invention relates to a semiconductor device and a semiconductor device in which semiconductor devices are stacked in multiple stages, and particularly relates to improving the degree of integration by enabling three-dimensional mounting.
近年、電子機器の小型化、高機能化は、ＬＳＩの微細化技術によって半導体装置そのものが小型化、高集積化、高機能化が進展し、特にメモリやＡＳＩＣ（Ａｐｐｌｉｃａｔｉｏｎ Ｓｐｅｃｉｆｉｃ Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ）のＬＳＩを積み重ねて実装したスタック型半導体装置が携帯端末等に広く使われている。 In recent years, miniaturization and high functionality of electronic devices have led to the miniaturization of LSIs, and semiconductor devices themselves have been miniaturized, highly integrated, and highly functionalized. In particular, LSIs for memory and ASIC (Application Specific Integrated Circuit) have been developed. Stacked semiconductor devices stacked and mounted are widely used for portable terminals and the like.
上記のような半導体装置を実現するための従来技術としては、例えば、特開２０００−２０８６９号公報の図１に示されるようにＴＡＢテープ、フレキシル基板、リジッド基板に半導体素子を搭載し樹脂封止して厚みを１００μｍ程度まで薄くしたパッケージを複数個積み重ねて実装したスタック型半導体装置用モジュールや、特開平７―１０６５０９号公報の図１に示されるように外部端子が基板の両面に設けられ配線基板の凹部に半導体素子を搭載し、前記基板の両面で交互に外部端子を接続したモジュールや、特開２０００−１８３２８３号公報の図４（ｃ）に示されるように配線基板に第１の半導体素子をフリップチップし、その周囲にスタッドバンプを設け、そのスタッドバンプに第２の半導体素子の配線体を接続して樹脂封止した構造などが挙げられる。 As a conventional technique for realizing the semiconductor device as described above, for example, as shown in FIG. 1 of Japanese Patent Laid-Open No. 2000-20869, a semiconductor element is mounted on a TAB tape, a flexible substrate, or a rigid substrate, and resin sealing is performed. Then, a stack type semiconductor device module in which a plurality of packages whose thickness is reduced to about 100 μm are stacked and mounted, or external terminals are provided on both sides of the substrate as shown in FIG. 1 of Japanese Patent Laid-Open No. 7-106509. A module in which a semiconductor element is mounted in a concave portion of a substrate and external terminals are alternately connected on both surfaces of the substrate, or a first semiconductor on a wiring substrate as shown in FIG. 4C of Japanese Patent Laid-Open No. 2000-183283. Flip-chip the device, provide stud bumps around it, connect the wiring of the second semiconductor device to the stud bumps, and seal with resin Structure and the like.
上述した従来例のうち、特開２０００−２０８６９号公報に開示されるものでは、薄型でスタック型に複数個実装してもモジュールの厚さはそれほど厚くならない。しかし、構造上外部接続端子をチップの面上に設けることができず、チップ周囲に設けられているので平面的に大きな面積を必要とする。例えば、テープキャリアパッケージの例ではチップの面積に対してチップの外側に３〜５ｍｍの領域に外部接続端子が設けられるために占める面積は非常に大きくなるという問題点がある。 Of the conventional examples described above, the one disclosed in Japanese Patent Application Laid-Open No. 2000-20869 is thin, and even if a plurality of stacks are mounted, the thickness of the module does not increase so much. However, the external connection terminals cannot be provided on the surface of the chip because of the structure, and are provided around the chip, so that a large area in plan is required. For example, in the case of the tape carrier package, there is a problem that the area occupied by the external connection terminals in the region of 3 to 5 mm outside the chip is very large with respect to the area of the chip.
特開平７―１０６５０９号公報に開示される構造は、配線基板の凹部にチップを搭載する構造であり、これを複数個スタック構造に積み重ねるために、全体の厚さが厚くなってしまうという問題点がある。また、平面方向の面積が大きくなってしまうという問題点は特開２０００−２０８６９号公報に開示されるものと同様である。 The structure disclosed in Japanese Patent Application Laid-Open No. 7-106509 is a structure in which a chip is mounted in a concave portion of a wiring board, and since a plurality of these are stacked in a stack structure, the overall thickness becomes thick. There is. Further, the problem that the area in the plane direction becomes large is the same as that disclosed in Japanese Patent Laid-Open No. 2000-20869.
特開２０００−１８３２８３号公報に開示される従来例は、配線基板の厚さ分だけ厚くなり、このため、特開２０００−２０８６９号公報および特開平７―１０６５０９号公報に開示されるものと同様に平面方向の面積が小さくならないという問題点がある。 The conventional example disclosed in Japanese Patent Laid-Open No. 2000-183283 is thicker by the thickness of the wiring board, and is therefore the same as that disclosed in Japanese Patent Laid-Open No. 2000-20869 and Japanese Patent Laid-Open No. 7-106509. However, there is a problem that the area in the plane direction is not reduced.
以上のようにスタック構造に実装すると厚くなり、平面方向の実装面積が大きくなる問題点があった。 As described above, when mounted on a stack structure, it becomes thick, and there is a problem that the mounting area in the plane direction becomes large.
本発明は、このような従来技術の課題を解決するものであり、その目的とするところは大幅に小型、薄型、高密度実装することできるようにした半導体装置を提供することにある。 The present invention solves such problems of the prior art, and an object of the present invention is to provide a semiconductor device which can be significantly reduced in size, thickness and high density.
本発明の半導体装置は、第１の配線を備え、第１の面と、該第１の面と反対側の第２の面とを有する配線体と、
前面に電極を有し、前記第１の面に搭載されて前記電極を介して前記第１の配線と電気的に接続するＩＣチップと、
前記第１の面に配設されて前記第１の配線と電気的に接続する導体柱と、
前記ＩＣチップと導体柱との間に充填されて前記第１の面と反対側となる上面を形成するとともに前記導体柱の端面を露出させる絶縁性樹脂と、を備え、
前記絶縁性樹脂の下面を前記配線体により完全に覆うように前記配線体が連続した膜により形成されている。
The semiconductor device of the present invention includes a first wiring and a wiring body having a first surface and a second surface opposite to the first surface;
An IC chip having an electrode on the front surface and mounted on the first surface and electrically connected to the first wiring via the electrode;
A conductor post disposed on the first surface and electrically connected to the first wiring;
An insulating resin that is filled between the IC chip and the conductor column and forms an upper surface opposite to the first surface and exposes an end surface of the conductor column;
The wiring body is formed of a continuous film so that the lower surface of the insulating resin is completely covered by the wiring body.
この場合、前記端面と前記上面が実質的に連続した平坦な面であるとしてもよい。 In this case, the end surface and the upper surface may be a flat surface that is substantially continuous.
さらに、前記配線体の前記第２の面に設けられた第２の配線を有するとしてもよい。 Furthermore, it is good also as having the 2nd wiring provided in the said 2nd surface of the said wiring body.
さらに、前記上面に設けられ、前記端面と電気的に接続する第３の配線を有するとしてもよい。 Furthermore, it is good also as having the 3rd wiring provided in the said upper surface and electrically connected with the said end surface.
さらに、前記端面と前記第２の配線との間に形成された半田ボールを有するとしてもよい。 Furthermore, a solder ball formed between the end face and the second wiring may be provided.
また、前記第２の配線上に形成された半田ボールを有するとしてもよい。 Also, solder balls formed on the second wiring may be provided.
また、前記上面に形成され、前記端面と電気的に接続する第３の配線を有するとしてもよい。 Moreover, it is good also as having the 3rd wiring formed in the said upper surface and electrically connected with the said end surface.
また、前記端面上に形成された半田ボールを有するとしてもよい。 Moreover, it is good also as having the solder ball formed on the said end surface.
また、前記配線体は、前記第２の面の露出部分に配設されたレジスト層を有するとしてもよい。 The wiring body may include a resist layer disposed on the exposed portion of the second surface.
本発明の積層型半導体装置は、半導体装置が複数積層された積層型半導体装置であって、
前記複数の半導体装置のなかの１つの半導体装置の端面は、他の半導体装置の第２の配線と電気的に接続する。
The stacked semiconductor device of the present invention is a stacked semiconductor device in which a plurality of semiconductor devices are stacked,
An end face of one semiconductor device among the plurality of semiconductor devices is electrically connected to a second wiring of another semiconductor device.
本発明は以上説明したように構成されているので、以下に記載するような硬化を奏する。 Since the present invention is configured as described above, it exhibits curing as described below.
半導体素子の両面に極薄の配線体を配置し、半導体素子を挟み込んで両配線体を半導体素子に平行して林立する導体柱で相互に接続しているために、最小面積で厚さが１００μｍ以下の半導体装置が実現できる。 Since ultra-thin wiring bodies are arranged on both sides of the semiconductor element, and the semiconductor elements are sandwiched and both wiring bodies are connected to each other by conductor pillars standing parallel to the semiconductor element, the thickness is 100 μm with a minimum area. The following semiconductor devices can be realized.
第２配線体を用いないものの場合には、面積が若干大きくなるが厚さは６０μｍ以下の半導体装置が実現できる。 In the case where the second wiring body is not used, a semiconductor device having a slightly larger area but a thickness of 60 μm or less can be realized.
単体の半導体装置を多段に積み重ねて接続した積層型半導体装置としたものでは非常に薄い高集積の半導体装置が簡単に得られる。 In a stacked semiconductor device in which single semiconductor devices are stacked and connected in multiple stages, a very thin highly integrated semiconductor device can be easily obtained.
第１配線体を埋め込み配線で形成し、第２配線体をテープキャリア配線体で形成する場合には、工程が簡単となり最小面積の半導体装置が得られる。 In the case where the first wiring body is formed by the embedded wiring and the second wiring body is formed by the tape carrier wiring body, the process becomes simple and a semiconductor device having a minimum area can be obtained.
第１配線体と第２配線体を相互に接続する導体柱の形成時期を、半導体素子を接続する前に形成する場合には、メッキ作業等が途中工程で入らないために製造工程が単純化する。 Simplifying the manufacturing process because plating work and the like are not performed in the middle of the process when forming the conductor pillars connecting the first wiring body and the second wiring body before connecting the semiconductor elements. To do.
第１配線体と第２配線体を共に埋め込み型の配線体で形成する場合には極薄の半導体装置が簡単に製造できる。 When both the first wiring body and the second wiring body are formed of embedded wiring bodies, an extremely thin semiconductor device can be easily manufactured.
個片化されていない半完成品の半導体装置を多層に積み重ねて端子部を接続と接着した状態でまとめて所定領域を切断する場合には積層型半導体装置を効率よく生産することができる。 When semi-finished semiconductor devices that have not been separated into one another are stacked in multiple layers and the terminal portions are connected and bonded together to cut a predetermined region, a stacked semiconductor device can be produced efficiently.
第１，２配線体を多層配線にすることによって端子部が半導体素子の周辺及び半導体素子上に配置することが自由にでき、さらなる半導体装置の小面積化が可能となる。 By using multilayer wiring for the first and second wiring bodies, the terminal portion can be freely arranged around and on the semiconductor element, and the area of the semiconductor device can be further reduced.
以下に本発明の実施形態を図面に基づいて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
図１は、本発明による半導体装置の平面図であり、図２は、図１中のＡ−Ａ′の断面図である。図３は図１に示す半導体装置の製造工程を説明するための図である。 FIG. 1 is a plan view of a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view taken along the line AA 'in FIG. FIG. 3 is a diagram for explaining a manufacturing process of the semiconductor device shown in FIG.
ここで、図１、図２に示す半導体装置について説明する。 Here, the semiconductor device illustrated in FIGS. 1 and 2 will be described.
半導体素子４の電極５には第１配線体３が接続され、第１配線体３には半導体素子４の面内から外部にわたって延在する端子部１５が設けられている。第１配線体３の端子部１５は、半導体素子４の周囲に放射状に複数形成され、その厚さは１５μｍ程度であり、絶縁性の樹脂６により固定されている。 The first wiring body 3 is connected to the electrode 5 of the semiconductor element 4, and the first wiring body 3 is provided with a terminal portion 15 extending from the surface of the semiconductor element 4 to the outside. A plurality of terminal portions 15 of the first wiring body 3 are radially formed around the semiconductor element 4 and have a thickness of about 15 μm and are fixed by an insulating resin 6.
半導体素子４の反第１配線体側となる面には配線体１９が設けられ、配線体１９の端子部１６は、半導体素子４の周囲に樹脂６を貫通する形態で設けられた導体柱１０を介して接続されている。端子部１６以外の部分は接着材、例えばエポキシ系接着剤によって強固に接着されている。 A wiring body 19 is provided on the surface on the side opposite to the first wiring body of the semiconductor element 4, and the terminal portion 16 of the wiring body 19 has a conductor column 10 provided in a form penetrating the resin 6 around the semiconductor element 4. Connected through. Portions other than the terminal portion 16 are firmly bonded with an adhesive, for example, an epoxy adhesive.
次に、図１および図２に示した半導体装置の製造方法について図３を参照して説明する。 Next, a method of manufacturing the semiconductor device shown in FIGS. 1 and 2 will be described with reference to FIG.
図３（ａ）に示される基板１は、第１の配線体としての第１配線体３を形成するための平らな銅基板であり、一枚の基板に形成する第１配線体３の数量は半導体素子の大きさによって取り数は異なる。基板１の大きさはおおよそ縦１００ｍｍ、横３００ｍｍ、板厚は０．２５ｍｍである。この基板１の板厚と大きさは第１配線体３の取り数によって適宜決められる。 The substrate 1 shown in FIG. 3A is a flat copper substrate for forming the first wiring body 3 as the first wiring body, and the number of the first wiring bodies 3 formed on one substrate. The number varies depending on the size of the semiconductor element. The substrate 1 is approximately 100 mm long, 300 mm wide, and 0.25 mm thick. The thickness and size of the substrate 1 are appropriately determined depending on the number of first wiring bodies 3 to be taken.
次に、図３（ａ）に示した基板１に第１配線体３をパターン形成する方法について説明する。 Next, a method for patterning the first wiring body 3 on the substrate 1 shown in FIG.
一つの方法としては、図３（ｂ）に示すように、銅板全面にメッキ（または圧延）によって１０〜１５μｍ程度の厚さに積層したＡｕ／Ｎｉ／Ａｕメッキ２を形成する。その後、感光性レジスト（図示せず）を塗布し、マスク露光した後に現像する。これにより、第１の第１配線体３を形成する部分が被覆され、それ以外が剥離されるようにパターニングする。次に、レジストパターンをマスクにしてＮｉを例えばメルテックス社製、商品名エンストリップ ＮＰ（アルカリ性）やエンストリップ １６５Ｓ（硫酸系）でエッチングしてＮｉの配線体形成後、レジストを溶剤またはプラズマ等で除去する。これにより、第１配線体３が複数個同時に形成される。その後、第１配線体３のパターン上に０．１μｍ程度のＡｕメッキをして接続時の酸化防止とする。 As one method, as shown in FIG. 3B, Au / Ni / Au plating 2 laminated to a thickness of about 10 to 15 μm is formed on the entire surface of the copper plate by plating (or rolling). Then, a photosensitive resist (not shown) is applied, developed after mask exposure. As a result, patterning is performed so that the portion forming the first first wiring body 3 is covered and the other portions are peeled off. Next, using a resist pattern as a mask, Ni is etched with, for example, a product name, Enstrip NP (alkaline) or Enstrip 165S (sulfuric acid), manufactured by Meltex, and a Ni wiring body is formed. Remove with. Thereby, a plurality of first wiring bodies 3 are formed simultaneously. Thereafter, Au plating of about 0.1 μm is applied on the pattern of the first wiring body 3 to prevent oxidation at the time of connection.
また、別の方法としては、配線体パターン形状に感光性レジストを塗布、マスク露光、現像して配線体形成部分のレジストが剥離されるようにパターニングする。その後薄いＡｕメッキの上に、１０〜１５μｍのＮｉをメッキし、さらにその上にＡｕメッキをして接続時の酸化防止とする。その後、レジストは上述と同じ方法で除去する。Ａｕメッキは０．１μｍ程度でよい。 As another method, a photosensitive resist is applied to the wiring body pattern shape, mask exposure and development are performed, and patterning is performed so that the resist on the wiring body forming portion is peeled off. Thereafter, 10 to 15 μm of Ni is plated on the thin Au plating, and further Au plating is applied thereon to prevent oxidation at the time of connection. Thereafter, the resist is removed by the same method as described above. Au plating may be about 0.1 μm.
その後、基板１上のＡｕ／Ｎｉ／Ａｕからなる第１配線体３に、図３（ｃ）に示すように半導体素子４の電極５（図２参照）を位置合わせして加熱圧接によるフリップチップ接続を行う。その後、第１配線体３と半導体素子４との間にアンダーフィル封止剤として低粘度樹脂（例えば住友ベークライト（株）社製、商品名ＣＲＰ−４７１１Ａ等の大チップ低応力性の樹脂）を充填・加熱硬化させた後に一般的なトランスファー成形により樹脂６を半導体素子の周囲を充填して半導体素子と基板を接着して応力に対して耐性を持たせる。 After that, as shown in FIG. 3 (c), the electrode 5 (see FIG. 2) of the semiconductor element 4 is aligned with the first wiring body 3 made of Au / Ni / Au on the substrate 1, and the flip chip is formed by heating and pressing. Connect. Thereafter, a low-viscosity resin (for example, a large chip low-stress resin such as CRP-4711A manufactured by Sumitomo Bakelite Co., Ltd.) is used as an underfill sealant between the first wiring body 3 and the semiconductor element 4. After filling and heat-curing, resin 6 is filled around the semiconductor element by general transfer molding, and the semiconductor element and the substrate are bonded to have resistance against stress.
上記のアンダーフィル樹脂を注入する方法とは別の方法としては、金属基板１と第１配線体３上にシート状または高粘度の樹脂を付着させておき、半導体素子４を第１配線体３の接続部に位置合わせして加熱圧着または加熱溶融させて接続すると同時に接着材も硬化させてアンダーフィル樹脂の代わりにすることも可能である。 As a method different from the method of injecting the underfill resin, a sheet-like or high-viscosity resin is adhered on the metal substrate 1 and the first wiring body 3, and the semiconductor element 4 is attached to the first wiring body 3. It is also possible to replace the underfill resin by aligning with the connecting portion and heating and press-bonding or heat-melting to connect and simultaneously curing the adhesive.
次いで、図３（ｄ）に示すように半導体素子４と充填した樹脂６とを研削機１００により研削する。研削前の半導体素子４の厚さは８００μｍ程度であり、これを樹脂６と一緒に１０μｍ程度の厚さまで薄く削る。ここで用いた研削機１００は、ディスコ社製の一般的な装置を用いて充分に目的の薄さに研削・制御できる。 Next, the semiconductor element 4 and the filled resin 6 are ground by a grinding machine 100 as shown in FIG. The thickness of the semiconductor element 4 before grinding is about 800 μm, and this is thinned to a thickness of about 10 μm together with the resin 6. The grinding machine 100 used here can be sufficiently ground and controlled to a desired thickness using a general apparatus manufactured by DISCO.
その後、半導体素子４の研削面には応力歪みや微細なクラック、欠けが発生するために、５０〜６０℃の３％ＮａＯＨに１〜２分間浸し、表面を１〜２μｍ程度エッチングした。 Thereafter, since stress strain, fine cracks, and chips were generated on the ground surface of the semiconductor element 4, it was immersed in 3% NaOH at 50 to 60 ° C. for 1 to 2 minutes, and the surface was etched by about 1 to 2 μm.
次に、樹脂６にスルーホールを形成する。図３（ｅ）〜図３（ｈ）は、説明しやすいようにスルーホール形成部分を拡大して示している。第１配線体３の周辺近傍にレーザー光８を照射し、第１配線体３上の樹脂６を蒸発させ、第１配線体３上の樹脂６にスルーホール９を形成する。このスルーホール９の径は５０〜１００μｍ程度であり、配線ピッチに応じて適宜選択できる。 Next, a through hole is formed in the resin 6. FIG. 3E to FIG. 3H show the through hole forming portion in an enlarged manner for easy explanation. Laser light 8 is irradiated near the periphery of the first wiring body 3 to evaporate the resin 6 on the first wiring body 3, thereby forming a through hole 9 in the resin 6 on the first wiring body 3. The diameter of the through hole 9 is about 50 to 100 μm, and can be appropriately selected according to the wiring pitch.
続いて、スルーホール９内を銅メッキにより充填する。この方法について図３（ｆ）を参照して説明する。基板１をアノード電極とし、カソード電極を銅板（不図示）に接続し、硫酸銅またはシアン化銅を電解液としてスルーホール９内を銅金属１１で充填させる。メッキ層は樹脂面より若干突出させ、突出部１２を形成する。その後に、錫メッキ浴、半田メッキ浴、または金メッキ浴に移して、突出部１２に錫メッキ、半田メッキまたは金メッキをする方法等が可能である。この様にして柱状の導体からなる端子部１０を形成する。 Subsequently, the through hole 9 is filled with copper plating. This method will be described with reference to FIG. The substrate 1 is used as an anode electrode, the cathode electrode is connected to a copper plate (not shown), and the inside of the through hole 9 is filled with copper metal 11 using copper sulfate or copper cyanide as an electrolytic solution. The plating layer is slightly protruded from the resin surface to form the protruding portion 12. Thereafter, a method of transferring to a tin plating bath, a solder plating bath, or a gold plating bath and performing tin plating, solder plating, or gold plating on the protruding portion 12 is possible. Thus, the terminal part 10 which consists of a columnar conductor is formed.
次に、図３（ｇ）に示すように、研削された半導体素子４の裏面１３とスルーホール９内を銅金属で充填し、表面に金または等がメッキされた突出部１２に、図２における配線体１９に相当するテープ配線基板１４の内部電極を接続する。テープ配線基板１４はベースフィルム上に銅により導体配線パターンが形成されており、該導体配線パターンの表面にニッケル／金のメッキが施されている。接続後、樹脂１０１により接続部を封止し、はんだなどにより端子部１０３を形成する。突出部１２とテープ配線基板の内部電極との接続は、突出部１２が金メッキの場合には加熱圧接、または超音波接合法などで接続し、また、突出部１２が半田メッキの場合は、２５０℃程度の温度で溶融接続をすることが出来る。 Next, as shown in FIG. 3 (g), the back surface 13 and the through hole 9 of the ground semiconductor element 4 are filled with copper metal, and the protrusion 12 having the surface plated with gold or the like is formed on the protrusion 12 shown in FIG. The internal electrode of the tape wiring board 14 corresponding to the wiring body 19 is connected. The tape wiring board 14 has a conductor wiring pattern formed of copper on a base film, and the surface of the conductor wiring pattern is plated with nickel / gold. After the connection, the connection portion is sealed with the resin 101, and the terminal portion 103 is formed with solder or the like. The protrusion 12 and the internal electrode of the tape wiring board are connected by heat pressure welding or ultrasonic bonding when the protrusion 12 is gold-plated, or 250 when the protrusion 12 is solder-plated. Melt connection can be made at a temperature of about ℃.
上記のテープ配線基板１４を配線体１９として用いる方法の他に、感光性樹脂の塗布、露光、現像によるパターン形成方法によるビルドアップ工法を用いる方法もある。この方法については後に詳細に述べる。この場合にも上述した金メッキ、半田メッキの方法は同じである。 In addition to the method of using the tape wiring substrate 14 as the wiring body 19, there is a method of using a build-up method by a pattern forming method by applying a photosensitive resin, exposing and developing. This method will be described in detail later. Also in this case, the gold plating and solder plating methods described above are the same.
その後、この状態で各半導体素子を個別にするダイシング装置で半導体素子間に切り溝を設ける（図示せず）。 Thereafter, in this state, a dicing device that separates each semiconductor element is provided with a kerf between the semiconductor elements (not shown).
その後、図３（ｈ）に示すように、研削面とスルーホール９が形成された面にエッチング時の保護樹脂（図示せず）を塗布し、熱硬化させた後に基板である銅を塩化第二鉄、または、塩化第二銅で銅基板全部をエッチング除去して１０〜５０μｍ程度の厚さとする。 Thereafter, as shown in FIG. 3 (h), a protective resin (not shown) at the time of etching is applied to the ground surface and the surface on which the through-holes 9 are formed, and after heat-curing, the substrate copper is chlorinated. The entire copper substrate is etched away with ferric or cupric chloride to a thickness of about 10 to 50 μm.
この後にダイシング装置で半導体素子間を行方向、列方向に切断後、保護樹脂を溶剤で溶かすと個片化された半導体素子の両面に薄膜を用いた配線体で挟まれた半導体装置ができあがる。 Thereafter, the semiconductor elements are cut in a row direction and a column direction by a dicing apparatus, and then the protective resin is dissolved in a solvent, whereby a semiconductor device is obtained in which both sides of the separated semiconductor elements are sandwiched by wiring bodies using a thin film.
以上の説明では、配線体を形成する基板として金属基板を用いて説明したが、他にもエッチングや機械的な剥離が可能な基板を用いることにより同様な構造の形成が可能である。 In the above description, the metal substrate is used as the substrate on which the wiring body is formed, but a similar structure can be formed by using a substrate that can be etched or mechanically peeled.
次に、導体柱からなる端子部１０の他の製造方法について説明する。 Next, another method for manufacturing the terminal portion 10 made of a conductive pillar will be described.
図３（ｅ）に示した状態において、樹脂にスルーホールを形成し、メッキにより金属粒を充填する代わりに、図３（ｂ）に示す工程で第１配線体３を形成後、端子部１０として２５〜３０μｍ径の金細線をワイヤーボンディングにより所定位置に接続すると、ワイヤーが熱と圧力と超音波のエネルギーで変形して５〜６０μｍ径の太さになるとともに金細線の一部が細り、そこからクランプ操作により切断され、端子部１０と同様のものが形成される。 In the state shown in FIG. 3E, instead of forming a through hole in the resin and filling the metal particles by plating, the first wiring body 3 is formed in the process shown in FIG. When connecting a gold wire with a diameter of 25 to 30 μm to a predetermined position by wire bonding, the wire is deformed by heat, pressure and ultrasonic energy to become a thickness of 5 to 60 μm and a part of the gold wire is thinned. From there, it is cut by a clamping operation, and the same thing as the terminal portion 10 is formed.
また、導体柱の端子部１０の高さを必要に応じて１個または２個積み重ねたスタッドバンプを形成した後に樹脂を充填する方法がある。 Further, there is a method of filling a resin after forming a stud bump in which one or two of the terminal portions 10 of the conductor pillars are stacked as required.
図１０（ａ）〜（ｇ）はスタッドバンプを用いた端子部の形成方法を説明するための図である。 FIGS. 10A to 10G are views for explaining a method of forming a terminal portion using stud bumps.
図１０（ａ）に示すように基板２０１上に第１配線体２０２を形成する。 As shown in FIG. 10A, the first wiring body 202 is formed on the substrate 201.
次に、図１０（ｂ）に示すように半導体素子２０３をその電極が第１配線体２０２と接続するように搭載する。 Next, as shown in FIG. 10B, the semiconductor element 203 is mounted so that the electrode is connected to the first wiring body 202.
続いて、図１０（ｃ）に示すように導体柱としてのスタッドバンプ２０４を積層し、図１０（ｄ）に示すように半導体素子２０３と基板２０１との間をアンダーフィル２０５を充填させる。 Subsequently, stud bumps 204 as conductor pillars are stacked as shown in FIG. 10C, and an underfill 205 is filled between the semiconductor element 203 and the substrate 201 as shown in FIG.
次に、図１０（ｅ）に示すように半導体素子２０３の周囲を樹脂２０６により封止する。 Next, as shown in FIG. 10E, the periphery of the semiconductor element 203 is sealed with a resin 206.
この後、図１０（ｆ）に示すように基板２０１をエッチング除去し、図１０（ｇ）に示すように樹脂２０６を研削除去する。 Thereafter, the substrate 201 is removed by etching as shown in FIG. 10 (f), and the resin 206 is removed by grinding as shown in FIG. 10 (g).
また、導体柱を形成した後に、樹脂封止を行う他の例について図１１を参照して説明する。 Another example in which resin sealing is performed after the conductor pillars are formed will be described with reference to FIG.
図１１において、３０１はＩＣチップ、３０２はＩＣチップ３０１の電極、３０３は、ＩＣチップ３０１の電極３０２が電気的に接続される平面状の配線体であり、この配線体３０３は、基板３０４上に固着して設けられている。 In FIG. 11, 301 is an IC chip, 302 is an electrode of the IC chip 301, and 303 is a planar wiring body to which the electrode 302 of the IC chip 301 is electrically connected. It is fixed and provided.
３０６は、ＩＣチップ３０１が組み付けられた前記配線体３０３の一方の面３０３ａ上で、前記配線体３０３に接続して設けられる導体柱、３０７は、配線体３０３の一方の面３０３ａ上で、ＩＣチップ３０１及び導体柱３０６が設けられていない部分に充填された絶縁樹脂である。 Reference numeral 306 denotes a conductor column provided on the one surface 303a of the wiring body 303 on which the IC chip 301 is assembled and is connected to the wiring body 303. Reference numeral 307 denotes an IC chip on the one surface 303a of the wiring body 303. This is an insulating resin filled in a portion where the chip 301 and the conductor pillar 306 are not provided.
次に、このように構成した半導体装置の製造方法について、説明する。 Next, a method for manufacturing the semiconductor device configured as described above will be described.
まず、図１１（ａ），（ｂ）に示すように、基板３０４上に形成された配線体３０３と、配線体３０３上に設けた導体柱（導体突起）３０６とからなる配線基板３０４の配線体３０３の一方の面３０３ａに、ＩＣチップ３０１をフリプチップ接続し、次に、図１１（ｃ）示すように、基板３０４の一方の面３０３ａ上で、ＩＣチップ３０１及び導体柱３０６を絶縁樹脂３０７で覆い、封止する。 First, as shown in FIGS. 11A and 11B, the wiring of the wiring board 304 including the wiring body 303 formed on the substrate 304 and the conductor pillars (conductor protrusions) 306 provided on the wiring body 303. The IC chip 301 is flip-chip connected to one surface 303a of the body 303. Next, as shown in FIG. 11C, the IC chip 301 and the conductor column 306 are connected to the insulating resin 307 on one surface 303a of the substrate 304. Cover and seal.
次に、図１１（ｄ）に示すように、樹脂３０７を研削し、導体柱３０６の端面３０８を露出させ、また、配線体３０４から基材３０５を除去する。 Next, as shown in FIG. 11D, the resin 307 is ground to expose the end face 308 of the conductor pillar 306, and the base material 305 is removed from the wiring body 304.
上記の方法は、メッキ作業を用いる製造方法に比べてメッキ作業等が途中工程で入らないために製造工程を単純化することができる。 The above method can simplify the manufacturing process because the plating operation or the like is not performed in the middle of the manufacturing method using the plating operation.
次に、第２配線体を感光性樹脂の塗布、露光、現像によるパターン形成方法によるビルドアップ工法を用いて形成する方法について説明する。 Next, a method of forming the second wiring body by using a build-up method by a pattern forming method by applying a photosensitive resin, exposing, and developing will be described.
図５は、第２配線体を埋め込み型の配線体で形成する製造方法の手順を示すものである。 FIG. 5 shows the procedure of the manufacturing method for forming the second wiring body with an embedded wiring body.
図５（ａ）に示される第２金属基板２２上には、図３（ａ）に示した第１配線体３と同様の配線体２５が形成されている。なお、メモリをスタック構造に積層する場合には第１配線体と第２配線体のパターンは同じ場合が多い。 On the second metal substrate 22 shown in FIG. 5A, a wiring body 25 similar to the first wiring body 3 shown in FIG. 3A is formed. When the memories are stacked in a stack structure, the patterns of the first wiring body and the second wiring body are often the same.
次いで、図５（ｂ）に示すように金属基板１２に第２配線体の端子部に、半完成品の半導体装置２４を接続する。半導体装置２４は、図３（ｆ）に示した状態の半導体装置であり、図３（ｆ）における第１配線体３と接続する端子部１０の突出部１２配線体５の所定の位置に合わせて接続する。 Next, as shown in FIG. 5B, a semi-finished semiconductor device 24 is connected to the metal substrate 12 at the terminal portion of the second wiring body. The semiconductor device 24 is the semiconductor device in the state shown in FIG. 3F, and is aligned with a predetermined position of the protruding portion 12 wiring body 5 of the terminal portion 10 connected to the first wiring body 3 in FIG. Connect.
次に、接続した両者の間にアンダーフィル樹脂２６を充填し、熱硬化させる。このアンダーフィル樹脂を半導体装置２４と配線体２５の間に充填においては、これらの間隔が狭く、また、側面から注入しなければならないため、金属基板の一辺を真空装置のノズル形状の治具で挟み込み減圧しながら対辺から低粘度のアンダーフィル樹脂を注入して毛細管現象と減圧の作用で基板間全面に充填させる方法が有効となる。 Next, the underfill resin 26 is filled between the two connected, and cured. In filling the underfill resin between the semiconductor device 24 and the wiring body 25, these intervals are narrow and must be injected from the side surface. Therefore, one side of the metal substrate is formed with a nozzle-shaped jig of a vacuum device. It is effective to inject a low-viscosity underfill resin from the opposite side while sandwiching and reducing the pressure to fill the entire surface between the substrates by the action of capillary action and pressure reduction.
続いて、基板１および第２金属基板２２をエッチング除去し、その後、半田浴により第１配線体３および配線体２５に端子部２７を形成し、図５（ｃ）に示す状態とする。 Subsequently, the substrate 1 and the second metal substrate 22 are removed by etching, and thereafter, terminal portions 27 are formed on the first wiring body 3 and the wiring body 25 by a solder bath to obtain the state shown in FIG.
上記の半導体装置２４と配線体２５との間にアンダーフィル樹脂を注入する方法に代えて、配線体２５上にシート状または高粘度の接着材を予め適量の厚さに塗布してから半導体装置２４を配線体２５に接続して加圧接着すると共に接着材を硬化する方法も一般的に用いられる方法である。 Instead of the method of injecting an underfill resin between the semiconductor device 24 and the wiring body 25 described above, a sheet-like or high-viscosity adhesive material is applied to the wiring body 25 in advance to an appropriate thickness, and then the semiconductor device. A method of connecting the wiring 24 to the wiring body 25 and performing pressure bonding and curing the adhesive is also a generally used method.
これらの方法で製造された半導体装置の具体的な寸法は、配線基板２５（第２配線体）および第１配線体３（第１配線体）の厚さがそれぞれ１０〜１５μｍ、半導体素子厚が１０μｍ、配線基板と半導体素子間を接着するアンダーフィル樹脂厚が５〜１０μｍ程度であり、これらの最大の厚さを合計しても６０μｍ程度の半導体装置ができあがる。 The specific dimensions of the semiconductor device manufactured by these methods are as follows: the thickness of the wiring board 25 (second wiring body) and the first wiring body 3 (first wiring body) is 10 to 15 μm, respectively, and the semiconductor element thickness is The thickness of the underfill resin for bonding between the wiring substrate and the semiconductor element is about 5 to 10 μm, and even when these maximum thicknesses are combined, a semiconductor device of about 60 μm is completed.
図３に示した第２配線体としてテープ配線基板１４を用いた場合には、テープ配線基板１４の厚さは５０〜８０μｍ程度あり、合計厚さは１２５μｍの厚さになる。 When the tape wiring substrate 14 is used as the second wiring body shown in FIG. 3, the thickness of the tape wiring substrate 14 is about 50 to 80 μm, and the total thickness is 125 μm.
次に、第１配線体および第２配線体を多層に形成する製造方法について説明する。 Next, a manufacturing method for forming the first wiring body and the second wiring body in multiple layers will be described.
図３に示した金属基板１にＮｉ／Ａｕのパターンを形成してからポリイミド等の感光性接着材を塗布、露光、現像してコンタクト孔を設けた後に、銅配線をパターニング形成する。こうすることによって多層配線が形成できる。この方法は、ビルドアップ法と一般的に呼ばれている。 After forming a Ni / Au pattern on the metal substrate 1 shown in FIG. 3, a photosensitive adhesive such as polyimide is applied, exposed, and developed to provide contact holes, and then copper wiring is patterned. By doing so, a multilayer wiring can be formed. This method is generally called a build-up method.
上記のようにして作製した第１配線基板および第２配線基板を備える半導体素子を上述した方法を組み合わせて接続する。 The semiconductor elements including the first wiring board and the second wiring board manufactured as described above are connected by combining the above-described methods.
上記の方法で第１配線体および第２配線体を多層配線することによって、端子部を半導体素子の周辺及び半導体素子上に配置することが自由にでき、さらなる半導体装置の小面積化が可能となる。 By the multilayer wiring of the first wiring body and the second wiring body by the above method, the terminal portion can be freely arranged around the semiconductor element and on the semiconductor element, and the area of the semiconductor device can be further reduced. Become.
次に、半導体装置の第２実施例について図４を用いて説明する。 Next, a second embodiment of the semiconductor device will be described with reference to FIG.
図４は、図３（ｇ）における第２の配線体に相当するテープ配線基板１４を接続する工程を省略し、半導体素子４の片側のみに薄膜を用いた配線体が用いられた半導体装置としたものである。この場合には、第２配線体を用いない分薄く形成できるが、素子４の裏面１３に端子部（図３（ｇ）における１０３）を設けることができず、その分半導体素子４の外部に設けなければならないため、半導体装置の大きさが若干大きくなる。 4 omits the step of connecting the tape wiring substrate 14 corresponding to the second wiring body in FIG. 3G, and includes a semiconductor device in which a wiring body using a thin film is used only on one side of the semiconductor element 4. It is a thing. In this case, the second wiring body can be thinned without using the second wiring body. However, the terminal portion (103 in FIG. 3G) cannot be provided on the back surface 13 of the element 4, and accordingly, outside the semiconductor element 4 accordingly. Since it must be provided, the size of the semiconductor device is slightly increased.
次に、上記のように構成された半導体装置を多段に積層した半導体モジュールについて説明する。 Next, a semiconductor module in which the semiconductor devices configured as described above are stacked in multiple stages will be described.
図６は、図２に示した状態の半導体装置７０を位置決め治具２１に多段に重ねてリフロー炉に通して端子部同志を接続したものである。このため、図６には示さないが、以下の説明では図２に示した符号を用いて説明する。 FIG. 6 shows the semiconductor device 70 in the state shown in FIG. 2 stacked in multiple stages on the positioning jig 21 and passed through a reflow furnace to connect the terminals. For this reason, although not shown in FIG. 6, in the following description, it demonstrates using the code | symbol shown in FIG.
図６は、図２に示した状態の半導体装置７０を複数個スタック構造に積層した半導体モジュールの断面図である。図２に示した状態の半導体装置７０の第１配線体３の端子部１５に、印刷法またはメッキ法により半田ボールをあらかじめ設けておく。配線体１９には半田のような材料を設けておく必要はなく、半田と塗れ性の良い材料、例えば金を０．１μｍ程度被着させておく。これは、例えば、図３に示したように配線体１９としてテープ配線基板１４を使用する場合には、その製造工程から材料構成は一般的なものであり全く問題ない。 FIG. 6 is a cross-sectional view of a semiconductor module in which a plurality of semiconductor devices 70 in the state shown in FIG. 2 are stacked in a stack structure. Solder balls are provided in advance on the terminal portion 15 of the first wiring body 3 of the semiconductor device 70 in the state shown in FIG. 2 by a printing method or a plating method. The wiring body 19 does not need to be provided with a material such as solder, and a material having good wettability with solder, for example, gold is applied to about 0.1 μm. For example, when the tape wiring substrate 14 is used as the wiring body 19 as shown in FIG. 3, the material structure is general from the manufacturing process, and there is no problem at all.
次に、半導体装置７０の端子部を治具２１で位置決めして、一つ目の半導体装置の上に２つ目、３つ目と重ねていくと１つ目の半導体装置７０の第２配線基板１９の端子部１６に２つ目の半導体装置７０の第１配線基板３の端子部１５が接触し、窒素雰囲気のソルダーリフロー装置で加熱溶融すると図６に示すように各端子部が電気的に導通した積層型半導体装置が完成する。 Next, when the terminal portion of the semiconductor device 70 is positioned by the jig 21 and overlapped with the second and third on the first semiconductor device, the second wiring of the first semiconductor device 70 is obtained. When the terminal portion 15 of the first wiring substrate 3 of the second semiconductor device 70 comes into contact with the terminal portion 16 of the substrate 19 and is heated and melted by a solder reflow apparatus in a nitrogen atmosphere, each terminal portion is electrically connected as shown in FIG. Thus, a stacked semiconductor device that is electrically connected to the substrate is completed.
図７は、図４に示した状態の半導体装置８０を多段に重ねてリフロー炉に通して端子部同志を接続したものである。このため、図７には示さないが、以下の説明では図４に示した符号を用いて説明する。 FIG. 7 is a diagram in which the semiconductor devices 80 in the state shown in FIG. 4 are stacked in multiple stages and passed through a reflow furnace to connect the terminals. For this reason, although not shown in FIG. 7, in the following description, it demonstrates using the code | symbol shown in FIG.
図７は、図４に示した状態の半導体装置８０を同様に重ねて端子部をリフローして電気的に導通させた構造である。本実施例においても図６に示した実施例と同様に位置決め治具使用しているが図示省略している。本実施例の場合には、端子部１５が半導体装置８０の周辺部に形成されている点のみが図６に示した実施例との違いであり、図６に示した積層型半導体装置よりも第２配線基板１９がない分だけ厚さが薄くなるが、ピン数が同じ場合には平面的な面積は大きくなる可能性がある。 FIG. 7 shows a structure in which the semiconductor devices 80 in the state shown in FIG. In this embodiment, a positioning jig is used as in the embodiment shown in FIG. In the case of the present embodiment, only the point that the terminal portion 15 is formed in the peripheral portion of the semiconductor device 80 is different from the embodiment shown in FIG. 6 and is more than the stacked semiconductor device shown in FIG. Although the thickness is reduced by the absence of the second wiring substrate 19, the planar area may be increased when the number of pins is the same.
次に、図６および図７に示すようなスタック構造の積層型半導体装置を効率よく製造する方法について、図８の断面図および図９の平面図を参照して説明する。 Next, a method for efficiently manufacturing a stacked semiconductor device having a stack structure as shown in FIGS. 6 and 7 will be described with reference to a cross-sectional view of FIG. 8 and a plan view of FIG.
まず、図３（ａ）〜（ｇ）の工程を経て図２に示す構造の半導体装置を作製する。このとき、基板から半導体素子を個片に切り出す切断工程を実施せず、半完成品の半導体装置２６とする。 First, the semiconductor device having the structure shown in FIG. 2 is manufactured through the steps of FIGS. At this time, the semiconductor device 26 is a semi-finished product without performing the cutting step of cutting the semiconductor element into individual pieces from the substrate.
次に、半完成品の半導体装置２６を多段に積層して基板の表面と裏面に設けられた端子部を位置合わせして接続部に被着されている接合部材をリフロー炉に通して溶融接続する。この状態の積層された基板をダイシング装置によって半導体素子間を切り離すことによって４段重ねの積層型半導体装置が完成する。 Next, semi-finished semiconductor devices 26 are stacked in multiple stages, the terminal portions provided on the front and back surfaces of the substrate are aligned, and the joining member attached to the connection portion is passed through a reflow furnace to be melt-connected. To do. The stacked substrate in this state is completed by separating the semiconductor elements from each other with a dicing device.
以上では半導体装置間の接続方法としてリフロー法による溶融接続を例に用いて説明したが、例えばこの他に端子部に金バンプを形成しておくことにより、金−金圧着法や、圧接法などの工法を用いることも可能である。 In the above description, the fusion connection by the reflow method is used as an example of the connection method between the semiconductor devices. However, for example, by forming a gold bump on the terminal portion, a gold-gold pressure bonding method, a pressure welding method, etc. It is also possible to use this method.
また、半導体装置を積層した後、半導体装置間に樹脂を注入、硬化させるか、もしくは半導体装置間に、あらかじめシート状、もしくは液状の接着剤を供給しておくことにより、接続部を封止することで、より信頼性の高い積層型半導体装置を得ることも可能である。 In addition, after the semiconductor devices are stacked, the connection portion is sealed by injecting and curing a resin between the semiconductor devices, or by supplying a sheet-like or liquid adhesive in advance between the semiconductor devices. Thus, a more reliable stacked semiconductor device can be obtained.
１ 基板
２ Ｎｉメッキ
３ 第１配線体
４ 半導体素子
５ 電極
６ 樹脂
７ アンダーフィル
８ レーザー光
９ スルーホール
１０ 導体柱
１１ 銅金属
１２ 突出部
１３ 半導体素子の裏面
１４ テープ配線基板
１５，１６ 端子部
１９ 第２配線体
２１ 位置決め治具
２２ 第２金属基板
２５ 配線体
２６ 半完成品の半導体装置
DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Ni plating 3 1st wiring body 4 Semiconductor element 5 Electrode 6 Resin 7 Underfill 8 Laser beam 9 Through hole 10 Conductor pillar 11 Copper metal 12 Protrusion part 13 Back surface 14 of semiconductor element Tape wiring board 15 and 16 Terminal part 19 Second wiring body 21 Positioning jig 22 Second metal substrate 25 Wiring body 26 Semi-finished semiconductor device
Claims (10)
前面に電極を有し、前記第１の面に搭載されて前記電極を介して前記第１の配線と電気的に接続するＩＣチップと、
前記第１の面に配設されて前記第１の配線と電気的に接続する導体柱と、
前記ＩＣチップと導体柱との間に充填されて前記第１の面と反対側となる上面を形成するとともに前記導体柱の端面を露出させる絶縁性樹脂と、を備え、
前記絶縁性樹脂の下面を前記配線体により完全に覆うように前記配線体が連続した膜により形成されている半導体装置。 A wiring body comprising a first wiring and having a first surface and a second surface opposite to the first surface;
An IC chip having an electrode on the front surface and mounted on the first surface and electrically connected to the first wiring via the electrode;
A conductor post disposed on the first surface and electrically connected to the first wiring;
An insulating resin that is filled between the IC chip and the conductor column and forms an upper surface opposite to the first surface and exposes an end surface of the conductor column;
A semiconductor device in which the wiring body is formed of a continuous film so that the lower surface of the insulating resin is completely covered by the wiring body.
前記端面と前記上面が実質的に連続した平坦な面である半導体装置。 The semiconductor device according to claim 1,
A semiconductor device in which the end surface and the upper surface are substantially continuous flat surfaces.
前記配線体の前記第２の面に設けられた第２の配線を有する半導体装置。 The semiconductor device according to claim 2,
A semiconductor device having a second wiring provided on the second surface of the wiring body.
前記上面に設けられ、前記端面と電気的に接続する第３の配線を有する半導体装置。 The semiconductor device according to claim 3.
A semiconductor device having a third wiring provided on the upper surface and electrically connected to the end surface.
前記端面と前記第２の配線との間に形成された半田ボールを有する半導体装置。 The semiconductor device according to claim 4.
A semiconductor device having a solder ball formed between the end face and the second wiring.
前記第２の配線上に形成された半田ボールを有する半導体装置。 The semiconductor device according to claim 3.
A semiconductor device having a solder ball formed on the second wiring.
前記複数の半導体装置のなかの１つの半導体装置の端面は、他の半導体装置の第２の配線と電気的に接続する積層型半導体装置。 A stacked semiconductor device in which a plurality of semiconductor devices according to claim 3 are stacked,
A stacked semiconductor device in which an end surface of one of the plurality of semiconductor devices is electrically connected to a second wiring of another semiconductor device.
前記上面に形成され、前記端面と電気的に接続する第３の配線を有する半導体装置。 The semiconductor device according to claim 1,
A semiconductor device having a third wiring formed on the upper surface and electrically connected to the end surface.
前記端面上に形成された半田ボールを有する半導体装置。 The semiconductor device according to claim 1,
A semiconductor device having solder balls formed on the end face.
前記配線体は、前記第２の面の露出部分に配設されたレジスト層を有する半導体装置。
The semiconductor device according to claim 1,
The said wiring body is a semiconductor device which has a resist layer arrange | positioned in the exposed part of the said 2nd surface.
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