JP2007515079A - 従来の端子を備えた超接合装置の製造方法 - Google Patents
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Abstract
【選択図】 なし
Description
図1から図11は、本発明の第1の好ましい実施例による、従来の端子を備えた超接合装置の製造方法を示す。
Claims (14)
- 半導体ディバイスの製造方法であって、
相互に対向する第1及び第2の主表面を有する半導体基板を設け、上記の半導体基板は、第2主表面に第1導電率形の強くドープされた領域を有し、第1主表面に第1導電率形の軽くドープされた領域を有し、
上記の半導体基板において、その作動領域に複数個の溝と複数個のメサとをエッチングにより設け、各溝は、強くドープされた領域に向け、第1主表面から第1深さ位置まで伸びる第1延長部分を有し、各メサは、第1主表面に対し所定の傾斜を維持する側壁面を有し、上記の複数個の溝の各々は、複数個のメサの1つにより、その他の溝の各々から離れていて、
作動領域と、作動領域の外側およびこれに隣接する端子領域内に延びる、複数個のメサと複数個の溝との所定領域を、各メサの頂部、複数個の溝の各々の両側面および底部ならびに端子領域の頂部を酸化物が覆うまで酸化し、
複数個のメサと複数個の溝との所定領域を、乾式酸化物エンチング法を用いてエッチングし、複数個の溝の底部にある酸化物を除去し、
作動領域と端子領域との間の境界の所定領域上に保護シールドを形成し、
その後複数個のメサと複数個の溝との所定領域の上から保護シールドを部分的に除去し、
複数個のメサと複数個の溝との所定領域の少なくとも1つの所定のメサに、隣接対の溝において、1つの溝の側壁面で、第1導電率形のドーパントを、第1所定打込み角度で打込み、上記の1つの溝の側壁面に、強くドープされた領域より低いドープ濃度を有する第1導電率形の第1ドープ領域を形成し、
複数個のメサと複数個の溝との所定領域の少なくとも1つのメサに、第1導電率形のドーパントを打込んだ側壁に対向する上記の少なくとも1つのメサの側壁面で、第2導電率形のドーパントを、第2所定打込み角度で打込んで、第1導電率形のドーパントを打込んだ側壁に対向する側壁面に第2導電率形の第2ドープ領域を設けて、複数個の溝の少なくとも1つの溝の深さ方向に沿って位置する第1および第2ドープ領域のP−N接合を形成すると共に、作動領域のイオンが打込まれていない外側壁を設け、
複数個の溝に絶縁材料を充填し、
構造体の頂面を平坦化して、
超接合装置をこの構造体上に形成するもの。 - 請求項1に記載の半導体ディバイスの製造方法であって、保護シールドを形成する工程が、
複数個のメサと複数個の溝との所定領域の上にフォトレジストの層を沈着させ、
複数個のメサと複数個の溝との所定領域の各側の最後の溝の外側壁上のフォトレジストが保護され、上記の所定領域の残りの個所は保護されないように、マスクを置き、
フォトレジストの保護されていない部分を、紫外線光、深紫外線光、電子ビームおよびX線を含むグループから選ばれたフォトレジスト反応体に晒すことからなるものにおいて、
上記の保護シールドを部分的に除去する工程が、
複数個のメサと複数個の溝との所定領域上からマスクを除き、
反応したフォトレジストを構造体から取除き、
複数個のメサと複数個の溝の所定領域を湿式酸化物エッチング法によりエッチングして、反応しなかったフォトレジストにより酸化物が保護されていた上記の所定領域の各側の最後の溝の外側壁をのぞいて、上記の所定領域から反応しなかったフォトレジストと酸化物とを除去し、上記の酸化物は上記の各最後の溝の外側壁へのイオン打込みを阻止するため残されているもの。 - 請求項2に記載の半導体ディバイスの製造方法であって、
第2ドープ領域と電気的に連結する第3ドープ領域を第1および第2ドープ領域の第1主表面に設け、
第1導電率形の第4ドープ領域を、これが第3ドープ領域を挟んで第1ドープ領域と対向するように、上記の1つの溝の第1主表面と側壁面の少なくとも一方に設け、
ゲート電極層を、第1ドープ領域と第4ドープ領域との間で、ゲート絶縁層を介在させて第3ドープ領域に対向させて設けることからなるもの。 - 請求項3に記載の半導体ディバイスの製造方法であって、ゲート電極層が少なくとも1つの溝に形成されるもの。
- 請求項3に記載の半導体ディバイスの製造方法であって、ゲート電極層が第1主表面上に形成されるもの。
- 請求項1に記載の半導体ディバイスの製造方法であって、保護シールドを形成する工程が、
複数個のメサと複数個の溝との所定領域を乾式酸化物エッチング法を用いてエッチングして、複数個の溝の各々の両側部と底部とにある酸化物を除去し、
マスクを、このマスクの開口部のみが、作動領域の各側の最後の溝とこれに隣接するメサ領域上に位置するように位置決めし、
作動領域の最後の溝とこれに隣接するメサ領域のみが、フォトレジストが沈着する領域であるようにフォトレジストの層をマスク上に沈着させることからなるものにおいて、
部分的に保護シールドを除去する工程が、最後の溝とこれに隣接するメサ領域とを除いて、フォトレジストが沈着するのを阻止したマスクを除去することからなるもの。 - 請求項6に記載の半導体ディバイスの製造方法であって、更に、
第2ドープ領域と電気的に連結する第3ドープ領域を第1および第2ドープ領域の第1主表面に設け、
第1導電率形の第4ドープ領域を、これが第3ドープ領域を挟んで第1ドープ領域と対向するように、上記の複数個の溝の第1主表面と側壁面のいずれか一方に設け、
ゲート電極層を、第1ドープ領域と第4ドープ領域との間で、ゲート絶縁層を介在させて第3ドープ領域に対向させて設けることからなるもの。 - 請求項6に記載の半導体ディバイスの製造方法であって、ゲート電極層が第1主表面上に形成されるもの。
- 請求項6に記載の半導体ディバイスの製造方法であって、更に、
第2ドープ領域と電気的に連結する第3ドープ領域を第1および第2ドープ領域の第1主表面に設けることからなるもの。 - 請求項6に記載の半導体ディバイスの製造方法であって、更に、電極層を第1ドープ領域とオーム接触させるもの。
- 請求項6に記載の半導体ディバイスの製造方法であって、更に、
半導体ディバイスの製造において第1および第2導電率形のドーパントの各々の拡散長さが、隣接対の側壁面から、第1および第2ドープ領域のP−N接合までの距離より長いもの。 - 請求項1に記載の半導体ディバイスの製造方法であって、更に、
第2ドープ領域と電気的に連結する第3ドープ領域を第1および第2ドープ領域の第1主表面に設けることからなるもの。 - 請求項1に記載の半導体ディバイスの製造方法であって、更に、
電極層を第1ドープ領域とショットキー(Schottky)接触させることからなるもの。 - 請求項1に記載の半導体ディバイスの製造方法であって、
半導体ディバイスの製造において第1および第2導電率形のドーパントの各々の拡散長さが、隣接対の溝の側壁面から、第1および第2ドープ領域のP−N接合までの距離より長いもの。
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PCT/US2004/041302 WO2005065140A2 (en) | 2003-12-19 | 2004-12-10 | Method of manufacturing a superjunction device with conventional terminations |
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KR20080100265A (ko) | 2008-11-14 |
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US7704864B2 (en) | 2010-04-27 |
US7041560B2 (en) | 2006-05-09 |
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TW200531280A (en) | 2005-09-16 |
WO2005065140A2 (en) | 2005-07-21 |
US20050181558A1 (en) | 2005-08-18 |
EP1701686A4 (en) | 2009-07-01 |
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US20060160309A1 (en) | 2006-07-20 |
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