JP2007335532A - Graphene intergrated circuit - Google Patents

Graphene intergrated circuit Download PDF

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JP2007335532A
JP2007335532A JP2006163856A JP2006163856A JP2007335532A JP 2007335532 A JP2007335532 A JP 2007335532A JP 2006163856 A JP2006163856 A JP 2006163856A JP 2006163856 A JP2006163856 A JP 2006163856A JP 2007335532 A JP2007335532 A JP 2007335532A
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graphene
silicon carbide
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JP5167479B2 (en
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Kanji Yo
完治 陽
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Hokkaido University NUC
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for integrating nonlinear elements containing graphene, and to improve degree of integration of a semiconductor. <P>SOLUTION: The graphene integrated circuit has nonlinear elements, containing graphene formed on a silicon surface of a silicon carbide substrate. Its manufacturing method comprises a step of preparing the silicon carbide substrate, having the silicon surface covered with an insulation film; a step of removing the insulating film on a plurality of desired portions, to expose the silicon surface; a step of heating the substrate to form graphene on the exposed portions; a step of forming ohmic electrodes on the graphene, or a step of heating the substrate, having the silicon surface to form graphene on the silicon surface; a step of isolating the graphene; a step of forming an insulation film on the trenches formed by the isolation; and a step of forming ohmic electrodes on the graphene. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、グラフェンを含む非線形素子を有するグラフェン集積回路に関する。   The present invention relates to a graphene integrated circuit having a nonlinear element including graphene.

ＣＭＯＳ集積回路は、エレクトロニクスの基盤技術であるが、その半導体の集積度の向上を、ムーアの法則に示されるように維持することが困難になりつつある。具体的には、増大を続ける消費電力に伴う発熱が抑えられない状態にまで達していることがある。さらに、微細化に伴うショートチャンネル効果などの問題を抑えることと、寄生抵抗を低減することが相容れないため、微細化が行き詰まっていることがある。そのため、新しい材料を含めて様々な方法でこれを解決する努力が続けられている。それにより、カーボンナノチューブトランジスタが開発されたが、カーボンナノチューブトランジスタを集積化することは、本質的に困難である。   The CMOS integrated circuit is a basic technology of electronics, but it is becoming difficult to maintain the improvement of the degree of integration of the semiconductor as shown by Moore's law. Specifically, there is a case where the heat generation accompanying the continuously increasing power consumption has reached a state where it cannot be suppressed. Furthermore, miniaturization may be stuck because it is incompatible with suppressing problems such as the short channel effect associated with miniaturization and reducing parasitic resistance. Therefore, efforts are being made to solve this in various ways, including new materials. Thereby, carbon nanotube transistors have been developed, but it is inherently difficult to integrate the carbon nanotube transistors.

一方、カーボンナノチューブトランジスタをある意味で、たとえばコンタクト抵抗などの点で凌駕するデバイスポテンシャルを有するグラフェントランジスタが考えられている。従って、グラフェントランジスタを任意の部位に集積化できる技術があれば、半導体の集積度の向上が期待できる。   On the other hand, a graphene transistor having a device potential that surpasses the carbon nanotube transistor in terms of contact resistance, for example, has been considered. Therefore, if there is a technology that can integrate the graphene transistor at an arbitrary position, an improvement in the integration degree of the semiconductor can be expected.

グラファイト（グラフェン超薄膜）を形成する技術としては、６Ｈ-シリコンカーバイドの（０００１）シリコン面を熱処理することによって、シリコンを脱離させて超薄膜のエピタキシャルグラファイトを形成させることが報告されている（非特許文献１参照）。   As a technique for forming graphite (ultra-graphene ultra-thin film), it is reported that the (0001) silicon surface of 6H-silicon carbide is heat-treated to desorb silicon to form ultra-thin epitaxial graphite ( Non-patent document 1).

一方、微傾斜面を有するシリコンカーバイドを特定の方法でエッチング処理すると、クリアなステップ／テラス構造となることが報告されている（非特許文献２参照）。
J. Phys. Chem. B 2004, 108, 19912-19916 Physical Review Letters. Volume 91, Number 22, 226107 On the other hand, it has been reported that when silicon carbide having a slightly inclined surface is etched by a specific method, a clear step / terrace structure is obtained (see Non-Patent Document 2).
J. Phys. Chem. B 2004, 108, 19912-19916 Physical Review Letters. Volume 91, Number 22, 226107

本発明の目的は、グラフェンを含む非線形素子を集積化する技術を提供することである。   An object of the present invention is to provide a technique for integrating nonlinear elements including graphene.

本発明は、シリコンカーバイド基板の表面の所望の部位に、グラフェンを形成することができる手段を新たに見いだすことにより完成された。   The present invention has been completed by newly finding a means capable of forming graphene at a desired site on the surface of a silicon carbide substrate.

本発明の第一は以下に示すグラフェン集積回路に関する。
［１］シリコンカーバイド基板のシリコン面に形成されたグラフェンを含む非線形素子を有するグラフェン集積回路。
［２］前記シリコンカーバイドのポリタイプは、４Ｈまたは６Ｈである、［１］に記載のグラフェン集積回路。
［３］前記シリコン面は、４Ｈシリコンカーバイド（０００１）のシリコン面、または６Ｈシリコンカーバイド（０００１）のシリコン面である、［１］に記載のグラフェン集積回路。
［４］前記シリコンカーバイド基板のシリコン面は微傾斜面である、［１］に記載のグラフェン集積回路。
［５］複数の前記非線形素子を有する、［１］に記載のグラフェン集積回路。
［６］チップに集積された、［１］に記載のグラフェン集積回路。 The first of the present invention relates to the graphene integrated circuit described below.
[1] A graphene integrated circuit having a non-linear element including graphene formed on a silicon surface of a silicon carbide substrate.
[2] The graphene integrated circuit according to [1], wherein the polytype of the silicon carbide is 4H or 6H.
[3] The graphene integrated circuit according to [1], wherein the silicon surface is a silicon surface of 4H silicon carbide (0001) or a silicon surface of 6H silicon carbide (0001).
[4] The graphene integrated circuit according to [1], wherein the silicon surface of the silicon carbide substrate is a slightly inclined surface.
[5] The graphene integrated circuit according to [1], including a plurality of the nonlinear elements.
[6] The graphene integrated circuit according to [1], integrated on a chip.

本発明の第二は以下に示すグラフェン集積回路の製造方法に関する。
［７］シリコンカーバイド基板のシリコン面に形成されたグラフェンを含む非線形素子を有するグラフェン集積回路の製造方法であって、
絶縁膜で被覆されたシリコン面を有するシリコンカーバイド基板を準備するステップ；複数の所望の部位の前記絶縁膜を除去して、シリコン面を露出させるステップ；前記シリコンカーバイド基板を加熱することによって、前記露出部にグラフェンを形成するステップ；および前記グラフェンにオーミック電極を形成するステップを含む製造方法。
［８］シリコンカーバイド基板のシリコン面に形成されたグラフェンを含む非線形素子を有するグラフェン集積回路の製造方法であって、
シリコン面を有するシリコンカーバイド基板を加熱することによって、当該シリコン面にグラフェンを形成するステップ；前記グラフェンをドライエッチングによりアイソレーションするステップ；前記アイソレーションにより形成された溝に絶縁膜を形成するステップ；および前記グラフェンにオーミック電極を形成するステップを含む製造方法。 The second of the present invention relates to a method for manufacturing a graphene integrated circuit as described below.
[7] A method of manufacturing a graphene integrated circuit having a nonlinear element including graphene formed on a silicon surface of a silicon carbide substrate,
Providing a silicon carbide substrate having a silicon surface coated with an insulating film; removing the insulating film at a plurality of desired sites to expose the silicon surface; and heating the silicon carbide substrate to Forming a graphene on the exposed portion; and forming an ohmic electrode on the graphene.
[8] A method of manufacturing a graphene integrated circuit having a non-linear element including graphene formed on a silicon surface of a silicon carbide substrate,
Heating a silicon carbide substrate having a silicon surface to form graphene on the silicon surface; isolating the graphene by dry etching; forming an insulating film in a trench formed by the isolation; And a method of forming an ohmic electrode on the graphene.

本発明により、グラフェン非線形素子が集積化された回路が提供されるので、さらなるデバイスの集積度の向上が達せられる。   According to the present invention, since a circuit in which graphene nonlinear elements are integrated is provided, further improvement in device integration can be achieved.

１．本発明のグラフェン集積回路
本発明のグラフェン集積回路は、グラフェンを含む複数の非線形素子、およびこれらの非線形素子を接続する配線を有する。さらに抵抗やキャパシタなどの他の回路素子を有していてもよい。 1. Graphene Integrated Circuit of the Present Invention The graphene integrated circuit of the present invention has a plurality of nonlinear elements including graphene and wirings connecting these nonlinear elements. Furthermore, you may have other circuit elements, such as a resistor and a capacitor.

本発明の集積回路が有するグラフェンを含む非線形素子は、グラフェンをチャネル（伝導チャネル）とする素子であればよく、二端子素子であっても、三端子素子であっても、それ以上の多端子素子であってもかまわない。   The non-linear element including graphene included in the integrated circuit of the present invention may be an element having graphene as a channel (conduction channel). It may be an element.

非線形素子に含まれるグラフェンは、単原子層のカーボン結晶構造であってもよく、複数の原子層のカーボン結晶構造であってもよい。複数の原子層とは、例えば一桁数の原子層である。複数原子層のカーボン結晶構造は、一般にグラフェン多層膜（multi-layer graphene）またはグラフェン積層膜（stacked graphene）と称されることもある。   The graphene contained in the nonlinear element may have a carbon crystal structure with a monoatomic layer or a carbon crystal structure with a plurality of atomic layers. The plurality of atomic layers are, for example, single-digit atomic layers. The carbon crystal structure of a multi-atomic layer is sometimes called a graphene multilayer film (multi-layer graphene) or a graphene stacked film (stacked graphene).

非線形素子に含まれるグラフェンは、シリコンカーバイド基板の表面に形成されている。シリコンカーバイドのポリタイプは、４Ｈ-シリコンカーバイドまたは６Ｈ-シリコンカーバイドが好ましく、６Ｈ-シリコンカーバイドがより好ましい。平坦なグラフェンが形成されうるからである。さらにグラフェンが形成されたシリコンカーバイドの表面は、カーボン面でもよいがシリコン面の方がよいと考えられ、４Ｈ-シリコンカーバイドの（０００１）シリコン面、または６Ｈ-シリコンカーバイドの（０００１）シリコン面であることが好ましく、６Ｈ-シリコンカーバイドの（０００１）シリコン面であることがより好ましい。熱力学的に安定したグラフェンが形成されうるからである。   The graphene contained in the nonlinear element is formed on the surface of the silicon carbide substrate. The silicon carbide polytype is preferably 4H-silicon carbide or 6H-silicon carbide, and more preferably 6H-silicon carbide. This is because flat graphene can be formed. Further, the surface of the silicon carbide on which graphene is formed may be a carbon surface, but a silicon surface is considered better. Preferably, it is a (0001) silicon surface of 6H-silicon carbide. This is because thermodynamically stable graphene can be formed.

非線形素子に含まれるグラフェンは、高温アニールにより表面処理されたシリコンカーバイド基板を、真空中で熱処理して表面層のシリコン原子を乖離させ、かつ炭素原子を遊離させることで形成される。   Graphene contained in the non-linear element is formed by heat-treating a silicon carbide substrate surface-treated by high-temperature annealing in vacuum to dissociate silicon atoms in the surface layer and liberate carbon atoms.

グラフェンが形成されるシリコンカーバイド基板は、ジャスト基板であっても傾斜基板であってもよい。シリコンカーバイド基板の傾斜面は、前処理することにより原子ステップがバンチングを起こし、ステップ／テラス構造を形成する。ここで「前処理」とは、例えばH２/HClガスエッチングであり、これらは前述の非特許文献２などを参照して行われる。ステップ／テラス構造を有する傾斜面に形成されたグラフェンは、ストライプ状に形成されうる。微傾斜基板の傾斜角度（オフ角度）に応じてストライプ幅を調整することができるので、所望のストライプ幅のグラフェンを形成することができる。 The silicon carbide substrate on which the graphene is formed may be a just substrate or an inclined substrate. By pre-treating the inclined surface of the silicon carbide substrate, atomic steps cause bunching, and a step / terrace structure is formed. Here, the “pretreatment” is, for example, H 2 / HCl gas etching, which is performed with reference to the aforementioned Non-Patent Document 2 and the like. The graphene formed on the inclined surface having the step / terrace structure can be formed in a stripe shape. Since the stripe width can be adjusted according to the inclination angle (off angle) of the slightly inclined substrate, graphene having a desired stripe width can be formed.

シリコンカーバイドの微傾斜基板の傾斜方向を調整することによって、微傾斜基板上に形成されるグラフェンの電気伝導特性を変化させることができる。つまり、グラフェンの電気伝導特性に方向依存性を発現させることがある。また、半導体性または金属性などのさまざまな特性を自在に付与することもできる。   By adjusting the tilt direction of the vicinal substrate of silicon carbide, it is possible to change the electric conduction characteristics of graphene formed on the vicinal substrate. In other words, direction dependency may be manifested in the electrical conductivity characteristics of graphene. Moreover, various characteristics such as semiconductivity or metallicity can be freely imparted.

本発明の集積回路は、所望の部位に非線形素子が形成されていることを特徴とするが、これはグラフェンをシリコンカーバイド基板の表面の所望の位置に形成することができるためである。グラフェンを所望の位置に形成する手段の例には、例えば以下の二通りの手段が挙げられる（プロセス１および２）。   The integrated circuit of the present invention is characterized in that a non-linear element is formed at a desired portion because graphene can be formed at a desired position on the surface of the silicon carbide substrate. Examples of means for forming graphene at a desired position include the following two means (processes 1 and 2), for example.

（プロセス１）
プロセス１のフローが図１に示される。シリコンカーバイド基板１（図１（ａ））の表面を、絶縁膜２で覆った後、グラフェンを形成させる露出部３−１を設け（図１（ｂ））、そのシリコンカーバイド基板を熱処理して、グラフェン３を形成すればよい（図１（ｃ））。グラフェン３を形成させる露出部３−１以外を絶縁膜２で覆うには、基板１の表面全体に絶縁膜２をデポジションにより形成して、形成された絶縁膜２の所望の部位をエッチングなどにより除去すればよい。絶縁膜２は、例えば、窒化シリコン、酸化シリコン、酸化アルミニウムからなる膜である。 (Process 1)
The flow of process 1 is shown in FIG. After the surface of the silicon carbide substrate 1 (FIG. 1A) is covered with the insulating film 2, an exposed portion 3-1 for forming graphene is provided (FIG. 1B), and the silicon carbide substrate is subjected to heat treatment. Then, graphene 3 may be formed (FIG. 1C). In order to cover the portion other than the exposed portion 3-1 on which the graphene 3 is formed with the insulating film 2, the insulating film 2 is formed on the entire surface of the substrate 1 by deposition, and a desired portion of the formed insulating film 2 is etched. Can be removed. The insulating film 2 is a film made of, for example, silicon nitride, silicon oxide, or aluminum oxide.

（プロセス２）
プロセス２のフローが図２に示される。シリコンカーバイド基板１（図２（ａ））を熱処理して、基板表面全体にグラフェン３の膜を形成し（図２（ｂ））；所望の部位以外のグラフェン膜を、ドライエッチングにより除去して（アイソレーション）；さらにエッチングされた部位には絶縁膜２を形成すればよい（図２（ｃ））。絶縁膜２は、例えば、窒化シリコン、酸化シリコン、酸化アルミニウムからなる膜である。 (Process 2)
The flow of process 2 is shown in FIG. The silicon carbide substrate 1 (FIG. 2A) is heat-treated to form a graphene 3 film over the entire substrate surface (FIG. 2B); the graphene film other than the desired portion is removed by dry etching. (Isolation): An insulating film 2 may be formed on the etched portion (FIG. 2C). The insulating film 2 is a film made of, for example, silicon nitride, silicon oxide, or aluminum oxide.

所望の位置に形成されたグラフェン上には、オーミック電極４が形成されて非線形素子が形成される（図１（ｄ）および図２（ｄ））。オーミック電極４は、クロム、チタン、ニッケル、パラジウムなどの金属膜などの積層体であることが好ましく、それにより低抵抗化が実現される。形成されたオーミック電極は、ソース電極およびドレイン電極となる。   On the graphene formed at a desired position, an ohmic electrode 4 is formed to form a nonlinear element (FIGS. 1D and 2D). The ohmic electrode 4 is preferably a laminate of a metal film made of chromium, titanium, nickel, palladium or the like, thereby realizing low resistance. The formed ohmic electrode becomes a source electrode and a drain electrode.

非線形素子は、さらにゲート電極６が形成されることが好ましい（図１（ｅ）および図２（ｅ））。ゲート電極６は、例えばグラフェン上にゲート酸化膜５を介して形成されればよい。ゲート電極６は、例えばチタン/金（Ti/Au）、またはクロム/金 (Cr/Au)の積層体である。これにより、ゲート変調されるトランジスタが得られる。   It is preferable that the non-linear element further has a gate electrode 6 (FIGS. 1E and 2E). For example, the gate electrode 6 may be formed on the graphene via the gate oxide film 5. The gate electrode 6 is a laminated body of, for example, titanium / gold (Ti / Au) or chromium / gold (Cr / Au). Thereby, a gate-modulated transistor is obtained.

非線形素子（好ましくはトランジスタ）には、適宜保護膜が形成されていてもよい。各非線形素子を金属配線７により接続して集積回路とすればよい（図３（ｆ））。図３（ｆ）には、２つのインバータが順列接続された構造が示される。本発明の集積回路はチップ上に形成され、集積回路が形成されたチップ全体を、ボンディングパッドを除いて覆うことにより、デバイスとしての安定化を図ることができる。   A protective film may be appropriately formed on the nonlinear element (preferably a transistor). What is necessary is just to connect each nonlinear element by the metal wiring 7, and to make an integrated circuit (FIG.3 (f)). FIG. 3F shows a structure in which two inverters are connected in a permutation. The integrated circuit of the present invention is formed on a chip, and the entire chip on which the integrated circuit is formed is covered except for bonding pads, so that stabilization as a device can be achieved.

本発明のグラフェン集積回路は、メモリ回路として用いられうる。すなわち、グラフェンを含むトランジスタは、炭素原子Ｃ１２の同位元素であるＣ１３を用いて、グラフェンからなるチャネル中の核スピンに、電子スピンの情報を転写することにより情報を保持することができる。   The graphene integrated circuit of the present invention can be used as a memory circuit. That is, a transistor including graphene can hold information by transferring information on electron spins to nuclear spins in a channel made of graphene using C13, which is an isotope of carbon atom C12.

また本発明のグラフェン集積回路は、各非線形素子のグラフェンに、複数（通常２つ）の強磁性電極を配置されることで、ラテラル型のMR素子（巨大磁気抵抗素子）を構成することもできる。   The graphene integrated circuit of the present invention can also be configured as a lateral MR element (giant magnetoresistive element) by arranging a plurality of (usually two) ferromagnetic electrodes on the graphene of each nonlinear element. .

６Ｈ-シリコンカーバイドの（０００１）面（オフ角度：０°、ジャスト基板）に、グラフェンを形成し、三端子型の非線形素子（トランジスタ）を形成した。得られた非線形素子のソース−ドレイン電流と、ソース−ドレイン電圧との関係を図４に示した（ゲート電圧＝０）。Ｙ軸がドレイン電流の値を示し、Ｘ軸がソース-ドレイン電圧を示す。各曲線は、ゲート電圧を変化させた場合の電流−電圧曲線を示している。図４に示されるように、電圧と電流が比例していないことがわかる。
これらの非線形素子を配線で接続させれば、グラフェン集積回路が作製される。 Graphene was formed on the (0001) plane of 6H-silicon carbide (off angle: 0 °, just substrate) to form a three-terminal nonlinear element (transistor). FIG. 4 shows the relationship between the source-drain current of the obtained nonlinear element and the source-drain voltage (gate voltage = 0). The Y axis represents the drain current value, and the X axis represents the source-drain voltage. Each curve shows a current-voltage curve when the gate voltage is changed. As shown in FIG. 4, it can be seen that the voltage and current are not proportional.
If these nonlinear elements are connected by wiring, a graphene integrated circuit is manufactured.

本発明のグラフェン集積回路によりデバイスの集積度のさらなる向上が達成され、また新たなメモリが提供される。   The graphene integrated circuit of the present invention achieves further improvement in device integration and provides a new memory.

本発明のグラフェン集積回路における非線形素子の製造プロセスのフローの一例を示す図である。It is a figure which shows an example of the flow of the manufacturing process of the nonlinear element in the graphene integrated circuit of this invention. 本発明のグラフェン集積回路における非線形素子の製造プロセスのフローの別の一例を示す図である。It is a figure which shows another example of the flow of the manufacturing process of the nonlinear element in the graphene integrated circuit of this invention. 本発明のグラフェン集積回路の製造プロセスのフローの一例を示す図である。It is a figure which shows an example of the flow of the manufacturing process of the graphene integrated circuit of this invention. 本発明のグラフェン集積回路における非線形素子（三端子型）の、ドレイン電流とソース-ドレイン電圧の関係を示す図である。It is a figure which shows the relationship between the drain current and source-drain voltage of the nonlinear element (three terminal type | mold) in the graphene integrated circuit of this invention.

符号の説明Explanation of symbols

１：シリコンカーバイド基板
２：絶縁膜
３：グラフェン
３−１：グラフェンを形成するためのシリコン面の露出部
４：オーミック電極
５：ゲート酸化膜
６：ゲート電極
７：金属配線 1: Silicon carbide substrate 2: Insulating film 3: Graphene 3-1: Exposed portion of silicon surface for forming graphene 4: Ohmic electrode 5: Gate oxide film 6: Gate electrode 7: Metal wiring

Claims (9)

シリコンカーバイド基板のシリコン面に形成されたグラフェンを含む非線形素子を有するグラフェン集積回路。   A graphene integrated circuit having a non-linear element including graphene formed on a silicon surface of a silicon carbide substrate. 前記シリコンカーバイドのポリタイプは、４Ｈまたは６Ｈである、請求項１に記載のグラフェン集積回路。   The graphene integrated circuit according to claim 1, wherein the silicon carbide polytype is 4H or 6H. 前記シリコン面は、４Ｈシリコンカーバイド（０００１）のシリコン面、または６Ｈシリコンカーバイド（０００１）のシリコン面である、請求項１に記載のグラフェン集積回路。   The graphene integrated circuit according to claim 1, wherein the silicon surface is a silicon surface of 4H silicon carbide (0001) or a silicon surface of 6H silicon carbide (0001). 前記シリコンカーバイド基板のシリコン面は微傾斜面である、請求項１に記載のグラフェン集積回路。   The graphene integrated circuit according to claim 1, wherein a silicon surface of the silicon carbide substrate is a slightly inclined surface. 複数の前記非線形素子を有する、請求項１に記載のグラフェン集積回路。   The graphene integrated circuit according to claim 1, comprising a plurality of the nonlinear elements. チップに集積された、請求項１に記載のグラフェン集積回路。   The graphene integrated circuit according to claim 1, which is integrated on a chip. シリコンカーバイド基板のシリコン面に形成されたグラフェンを含む非線形素子を有するグラフェン集積回路の製造方法であって、
絶縁膜で被覆されたシリコン面を有するシリコンカーバイド基板を準備するステップ、
複数の所望の部位の前記絶縁膜を除去して、シリコン面を露出させるステップ、
前記シリコンカーバイド基板を加熱することによって、前記露出部にグラフェンを形成するステップ、および
前記グラフェンにオーミック電極を形成するステップを含む製造方法。 A method of manufacturing a graphene integrated circuit having a nonlinear element including graphene formed on a silicon surface of a silicon carbide substrate,
Providing a silicon carbide substrate having a silicon surface coated with an insulating film;
Removing the insulating film at a plurality of desired sites to expose the silicon surface;
A manufacturing method comprising: forming graphene on the exposed portion by heating the silicon carbide substrate; and forming an ohmic electrode on the graphene. シリコンカーバイド基板のシリコン面に形成されたグラフェンを含む非線形素子を有するグラフェン集積回路の製造方法であって、
シリコン面を有するシリコンカーバイド基板を加熱することによって、当該シリコン面にグラフェンを形成するステップ、
前記グラフェンをドライエッチングによりアイソレーションするステップ、
前記アイソレーションにより形成された溝に絶縁膜を形成するステップ、および
前記グラフェンにオーミック電極を形成するステップを含む製造方法。 A method of manufacturing a graphene integrated circuit having a nonlinear element including graphene formed on a silicon surface of a silicon carbide substrate,
Forming graphene on the silicon surface by heating a silicon carbide substrate having the silicon surface;
Isolating the graphene by dry etching;
A manufacturing method comprising the steps of: forming an insulating film in the trench formed by the isolation; and forming an ohmic electrode on the graphene. シリコンカーバイド基板のシリコン面に形成されたグラフェンを含む非線形素子を有するグラフェン集積回路、および
前記非線形素子のグラフェンに配置された複数の強磁性電極を含む、
ラテラル型の巨大磁気抵抗素子。 A graphene integrated circuit having a non-linear element including graphene formed on a silicon surface of a silicon carbide substrate, and a plurality of ferromagnetic electrodes disposed on the graphene of the non-linear element,
Lateral type giant magnetoresistive element.
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