JP2007227820A - Semiconductor device, and manufacturing method thereof - Google Patents

Semiconductor device, and manufacturing method thereof Download PDF

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JP2007227820A
JP2007227820A JP2006049529A JP2006049529A JP2007227820A JP 2007227820 A JP2007227820 A JP 2007227820A JP 2006049529 A JP2006049529 A JP 2006049529A JP 2006049529 A JP2006049529 A JP 2006049529A JP 2007227820 A JP2007227820 A JP 2007227820A
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JP4901241B2 (en
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Masahiko Tsuchiya
正彦 土谷
Tadashi Horio
直史 堀尾
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Stanley Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device structured in such a way that heights of a pair of electrodes are easily aligned. <P>SOLUTION: On a supporting substrate, a first semiconductor layer constructed from a first conductive semiconductor is formed. On the first semiconductor layer, a second semiconductor layer is formed as constructed from a second conductive semiconductor inverse to the first conductive semiconductor. A groove is formed which reaches a bottom face of the second semiconductor layer, and divides the second semiconductor layer into a first area and a second area separated from each other. On the first area of the second semiconductor layer, a first electrode is formed and a second electrode is formed for covering from the second area of the second semiconductor layer to the surface of the first semiconductor layer on the bottom face of the groove. The first semiconductor layer and the second semiconductor layer are formed from a group III-V chemical compound semiconductor containing nitrogen as group-V elements. A face of the first electrode in contact with the second semiconductor layer and a face of the second electrode in contact with the first semiconductor layer and the second semiconductor layer are formed from the same metal material. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関し、特に支持基板の一方の面上に一対の電極が形成された半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a pair of electrodes formed on one surface of a support substrate and a manufacturing method thereof.

図４に、特許文献１に開示された半導体発光素子の断面図を示す。サファイア基板１００の上に、ＧａＮバッファ層１０１、ｎ型ＧａＮ層１０２、ｎ型ＡｌＧａＮ層１０３、ＩｎＧａＮ層１０４、ｐ型ＡｌＧａＮ層１０５、ｐ型ＧａＮ層１０６がこの順番に積層されている。ｎ型ＡｌＧａＮ層１０３からｐ型ＧａＮ層１０６までの積層がメサ状にされ、そのメサの周囲にｎ型ＧａＮ層が露出している。メサの周囲のｎ型ＧａＮ層１０２の上面にｎ側電極１０７が形成され、ｐ型ＧａＮ層１０６の上面にｐ側電極１０８が形成されている。   FIG. 4 is a cross-sectional view of the semiconductor light emitting device disclosed in Patent Document 1. On the sapphire substrate 100, a GaN buffer layer 101, an n-type GaN layer 102, an n-type AlGaN layer 103, an InGaN layer 104, a p-type AlGaN layer 105, and a p-type GaN layer 106 are laminated in this order. The stack from the n-type AlGaN layer 103 to the p-type GaN layer 106 is mesa-shaped, and the n-type GaN layer is exposed around the mesa. An n-side electrode 107 is formed on the upper surface of the n-type GaN layer 102 around the mesa, and a p-side electrode 108 is formed on the upper surface of the p-type GaN layer 106.

電極１０７及び１０８をサブマウント基板に対向させて、半導体発光素子がサブマウント基板に実装される。このとき、電極１０７及び１０８が、サブマウント基板のボンディングパッドに接続される。ＩｎＧａＮ層１０４で発光した光が、サファイア基板１００を通って外部に放射される。   The semiconductor light emitting device is mounted on the submount substrate with the electrodes 107 and 108 facing the submount substrate. At this time, the electrodes 107 and 108 are connected to the bonding pads of the submount substrate. Light emitted from the InGaN layer 104 is emitted to the outside through the sapphire substrate 100.

特開２００３−３１８５１号公報JP 2003-31851 A

図４に示した半導体発光素子では、ｐ側電極１０８がメサの上面に形成され、ｎ側電極１０７がメサの周囲に配置される。このため、ｐ側電極１０８の上面とｎ側電極１０７の上面との高さが揃わない。この半導体発光素子をサブマウント基板にフリップチップボンディングするために、サブマウント基板側で、２つの電極の高さの相違を吸収する構造を採用しなければならない。   In the semiconductor light emitting device shown in FIG. 4, the p-side electrode 108 is formed on the upper surface of the mesa, and the n-side electrode 107 is disposed around the mesa. For this reason, the heights of the upper surface of the p-side electrode 108 and the upper surface of the n-side electrode 107 are not uniform. In order to flip-chip bond the semiconductor light emitting device to the submount substrate, a structure that absorbs the difference in height between the two electrodes must be employed on the submount substrate side.

本発明の目的は、一対の電極の高さを容易に揃えることが可能な構造の半導体装装置及びその製造方法を提供することである。   An object of the present invention is to provide a semiconductor device having a structure capable of easily aligning the height of a pair of electrodes and a method for manufacturing the same.

本発明の一観点によると、
支持基板と、
前記支持基板上に形成され、第１導電型の半導体からなる第１の半導体層と、
前記第１の半導体層の上に形成され、前記第１導電型とは逆の第２導電型の半導体からなる第２の半導体層と、
前記第２の半導体層の底面まで達し、該第２の半導体層を、相互に分離された第１の領域と第２の領域とに区分する溝と、
前記第２の半導体層の第１の領域上に形成された第１の電極と、
前記第２の半導体層の第２の領域上から、前記溝の底面に表れた前記第１の半導体層の表面までを連続的に覆う第２の電極と
を有し、前記第１の半導体層及び第２の半導体層が、Ｖ族元素として窒素を含むＩＩＩ−Ｖ族化合物半導体で形成され、前記第１の電極の、前記第２の半導体層に接する面と、前記第２の電極の、前記第１の半導体層及び第２の半導体層に接する面とが、同一の金属材料で形成されている半導体装置が提供される。 According to one aspect of the invention,
A support substrate;
A first semiconductor layer formed on the support substrate and made of a first conductivity type semiconductor;
A second semiconductor layer formed on the first semiconductor layer and made of a semiconductor of a second conductivity type opposite to the first conductivity type;
A groove that reaches the bottom surface of the second semiconductor layer and divides the second semiconductor layer into a first region and a second region separated from each other;
A first electrode formed on a first region of the second semiconductor layer;
A second electrode that continuously covers from the second region of the second semiconductor layer to the surface of the first semiconductor layer that appears on the bottom surface of the groove, and the first semiconductor layer And the second semiconductor layer is formed of a III-V group compound semiconductor containing nitrogen as a group V element, the surface of the first electrode in contact with the second semiconductor layer, and the second electrode, A semiconductor device is provided in which a surface in contact with the first semiconductor layer and the second semiconductor layer is formed of the same metal material.

本発明の他の観点によると、
支持基板上に、第１導電型の第１の半導体層を形成する工程と、
前記第１の半導体層の上に、前記第１導電型とは逆の第２導電型の第２の半導体層を形成する工程と、
前記第２の半導体層に、少なくとも該第２の半導体層の底面まで達する溝を形成し、該第２の半導体層を、相互に分離された第１の領域と第２の領域とに区分する工程と、
前記第２の半導体層の第１の領域の上に第１の電極を形成し、前記第２の領域の上面から前記溝の底面に露出している前記第１の半導体層の表面までを連続的に覆う第２の電極を形成する工程と
を有し、前記第１の電極及び第２の電極を形成する工程において、両者を同時に成膜する半導体装置の製造方法が提供される。 According to another aspect of the invention,
Forming a first semiconductor layer of a first conductivity type on a support substrate;
Forming a second semiconductor layer of a second conductivity type opposite to the first conductivity type on the first semiconductor layer;
A groove reaching at least the bottom surface of the second semiconductor layer is formed in the second semiconductor layer, and the second semiconductor layer is divided into a first region and a second region separated from each other. Process,
A first electrode is formed on a first region of the second semiconductor layer, and continuous from the upper surface of the second region to the surface of the first semiconductor layer exposed on the bottom surface of the groove. Forming a second electrode that covers the substrate, and in the step of forming the first electrode and the second electrode, a method for manufacturing a semiconductor device is provided in which both are formed simultaneously.

第１の電極及び第２の電極の双方の下に第２の半導体層が配置されているため、２つの電極の上面の高さを容易に揃えることができる。   Since the second semiconductor layer is disposed under both the first electrode and the second electrode, the heights of the upper surfaces of the two electrodes can be easily aligned.

図１に、実施例による半導体発光装置の断面図を示す。サファイアのＣ面が露出した支持基板１の表面上にｎ型半導体層２が形成されている。ｎ型半導体層２の上に、ｐ型半導体層３が形成されている。ｎ型半導体層２及びｐ型半導体層３は、Ｖ族元素として窒素を含むＩＩＩ−Ｖ族化合物半導体で形成される。例えば、ＩｎｙＡｌ１−ｘ−ｙＧａｘＮ（ｘ＋ｙ≦１、０≦ｘ≦１、０≦ｙ≦１）で形成される。ｎ型半導体層２及びｐ型半導体層３は、有機金属化学気相堆積（ＭＯＣＶＤ）法により成膜される。 FIG. 1 is a sectional view of a semiconductor light emitting device according to an embodiment. An n-type semiconductor layer 2 is formed on the surface of the support substrate 1 where the C-plane of sapphire is exposed. A p-type semiconductor layer 3 is formed on the n-type semiconductor layer 2. The n-type semiconductor layer 2 and the p-type semiconductor layer 3 are formed of a III-V group compound semiconductor containing nitrogen as a group V element. For example, it is made of In y Al 1-xy Ga x N (x + y ≦ 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1). The n-type semiconductor layer 2 and the p-type semiconductor layer 3 are formed by metal organic chemical vapor deposition (MOCVD).

ｐ型半導体層３に、少なくともその底面まで達する溝８が形成されている。溝８は、ｐ型半導体層３を、相互に分離された第１の領域３ａと第２の領域３ｂとに区分する。第１の領域３ａは、第２の領域３ｂに比べて大きい。溝８の底面に露出したｎ型半導体層２の一部に、凹部９が形成されている。溝８及び凹部９は、フォトリソグラフィと、塩素ガスを用いた反応性イオンエッチング（ＲＩＥ）により形成される。   A groove 8 reaching at least the bottom surface is formed in the p-type semiconductor layer 3. The trench 8 divides the p-type semiconductor layer 3 into a first region 3a and a second region 3b that are separated from each other. The first area 3a is larger than the second area 3b. A recess 9 is formed in a part of the n-type semiconductor layer 2 exposed on the bottom surface of the groove 8. The groove 8 and the recess 9 are formed by photolithography and reactive ion etching (RIE) using chlorine gas.

ｐ型半導体層３の第１の領域３ａの上に、ｐ側電極４が形成されている。第２の領域３ｂの上面から、その端面を経由して溝８の底面に露出しているｎ型半導体層２の表面までを、ｎ側電極５が覆う。ｎ側電極５は、凹部９の内面に接触している。ｐ側電極４はｐ型半導体層３の第１の領域３ａにオーミック接触し、ｎ側電極５は、溝８の底面及び凹部９の内面においてｎ型半導体層２にオーミック接触する。   A p-side electrode 4 is formed on the first region 3 a of the p-type semiconductor layer 3. The n-side electrode 5 covers from the upper surface of the second region 3b to the surface of the n-type semiconductor layer 2 exposed at the bottom surface of the groove 8 via its end surface. The n-side electrode 5 is in contact with the inner surface of the recess 9. The p-side electrode 4 is in ohmic contact with the first region 3 a of the p-type semiconductor layer 3, and the n-side electrode 5 is in ohmic contact with the n-type semiconductor layer 2 on the bottom surface of the groove 8 and the inner surface of the recess 9.

ｐ側電極４の上にｐ側ボンディングパッド６が形成され、ｎ側電極５の上にｎ側ボンディングパッド７が形成されている。ボンディングパッド６及び７はＡｕ等で形成される。ｐ側電極４、ｎ側電極５、ｐ側ボンディングパッド６及びｎ側ボンディングパッド７は、リフトオフ法を利用した真空蒸着により形成される。   A p-side bonding pad 6 is formed on the p-side electrode 4, and an n-side bonding pad 7 is formed on the n-side electrode 5. The bonding pads 6 and 7 are made of Au or the like. The p-side electrode 4, the n-side electrode 5, the p-side bonding pad 6 and the n-side bonding pad 7 are formed by vacuum deposition using a lift-off method.

次に、図２Ａ及び図２Ｂを参照して、ｐ側電極４及びｎ側電極５の構造及び形成方法について説明する。   Next, with reference to FIG. 2A and FIG. 2B, the structure and formation method of the p-side electrode 4 and the n-side electrode 5 will be described.

図２Ａに、ｐ側電極４の第１の構成例を示す。ｐ側電極４は、第１の領域３ａ側から順番に、Ｒｈ層４ＲとＡｌ層４Ａとが交互に４層ずつ積層された８層構造を有する。盆ディングパッド５は、Ｔｉ層５Ｔ、Ｐｔ層５Ｐ、及びＡｕ層５Ａが積層された３層構造を有する。第１層目のＲｈ層４Ｒから第４層目のＡｌ層４Ａまでの４層の各々の厚さは０．３ｎｍである。第５層目のＲｈ層４Ｒ及び第６層目のＡｌ層４Ａの各々の厚さは０．５ｎｍである。第７層目のＲｈ層４Ｒの厚さは２ｎｍであり、第８層目のＡｌ層４Ａの厚さは９８ｎｍである。第８層目のＡｌ層４Ａは、図１に示した第１の半導体層２と第１の領域３ａとの界面で発生した光を反射する反射電極として作用する。   FIG. 2A shows a first configuration example of the p-side electrode 4. The p-side electrode 4 has an eight-layer structure in which four Rh layers 4R and four Al layers 4A are alternately stacked in order from the first region 3a side. The bonding pad 5 has a three-layer structure in which a Ti layer 5T, a Pt layer 5P, and an Au layer 5A are stacked. The thickness of each of the four layers from the first Rh layer 4R to the fourth Al layer 4A is 0.3 nm. The thickness of each of the fifth Rh layer 4R and the sixth Al layer 4A is 0.5 nm. The thickness of the seventh Rh layer 4R is 2 nm, and the thickness of the eighth Al layer 4A is 98 nm. The eighth Al layer 4A functions as a reflective electrode that reflects light generated at the interface between the first semiconductor layer 2 and the first region 3a shown in FIG.

Ｔｉ層５Ｔ及びＰｔ層５Ｐの各々の厚さは５０ｎｍであり、Ａｕ層５Ａの厚さは２００ｎｍである。ｎ側電極５は、ｐ側電極４と同一の積層構造を有する。これらの層は、真空蒸着により形成される。   Each of the Ti layer 5T and the Pt layer 5P has a thickness of 50 nm, and the Au layer 5A has a thickness of 200 nm. The n-side electrode 5 has the same stacked structure as the p-side electrode 4. These layers are formed by vacuum deposition.

一般に、Ｖ族元素としてＮを含むｐ型ＩＩＩ−Ｖ族化合物半導体にオーミック接触するｐ側電極材料としてＲｈが用いられ、ｎ型ＩＩＩ−Ｖ族化合物半導体にオーミック接触するｎ側電極材料としてＡｌが用いられる。   Generally, Rh is used as a p-side electrode material in ohmic contact with a p-type III-V compound semiconductor containing N as a V-group element, and Al is used as an n-side electrode material in ohmic contact with an n-type III-V compound semiconductor. Used.

図２Ａに示した第１の構成例では、第１層目のＲｈ層４Ｒがｐ型半導体層３の第１の領域３ａに接触する。このため、ｐ側電極４をｐ型の第１の領域３ａにのオーミック接触させることができる。   In the first configuration example shown in FIG. 2A, the first Rh layer 4 </ b> R is in contact with the first region 3 a of the p-type semiconductor layer 3. For this reason, the p-side electrode 4 can be brought into ohmic contact with the p-type first region 3a.

また、第１の構成例では、第１層目のＲｈ層４Ｒから第６層目のＡｌ層４Ａまでの６層の各々の厚さが、０．３ｎｍ〜０．５ｎｍ程度であり、非常に薄い。このため、実際には、第１層目のＲｈ４Ｒが、図１に示した第１の領域３ａ及び第２の領域３ｂの上面、及び溝８及び凹部９の内面を隈なく被覆することはなく、第１層目のＲｈ層４Ｒを堆積した時点で、これらの表面が露出した領域がまだらに存在すると考えられる。その上に第２層目のＡｌ層４Ａを堆積させると、一部の領域において、第２層目のＡｌ層４Ａと、まだらに露出していた表面とが接触する。溝８及び凹部９の内面に露出していたｎ型半導体層２に、第２層目のＡｌ層４Ａが接触するため、ｎ側電極５をｎ型半導体層２にオーミック接触させることができる。   In the first configuration example, the thickness of each of the six layers from the first Rh layer 4R to the sixth Al layer 4A is about 0.3 nm to 0.5 nm. thin. Therefore, in actuality, the first layer Rh4R does not cover the upper surfaces of the first region 3a and the second region 3b shown in FIG. When the first Rh layer 4R is deposited, it is considered that there are mottled regions where these surfaces are exposed. When the second Al layer 4A is deposited thereon, the second Al layer 4A comes into contact with the mottled surface in a part of the region. Since the second Al layer 4A is in contact with the n-type semiconductor layer 2 exposed on the inner surfaces of the groove 8 and the recess 9, the n-side electrode 5 can be in ohmic contact with the n-type semiconductor layer 2.

このように、ｐ側電極４及びｎ側電極５の、ｐ型半導体層３及びｎ型半導体層２に接触する面が、ｐ型半導体層３とオーミック接触する金属Ｒｈからなる領域と、ｎ型半導体層２とオーミック接触する他の金属Ａｌからなる領域とを含む。これにより、同一の電極構造を採用しても、ｐ型及びｎ型の両方の半導体層にオーミック接触させることが可能になる。   As described above, the surfaces of the p-side electrode 4 and the n-side electrode 5 that are in contact with the p-type semiconductor layer 3 and the n-type semiconductor layer 2 are made of the metal Rh that is in ohmic contact with the p-type semiconductor layer 3 and the n-type electrode. And a region made of other metal Al in ohmic contact with the semiconductor layer 2. Thereby, even if the same electrode structure is employed, it is possible to make ohmic contact with both the p-type and n-type semiconductor layers.

実際に、ｐ型半導体層３とｐ側電極４との接触抵抗は約９．４×１０−３Ωｃｍ２であり、ｎ型半導体層２とｎ側電極５との接触抵抗は約８．６×１０−５Ωｃｍ２であった。これにより、動作電圧３．４Ｖの青色発光ダイオードが実現された。この動作電圧は、図４に示した従来の素子と比べて遜色のないものである。ｐ型の第１の領域３ａにオーミック接触させることができる材料として、Ｒｈの代わりに、Ｐｔ、Ｉｒ、Ｐｄ等を用いてもよい。 Actually, the contact resistance between the p-type semiconductor layer 3 and the p-side electrode 4 is about 9.4 × 10 −3 Ωcm 2 , and the contact resistance between the n-type semiconductor layer 2 and the n-side electrode 5 is about 8.6. × 10 −5 Ωcm 2 . As a result, a blue light emitting diode with an operating voltage of 3.4 V was realized. This operating voltage is comparable to the conventional element shown in FIG. Pt, Ir, Pd, or the like may be used instead of Rh as a material that can be brought into ohmic contact with the p-type first region 3a.

図２Ｂに、ｐ側電極４の第２の構成例を示す。ｐ側電極４は、第１の領域３ａ側から順番に、厚さ１ｎｍのＲｈ層４Ｒと厚さ５００ｎｍのＡｌ層４Ａとが積層された２層構造を有する。ボンディングパッド５は、第１の構成例のものと同一の積層構造を有する。これらの層は、真空蒸着により形成される。ｎ側電極５も同様の積層構造を有する。   FIG. 2B shows a second configuration example of the p-side electrode 4. The p-side electrode 4 has a two-layer structure in which an Rh layer 4R having a thickness of 1 nm and an Al layer 4A having a thickness of 500 nm are stacked in order from the first region 3a side. The bonding pad 5 has the same laminated structure as that of the first configuration example. These layers are formed by vacuum deposition. The n-side electrode 5 has a similar laminated structure.

ｐ側電極４のＲｈ層４Ｒがｐ型の第１の領域３ａに接触する。このため、ｐ側電極４を形成した後、アニールを行わない状態で、ｐ側電極４と第１の領域３ａとの間の良好なオーミック接触が得られた。その接触抵抗は５×１０−３Ωｃｍ２であった。ｐ側電極４の、第１の領域３ａに接触する面のほぼ全領域にＲｈが露出しているため、第１の構成例に比べて、より低い接触抵抗が得られている。 The Rh layer 4R of the p-side electrode 4 is in contact with the p-type first region 3a. For this reason, after forming the p-side electrode 4, good ohmic contact between the p-side electrode 4 and the first region 3a was obtained without annealing. The contact resistance was 5 × 10 −3 Ωcm 2 . Since Rh is exposed in almost the entire region of the p-side electrode 4 in contact with the first region 3a, lower contact resistance is obtained compared to the first configuration example.

ところが、この状態では、ｎ側電極５とｎ型半導体層２とはショットキ接触になり、良好なオーミック接触が得られない。ｎ側電極５を形成した後、所定の条件でアニールを行うことにより、オーミック接触を得ることができる。これは、Ａｌ層４２内のＡｌ原子がＲｈ層４Ｒ内を拡散してｎ型半導体層２まで達するためであると考えられる。例えば、アニール時間が２０秒の条件では、アニー無温度が１００℃、２００℃、及び３００℃のときにショットキ接触のままであった。アニール温度を４００℃以上にするとオーミック接触が得られた。アニール温度を４００℃、５００℃、及び６００℃としたときの接触抵抗は、それぞれ４．０×１０−５Ωｃｍ２、０．６３×１０−５Ωｃｍ２、１．８×１０−５Ωｃｍ２であった。 However, in this state, the n-side electrode 5 and the n-type semiconductor layer 2 are in Schottky contact, and good ohmic contact cannot be obtained. After the n-side electrode 5 is formed, ohmic contact can be obtained by annealing under predetermined conditions. This is presumably because Al atoms in the Al layer 42 diffuse into the Rh layer 4R and reach the n-type semiconductor layer 2. For example, when the annealing time was 20 seconds, the Schottky contact was maintained when the annealing-free temperature was 100 ° C., 200 ° C., and 300 ° C. When the annealing temperature was 400 ° C. or higher, ohmic contact was obtained. The contact resistance when the annealing temperature is 400 ° C., 500 ° C., and 600 ° C. is 4.0 × 10 −5 Ωcm 2 , 0.63 × 10 −5 Ωcm 2 , and 1.8 × 10 −5 Ωcm 2, respectively. Met.

４００℃以上の温度でアニールを行うと、ｎ側電極５をｎ型半導体層２にオーミック接触させることができるが、逆に、アニールを行うことによりｐ側電極４とｐ型の第１の領域３ａとのオーミック接触が不良になり、ショットキ接触になってしまう傾向がある。従って、ｐ側電極４及びｎ側電極５を形成した後、ｎ側電極５とｎ型半導体層２とが接触する領域のみを局所的にアニールする必要がある。局所的なアニールとして、電極材料や半導体材料によって吸収される波長域のレーザを用いたレーザアニール等を採用することができる。例えば、Ｎｄ：ＹＡＧレーザ、ＣＯ２レーザ、Ａｒ＋レーザ、エキシマレーザ等を用いることができる。 When annealing is performed at a temperature of 400 ° C. or higher, the n-side electrode 5 can be brought into ohmic contact with the n-type semiconductor layer 2. Conversely, by performing annealing, the p-side electrode 4 and the p-type first region are formed. There is a tendency that ohmic contact with 3a becomes poor and Schottky contact occurs. Therefore, after forming the p-side electrode 4 and the n-side electrode 5, it is necessary to locally anneal only the region where the n-side electrode 5 and the n-type semiconductor layer 2 are in contact. As the local annealing, laser annealing using a laser having a wavelength region absorbed by an electrode material or a semiconductor material can be employed. For example, an Nd: YAG laser, a CO 2 laser, an Ar + laser, an excimer laser, or the like can be used.

上記実施例では、ｐ側電極４が配置されるｐ型半導体層３の第１の領域３ａの上面と、ｎ側電極５が配置される第２の領域３ｂの上面との高さが揃っている。このため、ｐ側電極４の上面とｎ側電極５の上面との高さ、及びｐ側ボンディングパッド６の上面とｎ側ボンディングパッド７の上面との高さを、容易に揃えることができる。   In the above embodiment, the upper surface of the first region 3a of the p-type semiconductor layer 3 where the p-side electrode 4 is disposed and the upper surface of the second region 3b where the n-side electrode 5 is disposed are aligned. Yes. For this reason, the height of the upper surface of the p-side electrode 4 and the upper surface of the n-side electrode 5 and the height of the upper surface of the p-side bonding pad 6 and the upper surface of the n-side bonding pad 7 can be easily aligned.

また、ｎ側電極５が、ｎ型半導体層２の表面に形成された凹部９の内面に接触するため、ｎ側電極５とｎ型半導体層２との接触面積を広くすることができる。このため、両者の接触抵抗を低減することが可能になる。   Further, since the n-side electrode 5 is in contact with the inner surface of the recess 9 formed on the surface of the n-type semiconductor layer 2, the contact area between the n-side electrode 5 and the n-type semiconductor layer 2 can be increased. For this reason, it becomes possible to reduce both contact resistance.

ｐ側電極４とｐ側ボンディングパッド６、及びｎ側電極５とｎ側ボンディングパッド７が、１回のフォトリソグラフィ工程に基づくリフトオフのみでパターニングされる。このため、フォトリソグラフィ工程を削減することができる。   The p-side electrode 4 and the p-side bonding pad 6, and the n-side electrode 5 and the n-side bonding pad 7 are patterned only by lift-off based on one photolithography process. For this reason, a photolithography process can be reduced.

図３に、図１に示した半導体発光装置をサブマウント基板に実装した状態の断面図を示す。図３に示したサブマウント基板の構造について説明する。シリコン基板２０の表面上に、酸化シリコン膜２１が形成されている。酸化シリコン膜２１の一部の領域上にｐ側電極層２２が形成され、他の領域上にｎ側電極層２３が形成されている。ｐ側電極層２２及びｎ側電極層２３は、例えばアルミニウム（Ａｌ）で形成される。   FIG. 3 shows a cross-sectional view of the semiconductor light emitting device shown in FIG. 1 mounted on a submount substrate. The structure of the submount substrate shown in FIG. 3 will be described. A silicon oxide film 21 is formed on the surface of the silicon substrate 20. A p-side electrode layer 22 is formed on a partial region of the silicon oxide film 21, and an n-side electrode layer 23 is formed on another region. The p-side electrode layer 22 and the n-side electrode layer 23 are made of, for example, aluminum (Al).

ｐ側電極層２２の上にｐ側接合用電極２４が形成され、ｎ側電極層２３の上にｎ側接合用電極２５が形成されている。接合用電極２４及び２５は、Ａｕ層とＳｎ層とが交互に積層された積層構造を有する。なお、接合用電極２４及び２５をＡｕＳｎ合金で形成してもよい。   A p-side bonding electrode 24 is formed on the p-side electrode layer 22, and an n-side bonding electrode 25 is formed on the n-side electrode layer 23. The bonding electrodes 24 and 25 have a laminated structure in which Au layers and Sn layers are alternately laminated. Note that the bonding electrodes 24 and 25 may be formed of an AuSn alloy.

半導体発光装置のｐ側ボンディングパッド６がｐ側接合用電極２４に接触し、ｎ側ボンディングパッド７がｎ側接合用電極２５に接触する。接触部分で共晶化させ、両者を電気的及び機械的に結合する。ｐ側ボンディングパッド６の上面とｎ側ボンディングパッド７の上面との高さが揃っているため、サブマウント基板側の接合用電極２４及び２５の微妙な高さ調整を行う必要がない。   The p-side bonding pad 6 of the semiconductor light emitting device is in contact with the p-side bonding electrode 24, and the n-side bonding pad 7 is in contact with the n-side bonding electrode 25. Eutectic is formed at the contact portion, and both are electrically and mechanically bonded. Since the heights of the upper surface of the p-side bonding pad 6 and the upper surface of the n-side bonding pad 7 are equal, it is not necessary to perform fine height adjustment of the bonding electrodes 24 and 25 on the submount substrate side.

ｐ側電極４としてＲｈとＡｌを用いると、ｐ側電極として実用化されているＮｉを用いた場合に比べて、高い反射率を得ることができる。半導体発光装置をフリップチップボンディングによりサブマウント基板に搭載し、透明な支持基板１を通して外部に光を取り出す場合、取り出し効率を高めることができる。   When Rh and Al are used as the p-side electrode 4, a higher reflectance can be obtained as compared with the case where Ni that is put into practical use as the p-side electrode is used. When the semiconductor light emitting device is mounted on the submount substrate by flip chip bonding and light is extracted to the outside through the transparent support substrate 1, the extraction efficiency can be increased.

半導体発光装置に電流を流すと、ｐ型半導体層３の第１の領域３ａとｎ型半導体層２との間のｐｎ接合領域で発光が生じる。サファイアからなる支持基板１は、半導体層２及び３のバンドギャップに対応する波長の光に対して透明である。このため、発生した光は、支持基板１を通って外部に放射される。   When a current is passed through the semiconductor light emitting device, light emission occurs in the pn junction region between the first region 3 a of the p-type semiconductor layer 3 and the n-type semiconductor layer 2. The support substrate 1 made of sapphire is transparent to light having a wavelength corresponding to the band gap of the semiconductor layers 2 and 3. For this reason, the generated light is emitted to the outside through the support substrate 1.

上記実施例では、図１に示したｐ側電極４とｎ側電極５とを同時に成膜したが、別々に成膜してもよい。この場合には、リフトオフ法を利用した真空蒸着により一方の電極を形成した後、さらにリフトオフ法を利用した真空蒸着により他方の電極を形成する。別々に形成すると、フォトリソグラフィ及び成膜工程が増えるが、ｐ型半導体及びｎ型半導体の各々にオーミック接触しやすい最適の材料を選択することができる。   In the above embodiment, the p-side electrode 4 and the n-side electrode 5 shown in FIG. 1 are formed simultaneously, but may be formed separately. In this case, after forming one electrode by vacuum deposition using the lift-off method, the other electrode is formed by vacuum deposition using the lift-off method. When formed separately, the number of photolithography and film formation steps increases, but an optimal material that can easily make ohmic contact with each of the p-type semiconductor and the n-type semiconductor can be selected.

図１に示したｐ側電極４とｐ側ボンディングパッド６との間、及びｎ側電極５とｎ側ボンディングパッド７との間に、反射層を挿入してもよい。反射層は、ｐｎ接合部分で発光した光を支持基板１側に向けて反射し、出射効率を高める。反射層の材料として、例えば、Ａｌ、Ａｇ、Ｒｈ、Ｉｒ、Ｐｔ等を用いることができる。   A reflective layer may be inserted between the p-side electrode 4 and the p-side bonding pad 6 and between the n-side electrode 5 and the n-side bonding pad 7 shown in FIG. The reflective layer reflects the light emitted at the pn junction portion toward the support substrate 1 side, and improves the emission efficiency. As the material of the reflective layer, for example, Al, Ag, Rh, Ir, Pt, or the like can be used.

上記実施例では、半導体発光装置をサブマウント基板に実装する場合を例にとって説明したが、他の半導体装置をサブマウント基板に実装する場合にも、上記実施例の構成を適用することができる。   Although the case where the semiconductor light emitting device is mounted on the submount substrate has been described as an example in the above embodiment, the configuration of the above embodiment can also be applied to the case where another semiconductor device is mounted on the submount substrate.

以上実施例に沿って本発明を説明したが、本発明はこれらに制限されるものではない。例えば、種々の変更、改良、組み合わせ等が可能なことは当業者に自明であろう。   Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

実施例による半導体発光装置の断面図である。It is sectional drawing of the semiconductor light-emitting device by an Example. （２Ａ）及び（２Ｂ）は、それぞれｐ側電極の第１の構成例及び第２の構成例を示す断面図である。(2A) and (2B) are sectional views showing a first configuration example and a second configuration example of the p-side electrode, respectively. 実施例による半導体発光装置をサブマウント基板に実装した状態の断面図である。It is sectional drawing of the state which mounted the semiconductor light-emitting device by the Example in the submount board | substrate. 従来の半導体発光装置の断面図である。It is sectional drawing of the conventional semiconductor light-emitting device.

符号の説明Explanation of symbols

１ 支持基板
２ ｎ型半導体層
３ ｐ型半導体層
４ ｐ側電極
５ ｎ側電極
６ ｐ側ボンディングパッド
７ ｎ側ボンディングパッド
８ 溝
９ 凹部
２０ シリコン基板
２１ 酸化シリコン膜
２２ ｐ側電極層
２３ ｎ側電極層
２４ ｐ側接合用電極
２５ ｎ側接合用電極 1 support substrate 2 n-type semiconductor layer 3 p-type semiconductor layer 4 p-side electrode 5 n-side electrode 6 p-side bonding pad 7 n-side bonding pad 8 groove 9 recess 20 silicon substrate 21 silicon oxide film 22 p-side electrode layer 23 n-side Electrode layer 24 p-side bonding electrode 25 n-side bonding electrode

Claims (8)

支持基板と、
前記支持基板上に形成され、第１導電型の半導体からなる第１の半導体層と、
前記第１の半導体層の上に形成され、前記第１導電型とは逆の第２導電型の半導体からなる第２の半導体層と、
前記第２の半導体層の底面まで達し、該第２の半導体層を、相互に分離された第１の領域と第２の領域とに区分する溝と、
前記第２の半導体層の第１の領域上に形成された第１の電極と、
前記第２の半導体層の第２の領域上から、前記溝の底面に表れた前記第１の半導体層の表面までを連続的に覆う第２の電極と
を有し、前記第１の半導体層及び第２の半導体層が、Ｖ族元素として窒素を含むＩＩＩ−Ｖ族化合物半導体で形成され、前記第１の電極の、前記第２の半導体層に接する面と、前記第２の電極の、前記第１の半導体層及び第２の半導体層に接する面とが、同一の金属材料で形成されている半導体装置。 A support substrate;
A first semiconductor layer formed on the support substrate and made of a first conductivity type semiconductor;
A second semiconductor layer formed on the first semiconductor layer and made of a semiconductor of a second conductivity type opposite to the first conductivity type;
A groove that reaches the bottom surface of the second semiconductor layer and divides the second semiconductor layer into a first region and a second region separated from each other;
A first electrode formed on a first region of the second semiconductor layer;
A second electrode that continuously covers from the second region of the second semiconductor layer to the surface of the first semiconductor layer that appears on the bottom surface of the groove, and the first semiconductor layer And the second semiconductor layer is formed of a III-V group compound semiconductor containing nitrogen as a group V element, the surface of the first electrode in contact with the second semiconductor layer, and the second electrode, A semiconductor device in which a surface in contact with the first semiconductor layer and the second semiconductor layer is formed of the same metal material. さらに、前記溝の底面に形成された凹部を有し、前記第２の電極が、前記凹部の内面を覆い、前記支持基板が、前記第１の半導体層及び第２の半導体層のバンドギャップに対応する波長の光に対して透明である請求項１に記載の半導体装置。   Furthermore, it has a recess formed in the bottom surface of the groove, the second electrode covers the inner surface of the recess, and the support substrate has a band gap between the first semiconductor layer and the second semiconductor layer. The semiconductor device according to claim 1, wherein the semiconductor device is transparent to light of a corresponding wavelength. 前記第１の電極及び第２の電極の、前記第１の半導体層及び第２の半導体層に接触する面が、該第１の半導体層とオーミック接触する金属からなる領域と、該第２の半導体層とオーミック接触する他の金属からなる領域とを含む請求項１または２に記載の半導体装置。   A region of the first electrode and the second electrode in contact with the first semiconductor layer and the second semiconductor layer, a region made of a metal in ohmic contact with the first semiconductor layer, and the second electrode The semiconductor device according to claim 1, further comprising a region made of another metal that is in ohmic contact with the semiconductor layer. 前記第１の電極の、前記第２の半導体層に接する面と、前記第２の電極の、前記第１の半導体層及び第２の半導体層に接する面とを形成する金属材料が、Ｒｈ及びＡｌを含む請求項１〜３のいずれかに記載の半導体装置。   A metal material that forms a surface of the first electrode in contact with the second semiconductor layer and a surface of the second electrode in contact with the first semiconductor layer and the second semiconductor layer is Rh and The semiconductor device according to claim 1, comprising Al. 支持基板上に、第１導電型の第１の半導体層を形成する工程と、
前記第１の半導体層の上に、前記第１導電型とは逆の第２導電型の第２の半導体層を形成する工程と、
前記第２の半導体層に、少なくとも該第２の半導体層の底面まで達する溝を形成し、該第２の半導体層を、相互に分離された第１の領域と第２の領域とに区分する工程と、
前記第２の半導体層の第１の領域の上に第１の電極を形成し、前記第２の領域の上面から前記溝の底面に露出している前記第１の半導体層の表面までを連続的に覆う第２の電極を形成する工程と
を有し、前記第１の電極及び第２の電極を形成する工程において、両者を同時に成膜する半導体装置の製造方法。 Forming a first semiconductor layer of a first conductivity type on a support substrate;
Forming a second semiconductor layer of a second conductivity type opposite to the first conductivity type on the first semiconductor layer;
A groove reaching at least the bottom surface of the second semiconductor layer is formed in the second semiconductor layer, and the second semiconductor layer is divided into a first region and a second region separated from each other. Process,
A first electrode is formed on a first region of the second semiconductor layer, and continuous from the upper surface of the second region to the surface of the first semiconductor layer exposed on the bottom surface of the groove. Forming a second electrode that covers the first electrode, and forming the first electrode and the second electrode in the step of forming the first electrode and the second electrode at the same time. 前記第１の電極及び第２の電極を形成する工程が、
前記第１の半導体層及び第２の半導体層の一方にオーミック接触する金属を、露出表面全面を被覆しない厚さだけ堆積させる工程と、
その後、前記第１の半導体層及び第２の半導体層の他方にオーミック接触する他の金属を堆積させる工程とを含む請求項５に記載の半導体装置の製造方法。 Forming the first electrode and the second electrode;
Depositing a metal in ohmic contact with one of the first semiconductor layer and the second semiconductor layer to a thickness that does not cover the entire exposed surface;
And then depositing another metal in ohmic contact with the other of the first semiconductor layer and the second semiconductor layer. 前記第１の電極及び第２の電極を形成する工程が、
Ｒｈ層を堆積させる工程と、
前記Ｒｈ層の上にＡｌ層を堆積させる工程と、
前記第１の半導体層がｎ型である場合には前記第２の電極と第１の半導体層との接触部分を局所的にアニールし、前記第２の半導体層がｎ型である場合には前記第１の電極と前記第２の半導体層との接触部分を局所的にアニールすることによって、オーミック接触を得る工程と
を含む請求項５に記載の半導体装置の製造方法。 Forming the first electrode and the second electrode;
Depositing an Rh layer;
Depositing an Al layer on the Rh layer;
When the first semiconductor layer is n-type, the contact portion between the second electrode and the first semiconductor layer is locally annealed, and when the second semiconductor layer is n-type The method of manufacturing a semiconductor device according to claim 5, further comprising: obtaining ohmic contact by locally annealing a contact portion between the first electrode and the second semiconductor layer. さらに、前記溝の底面に凹部を形成する工程を含み、前記第２の電極を形成する工程において、該第２の電極が前記凹部の内面を覆うように該第２の電極を形成する請求項５〜７のいずれかに記載の半導体装置の製造方法。   The method further includes the step of forming a recess in the bottom surface of the groove, wherein in the step of forming the second electrode, the second electrode is formed so as to cover the inner surface of the recess. The manufacturing method of the semiconductor device in any one of 5-7.
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