JP2007201166A

JP2007201166A - Redundancy repair method for semiconductor integrated circuit device

Info

Publication number: JP2007201166A
Application number: JP2006017842A
Authority: JP
Inventors: Hideaki Mizumura; 秀明水村
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 2006-01-26
Filing date: 2006-01-26
Publication date: 2007-08-09

Abstract

<P>PROBLEM TO BE SOLVED: To carry out redundancy repair by reliably detecting a half-short-circuit fault or a half-open-circuit fault, which is not detected in a conventional manner, concerning a process for inspecting a semiconductor integrated circuit device. <P>SOLUTION: The semiconductor integrated circuit device is constituted with the use of a redundancy repair method so as to allow a circuit 104 to be inspected and a redundant circuit 105, both of which have the same function to be respectively and individually connected to power sources VS1(101) and VS2(102). Then an abnormal current detecting circuit 106 measures still power source current in the respective power sources VS1, VS2. When the measurement value of the still power source current in the circuit 104 to be inspected is abnormal, the fault is determined based on a fact that the still power source current is made to flow more compared with a normal standard value or the redundant circuit 105 when the half-open-circuit fault or the half-short-circuit fault exists in the circuit 104 to be inspected. A power source supply route is disconnected with respect to the circuit 104 to be inspected, which is determined to have the fault, with the use of a fuse circuit 107, so that replacement is performed in the redundant circuit 105. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体集積回路装置の冗長救済方法に関し、特に半ショート故障や半オープン故障を確実に検出して冗長救済を可能にする技術に関する。 The present invention relates to a redundancy repair method for a semiconductor integrated circuit device, and more particularly, to a technique that enables redundant repair by reliably detecting a half short failure or a half open failure.

従来、半導体集積回路装置の検査においては、機能（ファンクション）テストを実施することにより縮退故障、オープン故障、ショート故障を検出し、冗長救済可能な故障が存在する場合は、故障判定した回路をあらかじめ用意してある冗長救済回路と置換することで救済を実現している。冗長救済回路との置換方法としては、レーザや電圧の印加によりヒューズをカットする方法などがある。 Conventionally, in the inspection of semiconductor integrated circuit devices, stuck-at faults, open faults and short-circuit faults are detected by performing function tests. The repair is realized by replacing the prepared redundant repair circuit. As a replacement method with the redundant relief circuit, there is a method of cutting a fuse by applying a laser or a voltage.

特にメモリとロジックが混在したシステムＬＳＩにおいては、通常ＤＲＡＭにはあらかじめ冗長メモリセルが準備されているが、ロジック部については冗長ロジック部が搭載されていない。その不良救済を可能にするために、メモリに複数のロジック部を接続し、その１つのみを選択し、他のロジック部を切り離すフューズ回路などを備えたものがある。拡散工程後にロジック部を選択することにより、不良ロジック部を切り離して歩留まりを向上させることができる（例えば、特許文献１参照）。 In particular, in a system LSI in which memory and logic are mixed, a redundant memory cell is usually prepared in advance in a DRAM, but a redundant logic part is not mounted on a logic part. In order to make it possible to repair the defect, there are some which include a fuse circuit that connects a plurality of logic units to a memory, selects only one of them, and disconnects the other logic units. By selecting the logic part after the diffusion step, the defective logic part can be separated and the yield can be improved (for example, see Patent Document 1).

また、メモリの冗長救済を行うための不良メモリセルの発見を容易にする手法として、メモリセル電源配線を半導体記憶装置全体で利用される電源線から分離してメモリマット毎に個別化し、このメモリセル電源配線を選択的にメモリセル電流測定用の第２の電源配線に接続し、そこに種々の電圧を印加したときの電流を測定することにより、メモリブロック内のＤＣ電流不良内容を解析可能にし、効率的にメモリセルの欠陥救済を施すものがある（例えば、特許文献２参照）。
特開２００４−４８６１８号公報特許第３２２６４２２号公報 Further, as a technique for facilitating the discovery of defective memory cells for performing redundant memory repair, the memory cell power supply wiring is separated from the power supply lines used in the entire semiconductor memory device, and is individualized for each memory mat. By selectively connecting the cell power supply wiring to the second power supply wiring for memory cell current measurement and measuring the current when various voltages are applied to it, the DC current failure contents in the memory block can be analyzed In some cases, memory cell defect repair is efficiently performed (see, for example, Patent Document 2).
JP 2004-48618 A Japanese Patent No. 3226422

しかしながら、従来の半導体集積回路装置の検査では、縮退故障、オープン故障、ショート故障チップの救済は可能だが、半ショート故障や半オープン故障のあるチップを確実に検出することはできず、後工程に行われる静止電源電流テストにおいて不良チップとして判定されていた。その結果、冗長救済可能な半ショート故障や半オープン故障チップが不良品として扱われ、歩留向上の障害となっていた。また、従来の半導体集積回路装置の冗長救済方法では、検査工程が別途必要であるために検査時間が増加し、専用の検査装置が別途必要であるために検査コストが増加するという問題があった。 However, conventional semiconductor integrated circuit device inspections can repair stuck-at faults, open faults, and short fault chips, but cannot reliably detect chips with half-short faults or half-open faults. It was determined as a defective chip in the quiescent power supply current test. As a result, half-short faults and half-open fault chips that can be redundantly remedied are treated as defective products, which is an obstacle to yield improvement. Further, the conventional redundancy repair method for a semiconductor integrated circuit device has a problem that inspection time is increased because a separate inspection process is required, and inspection cost is increased because a dedicated inspection device is required separately. .

本発明は、半導体集積回路装置の検査工程において、半ショート故障や半オープン故障を確実に検出して冗長救済を可能にする半導体集積回路装置の冗長救済方法を提供することを目的とする。 SUMMARY OF THE INVENTION An object of the present invention is to provide a redundant relief method for a semiconductor integrated circuit device capable of reliably detecting a half short failure and a half open failure in a semiconductor integrated circuit device inspection process and enabling redundancy relief.

本発明の冗長救済方法は、半導体集積回路装置に搭載された同一機能を有する被検査回路と冗長回路とがそれぞれ個別の電源に接続され、前記個別の電源における静止電源電流の測定値が異常であった場合に被検査回路を故障と判定し、故障と判定された被検査回路を冗長回路で置換するものである。上記構成によれば、被検査回路に半オープン故障や半ショート故障があった場合は静止電源電流が通常より多く流れるため、個別の電源における静止電源電流の測定値の異常を被検査回路の故障と判定することで、半ショート故障や半オープン故障を確実に検出して冗長救済を行うことが可能になる。 According to the redundant relief method of the present invention, a circuit to be inspected and a redundant circuit having the same function mounted on a semiconductor integrated circuit device are connected to individual power supplies, and the measured value of the quiescent power supply current in the individual power supply is abnormal. In such a case, the circuit to be inspected is determined to be faulty, and the circuit to be inspected determined to be faulty is replaced with a redundant circuit. According to the above configuration, if the circuit under test has a half open failure or a half short circuit failure, the quiescent power supply current flows more than usual. This makes it possible to reliably detect a half short failure or a half open failure and perform redundancy relief.

さらに本発明は、上記冗長救済方法において、被検査回路と冗長回路とがそれぞれ個別の接地に接続され、前記個別の電源と前記個別の接地との全ての組合せにおいて静止電源電流の測定を行うものである。上記構成によれば、個別の電源と個別の接地との全ての組合せにおいて静止電源電流の測定を行うため、個別の電源を増加させることなく検査対象回路と冗長回路を増やすことが可能となる。 Furthermore, the present invention provides the above redundancy remedy method in which the circuit under test and the redundant circuit are connected to separate grounds, and the static power supply current is measured in all combinations of the separate power supplies and the separate grounds. It is. According to the above configuration, the quiescent power supply current is measured in all combinations of individual power supplies and individual grounds, so that it is possible to increase the number of inspection target circuits and redundant circuits without increasing individual power supplies.

また本発明の半導体集積回路装置は、被検査回路と、冗長回路と、個別の電源の供給手段と、被検査回路を冗長回路で置換する冗長救済手段とを搭載し、上記冗長救済方法を実施可能に構成されたものである。上記構成によれば、半導体集積回路装置の個別の電源における静止電源電流の測定値の異常を被検査回路の故障と判定することで、半ショート故障や半オープン故障を確実に検出して冗長救済を行うことができる。 The semiconductor integrated circuit device according to the present invention includes a circuit to be tested, a redundant circuit, an individual power supply unit, and a redundant repair unit that replaces the circuit to be tested with a redundant circuit, and implements the above redundant repair method. It is configured to be possible. According to the above configuration, it is possible to reliably detect a half short-circuit failure or a half-open failure by determining an abnormality in the measured value of the quiescent power supply current in the individual power source of the semiconductor integrated circuit device as a failure of the circuit to be inspected. It can be performed.

さらに本発明は、上記構成の半導体集積回路装置において、複数の被検査回路に対して１個の冗長回路を対応させて構成されたものである。上記構成によれば、冗長回路を減らしてチップ面積を削減することができる。２個以上の被検査回路が故障と判定された場合は、冗長救済を行わず不良品扱いとする。 Further, according to the present invention, in the semiconductor integrated circuit device having the above-described configuration, one redundant circuit is associated with a plurality of circuits to be inspected. According to the above configuration, the redundant circuit can be reduced and the chip area can be reduced. When two or more circuits to be inspected are determined to be faulty, they are treated as defective products without performing redundancy relief.

さらに本発明は、上記構成の半導体集積回路装置において、静止電源電流を測定して測定値の異常を判定する異常電流検出回路を搭載したものである。さらに本発明は、上記構成の半導体集積回路装置において、異常電流検出回路に静止電源電流の測定値と比較する規格電流回路を備えたものである。上記構成によれば、静止電源電流の測定値と比較する規格電流回路を備えた異常電流検出回路を内部に搭載することにより、チップ面積は増加するが、外部の異常電流検出手段を用意する必要がなく、チップ単体で冗長救済を行うことが可能となる。 Further, according to the present invention, the semiconductor integrated circuit device having the above-described configuration is equipped with an abnormal current detection circuit that measures a quiescent power supply current and determines an abnormality in a measured value. Further, according to the present invention, in the semiconductor integrated circuit device configured as described above, the abnormal current detection circuit is provided with a standard current circuit for comparing with a measured value of the quiescent power supply current. According to the above configuration, an abnormal current detection circuit having a standard current circuit for comparison with a measured value of the quiescent power supply current is mounted inside, thereby increasing the chip area, but it is necessary to prepare an external abnormal current detection means Therefore, it becomes possible to carry out redundant relief with a single chip.

さらに本発明は、上記構成の半導体集積回路装置において、冗長救済手段としてヒューズ回路を用いたものである。上記構成によれば、故障と判定された被検査回路に対する電源供給経路をヒューズ回路を用いて切断し、冗長回路で置換することができるため、容易に冗長救済を行うことができる。 Furthermore, according to the present invention, a fuse circuit is used as a redundancy relief means in the semiconductor integrated circuit device having the above configuration. According to the above configuration, the power supply path to the circuit to be inspected determined to be faulty can be disconnected using the fuse circuit and replaced with the redundant circuit, so that redundant relief can be easily performed.

さらに本発明は、上記構成の半導体集積回路装置において、個別の電源における被検査回路と冗長回路の静止電源電流の測定値を比較する手段を備え、静止電源電流の測定値が大きい方の回路に対する電源供給経路を切断するものである。上記構成によれば、異常電流ではないが電流値の大きい回路に対してヒューズ回路を用いて電源供給経路を切断し、全体を低消費電力にすることができる。 Furthermore, the present invention provides a semiconductor integrated circuit device having the above-described configuration, comprising means for comparing measured values of the quiescent power supply current of the circuit under test and the redundant circuit in individual power supplies, for the circuit having the larger measured value of the quiescent power supply current. The power supply path is cut off. According to the above configuration, the power supply path can be cut using a fuse circuit for a circuit that is not an abnormal current but has a large current value, and the entire power consumption can be reduced.

さらに本発明は、上記構成の半導体集積回路装置において、冗長救済手段としてセレクタ回路等の接続切り換え手段を用いたものである。上記構成によれば、セレクタ回路等の接続切り換え手段により、故障と判定された被検査回路を冗長回路で置換することができるため、低消費電力にすることはできないが、より容易に冗長救済を行うことができる。 Further, according to the present invention, in the semiconductor integrated circuit device having the above configuration, connection switching means such as a selector circuit is used as redundancy relief means. According to the above configuration, since the circuit under test determined to be faulty can be replaced with a redundant circuit by the connection switching means such as the selector circuit, it is not possible to reduce the power consumption, but it is possible to easily repair the redundancy. It can be carried out.

さらに本発明は、上記構成の半導体集積回路装置において、故障と判定した被検査回路を冗長救済手段が自動的に冗長回路で置換するテストモードを備えたたものである。上記構成によれば、半導体集積回路装置をテストモードにすることにより、冗長救済手段により自動的に冗長救済が実施されるため、テスト時間を短縮し、テストコストを削減することができる。 The present invention further includes a test mode in which the redundant repair means automatically replaces the circuit under test determined to be faulty in the semiconductor integrated circuit device configured as described above. According to the above configuration, by setting the semiconductor integrated circuit device in the test mode, the redundant repair is automatically performed by the redundant repair means, so that the test time can be shortened and the test cost can be reduced.

本発明によれば、機能テストでは確実に検出することができなかった半オープン故障や半ショート故障を確実に検出して救済することが可能となる。これにより、従来は不良チップとして扱っていたものが救済処理され、歩留向上の効果が得られる。また、静止電源電流測定と異常検出を自動的に行うことにより、別工程での救済処理が不要となり、テスト時間を短縮し、テストコストを削減する効果が得られる。 According to the present invention, it is possible to reliably detect and relieve a half-open failure or a half-short failure that could not be reliably detected by the function test. As a result, what was conventionally handled as a defective chip is relieved, and the effect of yield improvement is obtained. Further, by automatically measuring the quiescent power supply current and detecting the abnormality, the relief process in a separate process becomes unnecessary, and the test time can be shortened and the test cost can be reduced.

（実施の形態１）
図１は本発明の実施の形態１に係る冗長救済方法を示す半導体集積回路装置の構成図である。図１において、１０１と１０２はそれぞれ半導体検査装置などから入力される個別の電源ＶＳ１とＶＳ２、１０３は接地ＶＳＳ、１０４は検査対象回路Ａ、１０５は検査対象回路Ａ１０４と同等の機能を持つ冗長回路Ｂ、１０６は検査対象回路Ａ１０４と冗長回路Ｂ１０５の静止電源電流を個別に測定し検査対象回路Ａ１０４の異常電流を検出する異常電流検出回路、１０７は異常電流検出回路１０６の結果から検査対象回路Ａ１０４と冗長回路Ｂ１０５を置き換えるヒューズボックスである。 (Embodiment 1)
FIG. 1 is a configuration diagram of a semiconductor integrated circuit device showing a redundancy repair method according to Embodiment 1 of the present invention. In FIG. 1, reference numerals 101 and 102 denote individual power sources VS1 and VS2 input from a semiconductor inspection apparatus or the like, 103 denotes a ground VSS, 104 denotes an inspection target circuit A, and 105 denotes a redundant circuit having the same function as the inspection target circuit A104. B and 106 are abnormal current detection circuits that individually detect the quiescent power supply currents of the inspection target circuit A104 and the redundant circuit B105 and detect abnormal currents of the inspection target circuit A104, and 107 is an inspection target circuit A104 based on the result of the abnormal current detection circuit 106. The fuse box replaces the redundant circuit B105.

検査対象回路Ａ１０４に半オープン故障や半ショート故障があった場合は、静止電源電流が通常規格値や冗長回路Ｂ１０５より多く流れる。この原理により、異常電流検出回路１０６で静止電源電流値を測定し、電流が通常規格値や冗長回路Ｂ１０５より多く流れた場合に冗長救済が必要と判定し、ヒューズボックス１０７においてフューズを切断することにより救済を行う。 When there is a half open fault or a half short fault in the circuit A104 to be inspected, the quiescent power supply current flows more than the normal standard value or the redundant circuit B105. Based on this principle, the quiescent power supply current value is measured by the abnormal current detection circuit 106, and when the current flows more than the normal standard value or the redundant circuit B105, it is determined that redundant relief is necessary, and the fuse is disconnected in the fuse box 107. Relief by

本実施の形態によれば、検査対象回路の静止電源電流が異常電流となった場合に異常検出信号を出力し、冗長回路を選択するように異常検出信号を用いてヒューズを切断することにより、冗長救済を自動的に行うことができる。 According to the present embodiment, when the static power supply current of the circuit to be inspected becomes an abnormal current, an abnormality detection signal is output, and the fuse is cut using the abnormality detection signal so as to select the redundant circuit, Redundant relief can be performed automatically.

図４は異常電流検出回路１０６の構成例を示す図である。図４において、１２１は静止電源電流検査により冗長救済を実施するテストモード、１２２はテストモードでオンになるスイッチ、１２３は静止電源電流を異常と判定する検査規格電流、１２４は検査対象回路の静止電源電流値と検査規格電流１２３を比較する比較器、１２５はヒューズの切断に必要な電圧値に変換するレベルシフタ、１０８は冗長回路を有効にするヒューズである。 FIG. 4 is a diagram illustrating a configuration example of the abnormal current detection circuit 106. In FIG. 4, 121 is a test mode in which redundancy relief is performed by a quiescent power supply current test, 122 is a switch that is turned on in the test mode, 123 is a test standard current that determines that the quiescent power supply current is abnormal, and 124 is a quiesce of the circuit to be inspected A comparator for comparing the power supply current value with the inspection standard current 123, 125 is a level shifter for converting the voltage value to a voltage required for cutting the fuse, and 108 is a fuse for enabling the redundant circuit.

このような異常電流検出回路の構成により、冗長救済を実施するテストモード以外ではヒューズを切断することがなく、テストモードでは静止電源電流の測定値が検査規格電流値より大きい場合に、自動的にヒューズの切断を行い冗長救済を実施することができる。 With this configuration of the abnormal current detection circuit, the fuse is not blown except in the test mode where redundancy relief is performed, and in the test mode, when the measured value of the quiescent power supply current is larger than the inspection standard current value, it is automatically Redundant relief can be performed by cutting the fuse.

図５は異常電流検出回路１０６の他の構成例を示す図であり、図４の比較回路１２４を検査対象回路Ａ１０４または冗長回路Ｂ１０５を選択する選択回路１２６に代えたものである。このように構成することにより、異常電流ではないが電流値の大きい回路に対してヒューズを切断し、全体を低消費電力にすることができる。 FIG. 5 is a diagram illustrating another configuration example of the abnormal current detection circuit 106, in which the comparison circuit 124 in FIG. 4 is replaced with a selection circuit 126 that selects the circuit A104 to be inspected or the redundant circuit B105. With this configuration, it is possible to cut the fuse for a circuit having a large current value but not an abnormal current, thereby reducing the overall power consumption.

図６はヒューズボックス１０７をデータ蓄積回路１０９で置き換えた構成を示す図である。データ蓄積回路１０９は異常電流検出回路１０６で異常となった検査対象回路の情報を保存する回路である。その情報をフラッシュメモリや初期化メモリに品種個別に保有しセレクタ回路切り換え等を行うことで、ヒューズボックス１０７を用いずに冗長救済を行うことが可能である。 FIG. 6 is a diagram showing a configuration in which the fuse box 107 is replaced with a data storage circuit 109. The data storage circuit 109 is a circuit that stores information on the circuit to be inspected that has become abnormal in the abnormal current detection circuit 106. By storing the information in the flash memory or the initialization memory for each product type and switching the selector circuit, it is possible to perform redundancy relief without using the fuse box 107.

図７は本発明の冗長救済方法を実施した半導体集積回路装置の組立後を示した図である。図７において、１３０は組立後のチップ、１３１はＶＳ１用の電源端子、１３２はＶＳ２用の電源端子、１３３は接地端子である。検査対象回路Ａ１０４が不良の場合は、ＶＳ１用電源端子１３１に電源１０１のＰＡＤの配線をしないことやＰＡＤを生成しないことにより、不良な回路に電源が供給されなくなるため消費電力の低減が可能になる。 FIG. 7 is a view showing a semiconductor integrated circuit device after the redundant relief method according to the present invention is assembled. In FIG. 7, 130 is a chip after assembly, 131 is a power supply terminal for VS1, 132 is a power supply terminal for VS2, and 133 is a ground terminal. If the circuit A104 to be inspected is defective, power is not supplied to the defective circuit by not wiring the PAD of the power supply 101 to the VS1 power supply terminal 131 or by not generating the PAD, so that power consumption can be reduced. Become.

図８は本発明の冗長救済方法を実施する半導体集積回路装置において、異常電流検出回路１０６をチップ１３０の外部に置く構成とした図である。図８において、１３４は静止電源電流を測定するための各電源の電流値確認用端子、１３５は異常検出回路１０６の結果によりヒューズ切断信号を入力する端子である。このように異常電流検出回路をチップの外部に移すことによりチップ面積を削減することが可能である。 FIG. 8 is a diagram showing a configuration in which the abnormal current detection circuit 106 is placed outside the chip 130 in the semiconductor integrated circuit device that implements the redundancy remedy method of the present invention. In FIG. 8, reference numeral 134 denotes a current value confirmation terminal for each power source for measuring the quiescent power supply current, and 135 denotes a terminal for inputting a fuse cutting signal according to the result of the abnormality detection circuit 106. Thus, the chip area can be reduced by moving the abnormal current detection circuit to the outside of the chip.

図１０は本発明の冗長救済方法における検査フロー例を示す図である。本検査フローにおいて、２０１は静止電源電流測定、２０２は静止電源電流測定結果による検査対象回路が正常か異常かの判別、２０３は検査対象回路が異常であった場合に実施する冗長救済、２０４は検査対象回路が正常であった場合の製品Ａ、２０５は検査対象回路が異常でかつ冗長救済を実施した製品Ｂである。製品Ｂは検査対象回路が異常なため冗長回路のみが使用可能であるが、製品Ａは検査対象回路も冗長回路も正常なため両方の回路が使用可能である。このような冗長救済方法により、両方の回路が使用可能な製品Ａと片方の回路のみが使用可能な製品Ｂを区別して製造することができる。 FIG. 10 is a diagram showing an example of an inspection flow in the redundancy repair method of the present invention. In this inspection flow, 201 is a quiescent power supply current measurement, 202 is a determination as to whether the inspection target circuit is normal or abnormal based on the quiescent power supply current measurement result, 203 is a redundant relief performed when the inspection target circuit is abnormal, and 204 is Products A and 205 when the circuit to be inspected is normal are products B in which the circuit to be inspected is abnormal and redundant relief has been performed. Since product B has an abnormal circuit to be inspected, only the redundant circuit can be used. However, since product A has both the circuit to be inspected and the redundant circuit normal, both circuits can be used. By such a redundant repair method, the product A that can use both circuits and the product B that can use only one circuit can be distinguished from each other.

図１１は本発明の冗長救済方法における他の検査フロー例を示す図である。本検査フローにおいては、機能検査２１２を実施する前に、まず静止電源電流測定２０１を行い、冗長救済２０３を実施することにより、機能検査後の冗長救済工程を削除し、テスト時間の短縮、テストコスト削減を図ることができる。 FIG. 11 is a diagram showing another inspection flow example in the redundancy repair method of the present invention. In this test flow, before performing the function test 212, first, the quiescent power supply current measurement 201 is performed and the redundancy repair 203 is performed, thereby eliminating the redundant repair process after the function test, reducing the test time, Cost reduction can be achieved.

（実施の形態２）
図２は本発明の実施の形態２に係る冗長救済方法を示す半導体集積回路装置の構成図である。本実施の形態は、実施の形態１の接地ＶＳＳ１０３を個別の接地ＶＳＳ１（１１１）とＶＳＳ２（１１２）に分割し、個別の電源１０１および１０２と組合せたものである。本実施の形態における他の構成要素は実施の形態１と同じであり、本実施の形態の冗長救済方法を実施した検査フローや半導体集積回路装置の組立に関する技術も実施の形態１と同じであるので、説明を省略する。このように構成することで、個別の電源を増加させることなく、検査対象回路Ａ１０４とは異なる検査対象回路Ｃ１１４と冗長回路Ｄ１１５を追加することができ、冗長救済を自動的に行う回路を増やすことが可能となる。 (Embodiment 2)
FIG. 2 is a configuration diagram of a semiconductor integrated circuit device showing a redundancy repair method according to the second embodiment of the present invention. In the present embodiment, the ground VSS 103 of the first embodiment is divided into individual ground VSS1 (111) and VSS2 (112) and combined with individual power supplies 101 and 102. The other components in the present embodiment are the same as those in the first embodiment, and the inspection flow in which the redundancy repair method of the present embodiment is implemented and the technology relating to the assembly of the semiconductor integrated circuit device are also the same as those in the first embodiment. Therefore, explanation is omitted. With this configuration, it is possible to add a test target circuit C114 and a redundant circuit D115 different from the test target circuit A104 without increasing individual power supplies, and increase the number of circuits that automatically perform redundancy relief. Is possible.

図３は図２の構成における個別の電源と個別の接地の組合せ方を示す図である。２つの電源ＶＳ１、ＶＳ２と２つの接地ＶＳＳ１、ＶＳＳ２を組合せることで、２つの検査対象回路Ａ、検査対象回路Ｃと２つの冗長回路Ｂ、冗長回路Ｄを設けることができ、検査対象回路Ａと検査対象回路Ｃの２つの回路の救済が可能になる。 FIG. 3 is a diagram showing a combination of individual power sources and individual grounds in the configuration of FIG. By combining the two power sources VS1 and VS2 and the two grounds VSS1 and VSS2, it is possible to provide two test target circuits A, a test target circuit C, two redundant circuits B, and a redundant circuit D. The test target circuit A And the circuit C to be inspected can be relieved.

図９は図２の構成における冗長回路１０５と冗長回路１１５を一つにした構成図である。図９において、１１０は異常電流検出回路１０６の測定結果を選別する異常個数検出回路である。本構成において、救済回路が１つで検査対象回路が２個以上不良となった場合は、不良フラグをたてて不良扱いにする。このように冗長回路を削減することでチップ面積を削減することができる。 FIG. 9 is a configuration diagram in which the redundant circuit 105 and the redundant circuit 115 in the configuration of FIG. 2 are combined. In FIG. 9, reference numeral 110 denotes an abnormal number detection circuit for selecting the measurement result of the abnormal current detection circuit 106. In this configuration, when one relief circuit and two or more circuits to be inspected are defective, a defect flag is set and treated as defective. Thus, the chip area can be reduced by reducing redundant circuits.

本発明の冗長救済方法は、半導体集積回路の加工技術の微細化に伴い、機能ファンクションだけでは救済しきれない半断線や半ショートの歩留りを向上させる検査に有効である。 The redundancy repair method of the present invention is effective for inspections that improve the yield of half-breaks and half-shorts that cannot be repaired only by functional functions as the processing technology of semiconductor integrated circuits is miniaturized.

本発明の実施の形態１に係る冗長救済方法を実施する半導体集積回路装置の構成を示す図。1 is a diagram showing a configuration of a semiconductor integrated circuit device that performs a redundancy repair method according to a first embodiment of the present invention. 本発明の実施の形態２に係る冗長救済方法を実施する半導体集積回路装置の構成を示す図。The figure which shows the structure of the semiconductor integrated circuit device which implements the redundant relief method which concerns on Embodiment 2 of this invention. 本発明の実施の形態２に係る冗長救済方法を実施する半導体集積回路装置における電源と接地の組合せを示す図。The figure which shows the combination of the power supply and ground in the semiconductor integrated circuit device which implements the redundant relief method which concerns on Embodiment 2 of this invention. 本発明の冗長救済方法における異常電流検出回路の構成例を示す図。The figure which shows the structural example of the abnormal current detection circuit in the redundant relief method of this invention. 本発明の冗長救済方法における異常電流検出回路の構成例を示す図。The figure which shows the structural example of the abnormal current detection circuit in the redundant relief method of this invention. 本発明の冗長救済方法における異常電流検出回路のヒューズボックスをデータ蓄積回路で置き換えた構成を示す図。The figure which shows the structure which replaced the fuse box of the abnormal current detection circuit with the data storage circuit in the redundancy relief method of this invention. 本発明の冗長救済方法を実施した半導体集積回路装置の製品組立図。The product assembly drawing of the semiconductor integrated circuit device which implemented the redundant relief method of this invention. 本発明の冗長救済方法を実施する半導体集積回路装置において異常電流検出回路をチップの外部に置く構成とした図。1 is a diagram showing a configuration in which an abnormal current detection circuit is placed outside a chip in a semiconductor integrated circuit device that implements the redundancy repair method of the present invention. FIG. 本発明の実施の形態２に係る冗長救済方法を実施する半導体集積回路装置において複数の検査対象回路に１つの救済回路を設けた構成を示す図。The figure which shows the structure which provided one relief circuit in the some test object circuit in the semiconductor integrated circuit device which implements the redundancy relief method which concerns on Embodiment 2 of this invention. 本発明の冗長救済方法を実施した半導体集積回路装置の検査フロー例を示す図。The figure which shows the test | inspection flow example of the semiconductor integrated circuit device which implemented the redundancy relief method of this invention. 本発明の冗長救済方法を実施した半導体集積回路装置の検査フロー例を示す図。The figure which shows the test | inspection flow example of the semiconductor integrated circuit device which implemented the redundancy relief method of this invention.

符号の説明Explanation of symbols

１０１第１の個別電源ＶＳ１
１０２第２の個別電源ＶＳ２
１０３共通接地ＶＳＳ
１０４検査対象回路Ａ
１０５冗長回路Ｂ
１０６異常電流検出回路
１０７ヒューズボックス
１０８ヒューズ
１０９データ蓄積回路
１１０異常個数検出回路
１１１第１の個別接地ＶＳＳ１
１１２第２の個別接地ＶＳＳ２
１１４検査対象回路Ｃ
１１５冗長回路Ｄ
１２１冗長救済実施の静止電源電流テストモード
１２２テストモード時にオンになるスイッチ
１２３規格電流
１２４比較回路
１２５レベルシフタ
１２６選択回路
１３１ＶＳ１用電源端子
１３２ＶＳ２用電源端子
１３３ＶＳＳ接地端子
１３４電流値出力端子
１３５異常電流結果入力端子 101 First individual power supply VS1
102 Second individual power supply VS2
103 Common ground VSS
104 Circuit A to be inspected
105 Redundant circuit B
106 Abnormal current detection circuit 107 Fuse box 108 Fuse 109 Data storage circuit 110 Abnormal number detection circuit 111 First individual ground VSS1
112 Second individual ground VSS2
114 Circuit C to be inspected
115 Redundant circuit D
121 Static power supply current test mode for performing redundancy relief 122 Switch turned on in test mode 123 Standard current 124 Comparison circuit 125 Level shifter 126 Selection circuit 131 Power supply terminal for VS1 132 Power supply terminal for VS2 133 VSS ground terminal 134 Current value output terminal 135 Abnormal Current result input terminal

Claims

被検査回路と前記被検査回路と同一機能を有する冗長回路とがそれぞれ個別の電源に接続された半導体集積回路装置の冗長救済方法であって、前記個別の電源における静止電源電流の測定値が異常であった場合に前記被検査回路を故障と判定し、故障と判定された前記被検査回路を前記冗長回路で置換する半導体集積回路装置の冗長救済方法。 A redundant relief method for a semiconductor integrated circuit device in which a circuit under test and a redundant circuit having the same function as the circuit under test are connected to individual power supplies, respectively, and the measured value of the quiescent power supply current at the individual power supply is abnormal A redundancy remedy method for a semiconductor integrated circuit device, in which the circuit under test is determined to be faulty in the case of the failure, and the circuit under test determined to be faulty is replaced with the redundancy circuit.

前記被検査回路と前記冗長回路とがそれぞれ個別の接地に接続され半導体集積回路装置であって、前記個別の電源と前記個別の接地との全ての組合せにおいて前記静止電源電流の測定を行う請求項１記載の半導体集積回路装置の冗長救済方法。 A semiconductor integrated circuit device in which the circuit under test and the redundant circuit are respectively connected to individual grounds, and the quiescent power supply current is measured in all combinations of the individual power sources and the individual grounds. 2. A redundant relief method for a semiconductor integrated circuit device according to 1.

被検査回路と、前記被検査回路と同一機能を有する冗長回路と、前記被検査回路及び前記冗長回路にそれぞれ個別の電源を供給する手段と、前記被検査回路を前記冗長回路で置換する冗長救済手段とを備え、複数の被検査回路に対して前記冗長回路を１つ対応させて構成した半導体集積回路装置。 A circuit to be inspected, a redundant circuit having the same function as the circuit to be inspected, means for supplying individual power to the circuit to be inspected and the redundant circuit, and redundancy repair for replacing the circuit to be inspected with the redundant circuit And a semiconductor integrated circuit device configured by associating one redundant circuit with a plurality of circuits to be inspected.

前記静止電源電流を測定して測定値の異常を判定する異常電流検出回路を備える請求項３記載の半導体集積回路装置。 4. The semiconductor integrated circuit device according to claim 3, further comprising an abnormal current detection circuit that measures the quiescent power supply current and determines an abnormality in the measured value.

前記異常電流検出回路に前記静止電源電流の測定値と比較する規格電流回路を備えた請求項４記載の半導体集積回路装置。 5. The semiconductor integrated circuit device according to claim 4, wherein the abnormal current detection circuit includes a standard current circuit for comparing with the measured value of the quiescent power supply current.

前記冗長救済手段がヒューズ回路である請求項３記載の半導体集積回路装置。 4. The semiconductor integrated circuit device according to claim 3, wherein the redundancy relief means is a fuse circuit.

個別の電源における前記被検査回路と前記冗長回路の静止電源電流の測定値を比較する手段を備え、前記ヒューズ回路は前記静止電源電流の測定値が大きい方の回路に対する電源供給経路を切断するように作動する請求項６記載の半導体集積回路装置。 Means for comparing the measured value of the static power supply current of the circuit under test and the redundant circuit in an individual power supply, and the fuse circuit cuts off the power supply path to the circuit having the larger measured value of the static power supply current 7. The semiconductor integrated circuit device according to claim 6, wherein the semiconductor integrated circuit device operates.

前記冗長救済手段はセレクタ回路等の接続切り換え手段である請求項３記載の半導体集積回路装置。 4. The semiconductor integrated circuit device according to claim 3, wherein the redundancy relief means is a connection switching means such as a selector circuit.

前記冗長救済手段は故障と判定した被検査回路を前記冗長回路で置換するテストモードを備えた請求項３記載の半導体集積回路装置。 4. The semiconductor integrated circuit device according to claim 3, wherein the redundancy repair means includes a test mode in which a circuit to be inspected determined to be faulty is replaced with the redundancy circuit.