JP2007184520A - Sti技術により実現された高解像度のcmosイメージセンサのための成層型フォトダイオード - Google Patents
Sti技術により実現された高解像度のcmosイメージセンサのための成層型フォトダイオード Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims abstract description 21
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- 230000000295 complement effect Effects 0.000 claims 2
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- 238000000034 method Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000008859 change Effects 0.000 description 3
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- 238000005468 ion implantation Methods 0.000 description 1
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Abstract
【解決手段】本発明のフォトダイオードは、第1導電型の半導体層と、該記半導体層内で互いに異なる深さで形成された複数の第2導電型のドープ領域と、前記半導体層内で前記の第2導電型ドープ領域の間に形成され、フォトダイオードの空乏のための電圧の印加時に、完全に空乏されずに複数の接合キャパシタを形成する複数の第1導電型のドー領域と、前記半導体層の表面下に形成されたピニング層を備える。
【選択図】図3
Description
Claims (20)
- 第1導電型の半導体層と、
該記半導体層内で互いに異なる深さで形成された複数の第2導電型のドープ領域と、
前記半導体層内で前記の第2導電型ドープ領域の間に形成され、フォトダイオードの空乏のための電圧の印加時に、完全に空乏されずに複数の接合キャパシタを形成する複数の第1導電型のドープ領域と、
前記半導体層の表面下に形成されたピニング層と
を備えたことを特徴とするCMOSイメージセンサのピクセルのためのフォトダイオード。 - 前記第1導電型のドープ領域が、前記半導体層及び前記第2導電型のドープ領域らより相対的に高いドープ濃度を有することを特徴とする請求項1に記載のCMOSイメージセンサのピクセルのためのフォトダイオード。
- 前記複数の第2導電型ドープ領域が、前記第1導電型のドープ領域等の一方面で互いに連結されたことを特徴とする請求項1に記載のCMOSイメージセンサのピクセルのためのフォトダイオード。
- 前記第1導電型ドープ領域の一部に形成されて、前記第1導電型ドープ領域の上下部に位置する前記第2導電型ドープ領域らの相互連結を提供するカウントドープ領域をさらに含むことを特徴とする請求項1に記載のCMOSイメージセンサのピクセルのためのフォトダイオード。
- 前記カウントドープ領域とオーバーラップし形成され、前記第1導電型ドープ領域の上部及び下部に位置する前記第2導電型ドープ領域に形成される他のカウントドープ領域をさらに含むことを特徴とする請求項4に記載のCMOSイメージセンサのピクセルのためのフォトダイオード。
- 前記ピニング層が、第1導電型であることを特徴とする請求項1〜5のいずれか1項に記載のCMOSイメージセンサのピクセルのためのフォトダイオード。
- 前記第1導電型と前記の第2導電型が互いに相補的なp型またはn型であることを特徴とする請求項1〜5のいずれか1項に記載のCMOSイメージセンサのピクセルのためのフォトダイオード。
- 前記ピクセルは、4T−ピクセルであることを特徴とする請求項1〜5のいずれか1項に記載のCMOSイメージセンサのピクセルのためのフォトダイオード。
- 前記ピクセルは、3T−ピクセルであることを特徴とする請求項1〜5のいずれか1項に記載のCMOSイメージセンサのピクセルのためのフォトダイオード。
- 前記第1導電型の半導体層が、エピタキシャル層であることを特徴とする請求項1〜5のいずれか1項に記載のCMOSイメージセンサのピクセルのためのフォトダイオード。
- 第1導電型の半導体層と、
該記半導体層に局部的に形成されたSTI(shallow Trench Isolation)領域と、
前記半導体層内に形成されたピンドフォトダイオードと、
該記のピンドフォトダイオードに生成された光電荷をセンシングノードに伝達するためのトランスタゲートとを備え、
前記ピンドフォトダイオードは、
前記半導体層内で互いにことなる深さに形成された複数の第2導電型のドープ領域と、
前記半導体層内で前記の第2導電型のドープ領域の間に形成され、フォトダイオードの空乏のための電圧印加時にも完全に空乏されずに複数の接合キャパシタを形成する複数の第1導電型のドープ領域と、
前記半導体層の表面下に形成されたピニング層と
を備えたことを特徴とするCMOSイメージセンサのピクセル。 - 前記第1導電型のドープ領域が、前記半導体層及び前記第2導電型ドープ領域らより相対的に高いドープ濃度を有することを特徴とする請求項11に記載のCMOSイメージセンサのピクセル。
- 前記複数の第2導電型ドープ領域が、前記トランスファーゲートの一方のエッジ下部領域で互いに連結されたことを特徴とする請求項11に記載のCMOSイメージセンサのピクセル。
- 前記STI領域の前記半導体層の表面の下部に形成された第1導電型のフィールドストップドープ領域を更に備え、
該記フィールドストップドープ領域は、前記ピニング層及び前記の複数の第1導電型のドープ領域と互いに連結されて形成されることを特徴とする請求項11に記載のCMOSイメージセンサのピクセル。 - 前記第1導電型ドープ領域の一部に形成されて、前記第1導電型ドープ領域の上下部に位置する前記第2導電型ドープ領域らの相互連結を提供するカウントドープ領域をさらに含むことを特徴とする請求項11に記載のCMOSイメージセンサのピクセル。
- 前記カウントドープ領域とオーバーラップし形成され、前記第1導電型ドープ領域の上部及び下部に位置する前記第2導電型ドープ領域に形成される他のカウントドープ領域をさらに含むことを特徴とする請求項15に記載のCMOSイメージセンサのピクセル。
- 前記カウントドープ領域及び他のカウントドープ領域は、前記STI領域の近傍に形成されることを特徴とする請求項16に記載のCMOSイメージセンサのピクセル。
- 前記ピニング層が、第1導電形であることを特徴とする請求項11〜17のいずれか1項に記載のCMOSイメージセンサのピクセル。
- 前記第1導電型と前記第2導電型が、互いに相補的なp型またはn型であることを特徴とする請求項11〜17のいずれか1項に記載のCMOSイメージセンサのピクセル。
- 前記第1導電型の半導体層が、エピタキシャル層であることを特徴とする請求項11〜17のいずれか1項に記載のCMOSイメージセンサのピクセル。
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KR1020060038536A KR100790224B1 (ko) | 2005-12-29 | 2006-04-28 | Sti 기술로 구현된 고해상도 cmos 이미지 센서를위한 성층형 포토다이오드 |
KR10-2006-0038536 | 2006-04-28 |
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US20100044824A1 (en) | 2010-02-25 |
US8703522B2 (en) | 2014-04-22 |
JP5214116B2 (ja) | 2013-06-19 |
US8247853B2 (en) | 2012-08-21 |
US20100044812A1 (en) | 2010-02-25 |
US8120069B2 (en) | 2012-02-21 |
US7633134B2 (en) | 2009-12-15 |
US20120295386A1 (en) | 2012-11-22 |
US20070158771A1 (en) | 2007-07-12 |
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