JP2007180083A - Semiconductor chip mounting substrate and manufacturing method therefor - Google Patents

Semiconductor chip mounting substrate and manufacturing method therefor Download PDF

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JP2007180083A
JP2007180083A JP2005373791A JP2005373791A JP2007180083A JP 2007180083 A JP2007180083 A JP 2007180083A JP 2005373791 A JP2005373791 A JP 2005373791A JP 2005373791 A JP2005373791 A JP 2005373791A JP 2007180083 A JP2007180083 A JP 2007180083A
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semiconductor chip
substrate
chip mounting
back surfaces
manufacturing
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Daisuke Mizutani
大輔 水谷
Yasuhiro Yoneda
泰博 米田
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Fujitsu Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor chip mounting substrate, capable of improving mounting reliability by reducing the thermal expansion coefficient between the substrate and a semiconductor chip, and to provide a manufacturing method therefor. <P>SOLUTION: A core substrate 2 of a packaged board 10 is made of a titanium alloy having a small thermal expansion coefficient. Anode oxidation films 3 are formed on the front and rear surfaces. A plurality of through-holes 4, piercing the front and rear surfaces of the core substrate 2, are provided on the core substrate 2, and an anode oxidation films 3 is also formed on the internal wall surfaces of the through-holes. Wiring layers, having a plurality of conductor patterns 6 electrically connected with each other via the through-holes 4, are formed on the anode oxidation films 3 on the front and the rear surfaces of the core substrate 2. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

本発明は、半導体チップ搭載用基板およびその製造方法に関し、特に電子機器の回路基板に対して半導体チップを電気的に接続するための半導体チップ搭載用基板およびその製造方法に関する。   The present invention relates to a semiconductor chip mounting substrate and a manufacturing method thereof, and more particularly to a semiconductor chip mounting substrate for electrically connecting a semiconductor chip to a circuit board of an electronic device and a manufacturing method thereof.

ネットワーク機器の高速化、大容量化にともない、半導体回路素子間での配線距離を短縮して実装密度を上げることが要求されている。半導体チップを高密度に実装する方法として、従来から、パッケージ基板、あるいはマルチチップ基板などと称する半導体チップ搭載用基板が用いられてきた。半導体チップ搭載用基板は、半導体チップよりも一回り大型のコア基板と、その表面に形成された少なくとも１層のビルドアップ層を含むものであって、その表裏面には、半導体チップとの接続部、およびそれが搭載される電子機器全体の回路基板（例えば、マザーボードなど）との接続部を備えている。   As network devices increase in speed and capacity, it is required to shorten the wiring distance between semiconductor circuit elements and increase the mounting density. Conventionally, a semiconductor chip mounting substrate called a package substrate or a multi-chip substrate has been used as a method for mounting semiconductor chips at high density. The semiconductor chip mounting substrate includes a core substrate that is slightly larger than the semiconductor chip and at least one build-up layer formed on the surface thereof, and the front and back surfaces thereof are connected to the semiconductor chip. Part and a connection part with the circuit board (for example, motherboard) of the whole electronic device in which it is mounted.

こうしたシリコンチップのベアチップ実装では、シリコンチップの熱膨張係数が常温で約３．５ｐｐｍ／℃程度であって、常温で１０〜２０ｐｐｍ／℃程度のプリント基板上に直接実装されることになる。そのため、プリント基板上にチップを実装した後で封止樹脂アンダーフィルを施しても、両者の熱膨張率の差によって接続部に熱応力が発生して、回路接続の信頼性が低下していた。また、一般に半導体チップ搭載用基板は半導体チップよりも熱膨張率が大きく、半導体チップとの接合部には熱応力が発生するなど、従来から半導体回路素子の接合部が製造時の熱ストレスによって破壊に至る要因となっていた。   In such bare chip mounting of a silicon chip, the thermal expansion coefficient of the silicon chip is about 3.5 ppm / ° C. at room temperature, and it is directly mounted on a printed circuit board having about 10 to 20 ppm / ° C. at room temperature. Therefore, even if the sealing resin underfill is applied after mounting the chip on the printed circuit board, the thermal stress is generated in the connection part due to the difference in thermal expansion coefficient between the two, and the reliability of the circuit connection is lowered. . In general, a semiconductor chip mounting substrate has a higher coefficient of thermal expansion than a semiconductor chip, and thermal stress is generated at the junction with the semiconductor chip. It became a factor leading to.

一方、高周波で動作する半導体回路素子を電気的に安定化するためには、半導体回路素子とグランド電極との間での接続距離を短くして、インダクタンスを下げることが求められている。しかし、半導体チップ搭載用基板自体の面積が小さいため、その電気的な安定を得るに足るグランド電極を設置するのは困難であった。そこで、半導体回路素子のグランド接続端子をマザーボードのグランド電極と接続できる半導体チップ搭載用基板が用いられることになる。   On the other hand, in order to electrically stabilize a semiconductor circuit element operating at a high frequency, it is required to reduce the inductance by shortening the connection distance between the semiconductor circuit element and the ground electrode. However, since the area of the semiconductor chip mounting substrate itself is small, it has been difficult to install a ground electrode sufficient to obtain electrical stability. Therefore, a semiconductor chip mounting substrate that can connect the ground connection terminal of the semiconductor circuit element to the ground electrode of the motherboard is used.

ところが、その場合に半導体チップ搭載用基板は、マザーボードのグランド電極への接続インダクタンスを低減する必要から、グランド電極の並列化によってそのグランド接続端子数が増加し、かえって半導体チップ搭載用基板の実装信頼性を低下させる要因となっていた。   However, in that case, since the semiconductor chip mounting substrate needs to reduce the connection inductance to the ground electrode of the mother board, the number of ground connection terminals increases due to the parallel connection of the ground electrode. On the contrary, the mounting reliability of the semiconductor chip mounting substrate is increased. It was a factor that decreased the sex.

このような問題を解決するために、従来から金属材料表面を陽極酸化してコア基板とするために、そのコア材料としてアルミニウムを主成分とする金属を用いる技術が開発されていた（例えば、特許文献１参照。）。ここでは、アルミニウムを主成分として、酸化被膜を絶縁層として用いると共に、金属基板をグランド層として用いることで、半導体の高周波化、多機能化に伴う信号線数の増加に対して微細配線化による高密度配線で対応することが可能となり、抵抗値の小さい良質のグランド層を形成することができ、低コスト化、歩留まり向上、電気特性向上の要求を満たすものとなる。
特開平１１−２９８１０４号公報（段落番号［００１４］〜［００３４］、図１など） In order to solve such a problem, in order to anodize the surface of a metal material to form a core substrate, a technique using a metal mainly composed of aluminum as the core material has been developed (for example, patents). Reference 1). Here, aluminum is used as the main component, an oxide film is used as an insulating layer, and a metal substrate is used as a ground layer, thereby reducing the number of signal lines associated with higher frequency and multi-functionalization of semiconductors. It is possible to cope with high-density wiring, and a high-quality ground layer with a small resistance value can be formed, which satisfies the demands for cost reduction, yield improvement, and electrical property improvement.
JP-A-11-298104 (paragraph numbers [0014] to [0034], FIG. 1 etc.)

しかし、アルミニウムを主成分とする金属の熱膨張率が概ね１０数ｐｐｍ／℃以上であって、半導体回路素子の材料であるシリコン（Ｓｉ）の熱膨張率（約３ｐｐｍ／℃）との差が大きく、半導体チップと半導体チップ搭載用基板の間の熱応力が大きくなるという問題があった。   However, the coefficient of thermal expansion of a metal whose main component is aluminum is approximately 10 or more ppm / ° C., and the difference from the coefficient of thermal expansion (about 3 ppm / ° C.) of silicon (Si), which is the material of the semiconductor circuit element, is There is a problem that the thermal stress between the semiconductor chip and the semiconductor chip mounting substrate becomes large.

本発明はこのような点に鑑みてなされたものであり、半導体チップとの熱膨張率差を小さくして、実装信頼性を向上するようにした半導体チップ搭載用基板およびその製造方法を提供することを目的とする。   The present invention has been made in view of the above points, and provides a semiconductor chip mounting substrate and a manufacturing method thereof in which a difference in thermal expansion coefficient from a semiconductor chip is reduced to improve mounting reliability. For the purpose.

本発明では、上記問題を解決するために、電子機器の回路基板に対して半導体チップを電気的に接続するための半導体チップ搭載用基板において、図１に示すように、チタンを主成分とし、表裏面を貫通するスルーホール４が形成され、表裏面およびスルーホール４の内壁面に絶縁性被膜（陽極酸化膜３）が形成された金属基板（コア基板２）と、表裏面の絶縁性被膜上に配置され、スルーホール４を介して表裏面で互いに電気的に接続した複数の導体パターン６を有する配線層と、を備えたことを特徴とする半導体チップ搭載用基板１０が提供される。   In the present invention, in order to solve the above problem, in the semiconductor chip mounting substrate for electrically connecting the semiconductor chip to the circuit board of the electronic device, as shown in FIG. A metal substrate (core substrate 2) in which through holes 4 penetrating the front and back surfaces are formed, and an insulating film (anodized film 3) is formed on the front and back surfaces and the inner wall surfaces of the through holes 4, and an insulating film on the front and back surfaces There is provided a semiconductor chip mounting substrate comprising a wiring layer having a plurality of conductor patterns 6 disposed on and electrically connected to each other on the front and back surfaces through through-holes 4.

上記の構成によれば、熱膨張率の小さいチタンを主成分とする金属基板を用いたことにより、半導体チップ１と半導体チップ搭載用基板１０との熱膨張率差が小さくなる。
また、電子機器の回路基板に対して半導体チップを電気的に接続するための半導体チップ搭載用基板を製造する製造方法において、コア基板となるチタン合金の表裏面を貫通してスルーホールを形成する第１工程と、前記表裏面、および前記スルーホールの内壁面に陽極酸化によって酸化被膜を形成する第２工程と、前記スルーホール内部に導電性ペーストを充填して前記表裏面を電気的に接続可能にする第３工程と、前記表裏面でそれぞれ配線層となる少なくとも１層の導体パターンを前記酸化被膜上に形成する第４工程と、を含むことを特徴とする半導体チップ搭載用基板の製造方法が提供される。 According to said structure, the thermal expansion coefficient difference of the semiconductor chip 1 and the semiconductor chip mounting substrate 10 becomes small by using the metal substrate which has titanium with a small thermal expansion coefficient as a main component.
Further, in a manufacturing method for manufacturing a semiconductor chip mounting substrate for electrically connecting a semiconductor chip to a circuit board of an electronic device, a through hole is formed through the front and back surfaces of a titanium alloy serving as a core substrate. A first step, a second step of forming an oxide film by anodic oxidation on the front and back surfaces and the inner wall surface of the through hole, and electrically connecting the front and back surfaces by filling the through hole with a conductive paste. 3. A semiconductor chip mounting substrate comprising: a third step for enabling; and a fourth step for forming at least one conductor pattern on the oxide film on each of the front and rear surfaces as a wiring layer. A method is provided.

上記の方法によれば、コア基板として熱膨張率の小さいチタン合金を用いるので、半導体チップと半導体チップ搭載用基板との熱膨張率差が小さくなる。   According to the above method, since the titanium alloy having a small coefficient of thermal expansion is used as the core substrate, the difference in coefficient of thermal expansion between the semiconductor chip and the semiconductor chip mounting substrate is reduced.

本発明によれば、半導体チップ搭載用基板のコア基板として、チタンを主成分とする金属基板を用いることにより、そこに搭載される半導体チップとの熱膨張率差を小さくして、その接合部で発生する応力を低減できる。   According to the present invention, by using a metal substrate mainly composed of titanium as a core substrate of a semiconductor chip mounting substrate, the difference in thermal expansion coefficient from the semiconductor chip mounted thereon is reduced, and the joint portion It is possible to reduce the stress generated in.

以下、図面を参照してこの発明の実施の形態について説明する。
図１は、本実施の形態の半導体チップ搭載用基板を示す概略断面図である。
本実施の形態の半導体チップ搭載用基板（以下、パッケージ基板という。）１０には、半導体チップ１が搭載されている。パッケージ基板１０のコア基板２は、０．５ｍｍ程度の厚さを有する所定形状のチタン合金からなる金属基板であって、その表面には陽極酸化膜３が形成されている。また、コア基板２には、コア基板２の表裏面を貫通する複数のスルーホール４が形成されており、それらの内壁面にも陽極酸化膜３が形成されている。 Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a schematic cross-sectional view showing a semiconductor chip mounting substrate according to the present embodiment.
A semiconductor chip 1 is mounted on a semiconductor chip mounting substrate (hereinafter referred to as a package substrate) 10 of the present embodiment. The core substrate 2 of the package substrate 10 is a metal substrate made of a titanium alloy having a predetermined shape having a thickness of about 0.5 mm, and an anodic oxide film 3 is formed on the surface thereof. The core substrate 2 is formed with a plurality of through holes 4 penetrating the front and back surfaces of the core substrate 2, and the anodic oxide film 3 is also formed on the inner wall surfaces thereof.

パッケージ基板１０の表裏面には、樹脂材が複数積層された絶縁層５内に、陽極酸化膜３によってコア基板２と絶縁された導体パターン６が配線層としてビルドアップされている。絶縁層５内の導体パターン６は、絶縁層５毎にメッキ加工された高精度の回路配線パターンをなしており、それぞれが各配線層を貫通するビアホール７によって適宜に接続されている。   On the front and back surfaces of the package substrate 10, a conductor pattern 6 insulated from the core substrate 2 by the anodic oxide film 3 is built up as a wiring layer in an insulating layer 5 in which a plurality of resin materials are laminated. The conductor pattern 6 in the insulating layer 5 forms a high-precision circuit wiring pattern plated for each insulating layer 5, and each is appropriately connected by a via hole 7 penetrating each wiring layer.

このパッケージ基板１０には、コア基板２の表裏面で最上部に位置する導体パターン６１、６２が実装部として形成されており、図１の上方に相当する実装部では、導体パターン６１（第１の配線層）が半導体チップ１の接続端子とはんだバンプ８を介して電気的に接続されている。また、図１の下方では図示しない電子機器の回路基板（例えば、マザーボード）と接続するための導体パターン６２（第２の配線層）からなる外部電極パッドなどにより、他方の実装部が構成されている。   The package substrate 10 is formed with conductor patterns 61 and 62 positioned on the top and bottom surfaces of the core substrate 2 as mounting parts. In the mounting part corresponding to the upper part of FIG. Are electrically connected to the connection terminals of the semiconductor chip 1 via the solder bumps 8. Further, in the lower part of FIG. 1, the other mounting part is constituted by an external electrode pad made of a conductor pattern 62 (second wiring layer) for connection to a circuit board (for example, a mother board) of an electronic device (not shown). Yes.

ここで、コア基板２の表裏面を貫通するスルーホール４内には、陽極酸化膜３によってコア基板２と電気的に絶縁された状態で導電性の貫通ビア９が充填されており、この貫通ビア９によってパッケージ基板１０のコア基板２の表裏面における回路配線パターンが電気的に接続されている。   Here, conductive through vias 9 are filled in the through holes 4 penetrating the front and back surfaces of the core substrate 2 while being electrically insulated from the core substrate 2 by the anodic oxide film 3. Circuit wiring patterns on the front and back surfaces of the core substrate 2 of the package substrate 10 are electrically connected by the vias 9.

また、コア基板２の陽極酸化膜３が部分的に除去された部分があって、そこが半導体チップ１のグランド電極を構成する導体パターン６１とビアホール７によって接続されている。したがって、チタン合金のコア基板２自体をグランド層として使用することができるから、従来の絶縁層５内にビルドアップされる導体パターン６をグランド層（銅メッキベタ層）と比較して、その容積を大きくすることで、容易に抵抗値の小さい良質のグランド層が形成できる。しかも、コア基板２自体がグランド層であれば、半導体チップ１とマザーボードとの距離を近づける必要がなくなるから、コア基板２を厚くすることができ、したがって、パッケージ基板１０の変形を抑えて、寸法安定性を高めることができる。   In addition, there is a portion where the anodic oxide film 3 of the core substrate 2 is partially removed, which is connected to the conductor pattern 61 constituting the ground electrode of the semiconductor chip 1 by the via hole 7. Therefore, since the titanium alloy core substrate 2 itself can be used as the ground layer, the conductor pattern 6 built up in the conventional insulating layer 5 is compared with the ground layer (copper-plated solid layer) and its volume is reduced. By increasing the size, a high-quality ground layer having a small resistance value can be easily formed. In addition, if the core substrate 2 itself is a ground layer, it is not necessary to reduce the distance between the semiconductor chip 1 and the mother board, so that the core substrate 2 can be made thicker, and therefore, deformation of the package substrate 10 can be suppressed and the dimensions can be reduced. Stability can be increased.

なお、パッケージ基板１０の回路配線パターンを構成するビルドアップ材（導体パターン６と絶縁層５とが積層された部分）は、図１ではその厚みを誇張して示している。実際には、単位層あたり４０μｍ程度の厚さであって、通常のパッケージ基板１０では４〜５層の配線パターンが形成されることから、全体としては表裏面でそれぞれ２００〜３００μｍ程度となる。   Note that the build-up material (portion where the conductor pattern 6 and the insulating layer 5 are laminated) constituting the circuit wiring pattern of the package substrate 10 is exaggerated in FIG. Actually, each unit layer has a thickness of about 40 μm, and a normal package substrate 10 has 4 to 5 layers of wiring patterns. Therefore, the entire front and back surfaces are about 200 to 300 μm.

半導体チップ１の材料であるシリコンの熱膨張率は、約３ｐｐｍ／℃であるのに対して、回路配線パターンを構成する絶縁層５は、その熱膨張率がおよそ５０ｐｐｍ／℃の樹脂材料が用いられることから、従来では、この大きな熱膨張率差に起因して、パッケージ基板１０の加熱処理時に両者の寸法差が生じていた。したがって、従来のコア材料としてアルミニウムを主成分とする金属を用いるものでは、はんだバンプ８に熱応力が加わって、その接着性を損なうことになる。   The thermal expansion coefficient of silicon which is a material of the semiconductor chip 1 is about 3 ppm / ° C., whereas the insulating layer 5 constituting the circuit wiring pattern is made of a resin material having a thermal expansion coefficient of about 50 ppm / ° C. Therefore, conventionally, due to this large difference in coefficient of thermal expansion, a dimensional difference between the two has occurred during the heat treatment of the package substrate 10. Therefore, in the case of using a metal having aluminum as a main component as a conventional core material, thermal stress is applied to the solder bumps 8 and the adhesiveness thereof is impaired.

これに対し、本実施の形態のパッケージ基板１０では、熱膨張率が小さい（８ｐｐｍ／℃程度）チタン合金をコア基板２として用いることにより、コア基板２の両面に形成された回路配線パターンの実装面と半導体チップ１との熱膨張率差が低減され、はんだバンプ８に生じる熱応力を低減することができる。   On the other hand, in the package substrate 10 of the present embodiment, the circuit wiring pattern formed on both surfaces of the core substrate 2 is mounted by using a titanium alloy having a low coefficient of thermal expansion (about 8 ppm / ° C.) as the core substrate 2. The difference in thermal expansion coefficient between the surface and the semiconductor chip 1 is reduced, and the thermal stress generated in the solder bump 8 can be reduced.

なお、パッケージ基板１０に搭載される半導体チップ１とコア基板２の熱膨張係数をそれぞれα１，α２としたとき、一般に
α１≦α２≦１０（ｐｐｍ／℃）
であることが望ましい。したがって、コア基板２の他方の面に接続される回路基板の熱膨張係数をα３（ｐｐｍ／℃）としたとき、
α１≦α２≦α３
であることになる。 When the thermal expansion coefficients of the semiconductor chip 1 and the core substrate 2 mounted on the package substrate 10 are α1 and α2, respectively, generally α1 ≦ α2 ≦ 10 (ppm / ° C.)
It is desirable that Therefore, when the coefficient of thermal expansion of the circuit board connected to the other surface of the core substrate 2 is α3 (ppm / ° C.),
α1 ≦ α2 ≦ α3
It will be.

また、チタン合金のコア基板２は、その表面が高精度な回路配線パターンの形成に耐え得るだけの平坦性を有すると共に、半導体チップ搭載用基板が使用される温度範囲（−５０〜２７０℃）内では相転移点やガラス転移点などを持たない。したがって、熱処理しても不連続な寸法変化をしないため、微細な回路配線パターンが可能になる。また、チタンを主成分とするチタン合金は、その表面に陽極酸化被膜を形成することで、アルミニウムと同様、簡便に絶縁性に優れた良質の絶縁層が得られる利点もある。   In addition, the titanium alloy core substrate 2 has a flat enough surface to withstand the formation of a highly accurate circuit wiring pattern, and a temperature range (−50 to 270 ° C.) in which the semiconductor chip mounting substrate is used. It has no phase transition point or glass transition point. Therefore, even if heat treatment is performed, discontinuous dimensional changes do not occur, so that a fine circuit wiring pattern is possible. Further, a titanium alloy containing titanium as a main component has an advantage that a high-quality insulating layer having excellent insulating properties can be obtained simply as in the case of aluminum by forming an anodized film on the surface thereof.

さらには、従来のガラスエポキシのコア基板と異なり、平坦性に優れ、熱処理による寸法変化が生じない。したがって、半導体の高周波化、多機能化に伴う信号線数の増加に対して微細配線化による高密度配線で対応することが可能となり、積層数を少なくできる。   Furthermore, unlike the conventional glass epoxy core substrate, it has excellent flatness and does not undergo dimensional changes due to heat treatment. Therefore, it is possible to cope with an increase in the number of signal lines due to high frequency and multi-functionality of the semiconductor by high density wiring by fine wiring, and the number of stacked layers can be reduced.

つぎに、上述したパッケージ基板１０の製造方法について説明する。
図２は、本実施の形態の半導体チップ搭載用基板の製造プロセスを示す断面図である。
同図（Ａ）では、板状のチタン合金をコア基板２となる形状に加工する。その後、同図（Ｂ）に示すスルーホール形成工程（第１工程）では、機械ドリル加工などによって表裏面を貫通するスルーホール４が形成される。 Next, a method for manufacturing the above-described package substrate 10 will be described.
FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor chip mounting substrate of the present embodiment.
In FIG. 2A, a plate-like titanium alloy is processed into a shape that becomes the core substrate 2. Thereafter, in the through hole forming step (first step) shown in FIG. 5B, through holes 4 penetrating the front and back surfaces are formed by mechanical drilling or the like.

図２（Ｃ）の絶縁処理工程（第２工程）では、コア基板２の表裏面、およびスルーホール４の内壁面を含む全てのコア基板２の表面に陽極酸化処理によって陽極酸化膜３を形成して絶縁する。つぎに、同図（Ｄ）に示す貫通ビア形成工程（第３工程）では、スルーホール４を導電性ペーストの充填材などで導通処理を行い、表裏面での電気的接続が可能な貫通ビア９を形成する。チタン合金のコア基板２をグランドとして用いる場合には、同図（Ｅ）に示すように、絶縁処理工程で形成された陽極酸化膜３の一部を予めエッチングによって除去しておき、その後、グランド端子に繋がる導体パターン６と接続するようにしている（同図（Ｆ）参照）。   In the insulation treatment step (second step) in FIG. 2C, the anodic oxide film 3 is formed by anodic oxidation treatment on the front and back surfaces of the core substrate 2 and the surfaces of all the core substrates 2 including the inner wall surfaces of the through holes 4. And insulate. Next, in the through via forming step (third step) shown in FIG. 4D, the through hole 4 is subjected to conduction treatment with a conductive paste filler or the like, and can be electrically connected to the front and back surfaces. 9 is formed. When the titanium alloy core substrate 2 is used as the ground, as shown in FIG. 5E, a part of the anodic oxide film 3 formed in the insulating process is removed in advance by etching, and then the ground is formed. It is made to connect with the conductor pattern 6 connected to a terminal (refer to the figure (F)).

さらに、コア基板２の両面に、ビルドアップ材、メッキ層の張り合わせなどによる通常の回路基板の製造プロセスを施して、所望する回路を形成するビルドアップ工程（第４工程）を経て、図１に示したパッケージ基板１０を得ることができる。なお、コア基板２として使用するチタン系の金属基板としては、チタン・アルミニウム（Ｔｉ−Ａｌ）合金、チタン・ニッケル（Ｔｉ−Ｎｉ）合金、あるいはチタン・パラジウム（Ｔｉ−Ｐｄ）合金などのチタン合金材料を用いることができる。   Furthermore, a normal circuit board manufacturing process is performed on both surfaces of the core substrate 2 by build-up material, plating layer bonding, and the like, and a build-up process (fourth process) for forming a desired circuit is performed. The package substrate 10 shown can be obtained. The titanium-based metal substrate used as the core substrate 2 is a titanium alloy such as a titanium / aluminum (Ti—Al) alloy, a titanium / nickel (Ti—Ni) alloy, or a titanium / palladium (Ti—Pd) alloy. Materials can be used.

表１には、上述した３つのチタン合金材料の組成例を示す。チタン・アルミニウム合金にはバナジウム（Ｖ）が含有されていることで、チタン・ニッケル合金と同様に、高温でもコア基板２としての硬さを保持できる。また、チタン・パラジウム合金は、パラジウムが白金族グループの金属であることから、耐食性に優れている。   Table 1 shows composition examples of the three titanium alloy materials described above. Since the titanium / aluminum alloy contains vanadium (V), the hardness of the core substrate 2 can be maintained even at a high temperature as in the case of the titanium / nickel alloy. Titanium / palladium alloys are excellent in corrosion resistance because palladium is a platinum group metal.

Figure 2007180083
Figure 2007180083

ただし、チタン・アルミニウム合金とチタン・パラジウム合金は、それぞれ０．２０〜０．３０％の鉄（Ｆｅ）および微量の水素、酸素、窒素を含んでいる。
本実施の形態の半導体チップ搭載用基板は、半導体チップが基板片面側に実装されるコア基板として、チタン主成分とする金属基板を用いることで、スルーホールの加工後にその表面を陽極酸化膜によって絶縁化すると共に、部分的に陽極酸化膜が除去された部分に半導体チップのグランド電極を接続するようにしたので、コア基板をグランド電極として使用することが可能になり、マザーボードなど電子機器全体の回路基板との接続端子数が低減し、安定した半導体チップの実装構造が得られる。 However, the titanium / aluminum alloy and the titanium / palladium alloy each contain 0.20 to 0.30% iron (Fe) and a trace amount of hydrogen, oxygen, and nitrogen.
The substrate for mounting a semiconductor chip according to the present embodiment uses a metal substrate mainly composed of titanium as a core substrate on which the semiconductor chip is mounted on one side of the substrate. As well as being insulated, the ground electrode of the semiconductor chip is connected to the part from which the anodized film has been partially removed, so that the core substrate can be used as the ground electrode, and the entire electronic device such as a motherboard can be used. The number of connection terminals to the circuit board is reduced, and a stable semiconductor chip mounting structure can be obtained.

図３は、本実施の形態の半導体チップ搭載用基板の変形例を示す概略断面図である。
このパッケージ基板１１は、コア基板２を覆う陽極酸化膜３を誘電体層として、コンデンサを形成したものである。ここでは、図１の半導体チップ搭載用基板（パッケージ基板１０）について使用した符号と同一の符号を付して、重複する説明を省略する。 FIG. 3 is a schematic cross-sectional view showing a modification of the semiconductor chip mounting substrate according to the present embodiment.
The package substrate 11 is a capacitor in which an anodized film 3 covering the core substrate 2 is used as a dielectric layer. Here, the same reference numerals as those used for the semiconductor chip mounting substrate (package substrate 10) in FIG.

この変形例では、図２（Ｃ）の工程で形成された陽極酸化膜３をエッチングせずに残しておいて、コア基板２の陽極酸化膜３を介して一方電極となる導体パターン６３を形成している。ここでは、アルマイト系の陽極酸化膜と同様に、薄い膜厚で高い絶縁信頼性（高誘電率）が得られるため、これを用いて内蔵コンデンサを形成すれば、コア基板２と導体パターン６３とにより電極間距離の短い大容量のコンデンサが形成できる。   In this modification, the anodic oxide film 3 formed in the step of FIG. 2C is left without being etched, and a conductor pattern 63 serving as one electrode is formed through the anodic oxide film 3 of the core substrate 2. is doing. Here, as in the case of the anodized anodized film, high insulation reliability (high dielectric constant) can be obtained with a thin film thickness. Therefore, if an internal capacitor is formed using this, the core substrate 2 and the conductor pattern 63 As a result, a large-capacity capacitor with a short distance between the electrodes can be formed.

（付記１） 電子機器の回路基板に対して半導体チップを電気的に接続するための半導体チップ搭載用基板において、
チタンを主成分とし、表裏面を貫通するスルーホールが形成され、前記表裏面および前記スルーホールの内壁面に絶縁性被膜が形成された金属基板と、
前記表裏面の前記絶縁性被膜上に配置され、前記スルーホールを介して前記表裏面で互いに電気的に接続した複数の導体パターンを有する配線層と、
を備えたことを特徴とする半導体チップ搭載用基板。 (Appendix 1) In a semiconductor chip mounting substrate for electrically connecting a semiconductor chip to a circuit board of an electronic device,
A metal substrate having titanium as a main component, through holes penetrating the front and back surfaces, and an insulating film formed on the front and back surfaces and the inner wall surfaces of the through holes,
A wiring layer having a plurality of conductor patterns arranged on the insulating coating on the front and back surfaces and electrically connected to each other on the front and back surfaces through the through holes;
A semiconductor chip mounting board comprising:

（付記２） 前記配線層は、そのいずれか一部が前記金属基板の表面または裏面における前記絶縁性被膜の除去部分に直接接続され、前記金属基板をグランド層として用いていることを特徴とする付記１記載の半導体チップ搭載用基板。   (Additional remark 2) Any one part of the said wiring layer is directly connected to the removal part of the said insulating film in the surface or the back surface of the said metal substrate, The said metal substrate is used as a ground layer, It is characterized by the above-mentioned. The semiconductor chip mounting substrate according to appendix 1.

（付記３） 前記金属基板は、アルミニウム、ニッケル、あるいはパラジウムを含有するチタン合金により形成されていることを特徴とする付記１記載の半導体チップ搭載用基板。   (Supplementary note 3) The semiconductor chip mounting substrate according to supplementary note 1, wherein the metal substrate is formed of a titanium alloy containing aluminum, nickel, or palladium.

（付記４） 前記金属基板は、０．５ｍｍ以上の厚みを有するチタン合金により形成されていることを特徴とする付記１記載の半導体チップ搭載用基板。
（付記５） 前記金属基板には、前記配線層に接続された電極層が前記絶縁性被膜を介して配置され、前記絶縁性被膜を誘電体層とするコンデンサを形成していることを特徴とする付記１記載の半導体チップ搭載用基板。 (Supplementary note 4) The semiconductor chip mounting substrate according to supplementary note 1, wherein the metal substrate is formed of a titanium alloy having a thickness of 0.5 mm or more.
(Additional remark 5) The electrode layer connected to the said wiring layer is arrange | positioned through the said insulating film in the said metal substrate, The capacitor which uses the said insulating film as a dielectric material layer is formed, It is characterized by the above-mentioned. The semiconductor chip mounting substrate according to appendix 1.

（付記６） 前記配線層は、１層、あるいは複数層の絶縁層にそれぞれ配置されると共に、前記絶縁層を貫通するビアホールによって互いに接続されていることを特徴とする付記１記載の半導体チップ搭載用基板。   (Supplementary note 6) The semiconductor chip mounting according to supplementary note 1, wherein the wiring layers are arranged in one or more insulating layers, and are connected to each other by via holes penetrating the insulating layer. Substrate.

（付記７） 電子機器の回路基板に対して半導体チップを電気的に接続するための半導体チップ搭載用基板を製造する製造方法において、
コア基板となるチタン合金の表裏面を貫通してスルーホールを形成する第１工程と、
前記表裏面、および前記スルーホールの内壁面に陽極酸化によって酸化被膜を形成する第２工程と、
前記スルーホール内部に導電性ペーストを充填して前記表裏面を電気的に接続可能にする第３工程と、
前記表裏面でそれぞれ配線層となる少なくとも１層の導体パターンを前記酸化被膜上に形成する第４工程と、
を含むことを特徴とする半導体チップ搭載用基板の製造方法。 (Additional remark 7) In the manufacturing method which manufactures the board | substrate for semiconductor chip mounting for electrically connecting a semiconductor chip with respect to the circuit board of an electronic device,
A first step of forming a through-hole penetrating the front and back surfaces of the titanium alloy serving as a core substrate;
A second step of forming an oxide film by anodic oxidation on the front and back surfaces and the inner wall surface of the through hole;
A third step of allowing the front and back surfaces to be electrically connected by filling the through hole with a conductive paste;
A fourth step of forming at least one conductor pattern on the oxide film on the front and back surfaces, each serving as a wiring layer;
The manufacturing method of the board | substrate for semiconductor chip mounting characterized by including these.

（付記８） 前記第２工程で形成された前記酸化被膜の一部を予めエッチングにより除去し、前記第４工程でグランド端子となる前記配線層を前記コア基板に接続される導体パターンとして形成することを特徴とする付記７記載の半導体チップ搭載用基板の製造方法。   (Supplementary Note 8) Part of the oxide film formed in the second step is removed in advance by etching, and the wiring layer serving as a ground terminal is formed as a conductor pattern connected to the core substrate in the fourth step. The method for manufacturing a semiconductor chip mounting substrate according to appendix 7, wherein:

（付記９） 前記コア基板は、アルミニウム、ニッケル、あるいはパラジウムを含有するチタン合金であることを特徴とする付記７記載の半導体チップ搭載用基板の製造方法。
（付記１０） 前記第４工程では、前記コア基板の一方の面に前記半導体チップとの接続端子を含む第１の配線層を形成し、前記コア基板の他方の面に前記回路基板と接続するための外部接続端子を含む第２の配線層を形成したことを特徴とする付記７記載の半導体チップ搭載用基板の製造方法。 (Additional remark 9) The said core substrate is a titanium alloy containing aluminum, nickel, or palladium, The manufacturing method of the semiconductor chip mounting substrate of Additional remark 7 characterized by the above-mentioned.
(Additional remark 10) At the said 4th process, the 1st wiring layer containing the connection terminal with the said semiconductor chip is formed in one surface of the said core substrate, and it connects with the said circuit board in the other surface of the said core substrate. 8. The method for manufacturing a semiconductor chip mounting substrate according to appendix 7, wherein a second wiring layer including an external connection terminal is formed.

（付記１１） 搭載される前記半導体チップと前記コア基板の熱膨張係数をそれぞれα１，α２としたとき、α１≦α２≦１０（ｐｐｍ／℃）であることを特徴とする付記７記載の半導体チップ搭載用基板の製造方法。   (Supplementary note 11) The semiconductor chip according to Supplementary note 7, wherein α1 ≦ α2 ≦ 10 (ppm / ° C.), where α1 and α2 are thermal expansion coefficients of the semiconductor chip and the core substrate to be mounted, respectively. Manufacturing method of mounting substrate.

（付記１２） 前記コア基板の他方の面に接続される前記回路基板の熱膨張係数をα３（ｐｐｍ／℃）としたとき、α１≦α２≦α３であることを特徴とする付記１１記載の半導体チップ搭載用基板の製造方法。   (Supplementary note 12) The semiconductor according to supplementary note 11, wherein α1 ≦ α2 ≦ α3, where α3 (ppm / ° C.) is a thermal expansion coefficient of the circuit board connected to the other surface of the core substrate. A method for manufacturing a chip mounting substrate.

本実施の形態の半導体チップ搭載用基板を示す概略断面図である。It is a schematic sectional drawing which shows the substrate for semiconductor chip mounting of this Embodiment. 本実施の形態の半導体チップ搭載用基板の製造プロセスを示す断面図である。It is sectional drawing which shows the manufacturing process of the board | substrate for semiconductor chip mounting of this Embodiment. 本実施の形態の半導体チップ搭載用基板の変形例を示す概略断面図である。It is a schematic sectional drawing which shows the modification of the substrate for semiconductor chip mounting of this Embodiment.

符号の説明Explanation of symbols

１ 半導体チップ
２ コア基板
３ 陽極酸化膜
４ スルーホール
５ 絶縁層
６、６１〜６３ 導体パターン
７ ビアホール
８ はんだバンプ
９ 貫通ビア
１０、１１ パッケージ基板（半導体チップ搭載用基板）
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Core substrate 3 Anodized film 4 Through hole 5 Insulating layer 6, 61-63 Conductor pattern 7 Via hole 8 Solder bump 9 Through-via 10, 11 Package substrate (substrate for semiconductor chip mounting)

Claims (5)

電子機器の回路基板に対して半導体チップを電気的に接続するための半導体チップ搭載用基板において、
チタンを主成分とし、表裏面を貫通するスルーホールが形成され、前記表裏面および前記スルーホールの内壁面に絶縁性被膜が形成された金属基板と、
前記表裏面の前記絶縁性被膜上に配置され、前記スルーホールを介して前記表裏面で互いに電気的に接続した複数の導体パターンを有する配線層と、
を備えたことを特徴とする半導体チップ搭載用基板。 In a semiconductor chip mounting substrate for electrically connecting a semiconductor chip to a circuit board of an electronic device,
A metal substrate having titanium as a main component, through holes penetrating the front and back surfaces, and an insulating film formed on the front and back surfaces and the inner wall surfaces of the through holes,
A wiring layer having a plurality of conductor patterns arranged on the insulating coating on the front and back surfaces and electrically connected to each other on the front and back surfaces through the through holes;
A semiconductor chip mounting board comprising: 前記配線層は、そのいずれか一部が前記金属基板の表面または裏面における前記絶縁性被膜の除去部分に直接接続され、前記金属基板をグランド層として用いていることを特徴とする請求項１記載の半導体チップ搭載用基板。   2. The wiring layer according to claim 1, wherein any part of the wiring layer is directly connected to a portion where the insulating coating is removed on the front surface or the back surface of the metal substrate, and the metal substrate is used as a ground layer. Substrate for mounting semiconductor chips. 前記金属基板は、アルミニウム、ニッケル、あるいはパラジウムを含有するチタン合金により形成されていることを特徴とする請求項１記載の半導体チップ搭載用基板。   2. The semiconductor chip mounting substrate according to claim 1, wherein the metal substrate is made of a titanium alloy containing aluminum, nickel, or palladium. 前記金属基板には、前記配線層に接続された電極層が前記絶縁性被膜を介して配置され、前記絶縁性被膜を誘電体層とするコンデンサを形成していることを特徴とする請求項１記載の半導体チップ搭載用基板。   The electrode layer connected to the wiring layer is disposed on the metal substrate via the insulating film, and a capacitor having the insulating film as a dielectric layer is formed. The semiconductor chip mounting substrate described. 電子機器の回路基板に対して半導体チップを電気的に接続するための半導体チップ搭載用基板を製造する製造方法において、
コア基板となるチタン合金の表裏面を貫通してスルーホールを形成する第１工程と、
前記表裏面、および前記スルーホールの内壁面に陽極酸化によって酸化被膜を形成する第２工程と、
前記スルーホール内部に導電性ペーストを充填して前記表裏面を電気的に接続可能にする第３工程と、
前記表裏面でそれぞれ配線層となる少なくとも１層の導体パターンを前記酸化被膜上に形成する第４工程と、
を含むことを特徴とする半導体チップ搭載用基板の製造方法。
In a manufacturing method for manufacturing a semiconductor chip mounting substrate for electrically connecting a semiconductor chip to a circuit board of an electronic device,
A first step of forming a through-hole penetrating the front and back surfaces of the titanium alloy serving as a core substrate;
A second step of forming an oxide film by anodic oxidation on the front and back surfaces and the inner wall surface of the through hole;
A third step of allowing the front and back surfaces to be electrically connected by filling the through hole with a conductive paste;
A fourth step of forming at least one conductor pattern on the oxide film on the front and back surfaces, each serving as a wiring layer;
The manufacturing method of the board | substrate for semiconductor chip mounting characterized by including these.
JP2005373791A 2005-12-27 2005-12-27 Semiconductor chip mounting substrate and manufacturing method therefor Pending JP2007180083A (en)

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JPH11298104A (en) * 1998-04-16 1999-10-29 Sumitomo Metal Electronics Devices Inc Circuit board for mounting semiconductor
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WO2010047228A1 (en) * 2008-10-21 2010-04-29 日本電気株式会社 Wiring board and method for manufacturing same
JPWO2010047228A1 (en) * 2008-10-21 2012-03-22 日本電気株式会社 Wiring board and manufacturing method thereof
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JPWO2011002031A1 (en) * 2009-06-30 2012-12-13 三洋電機株式会社 Device mounting substrate and semiconductor module
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JP2015099913A (en) * 2013-10-16 2015-05-28 株式会社アライドマテリアル Substrate for mounting semiconductor element and semiconductor element device using the same
JP2016538425A (en) * 2013-11-15 2016-12-08 ケンブリッジ ナノサーム リミティド Flexible electronic board
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