JP2007158330A - CMOS対応の浅いトレンチのeフューズ構造体及びその製造方法 - Google Patents
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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Abstract
【解決手段】 半導体基板(バルク又は半導体オン・インシュレータ)内に配置されたトレンチ内に埋め込まれた少なくとも1つのeヒューズを含む半導体構造体が提供される。本発明によると、eヒューズは、半導体基板内に配置されたドーパント領域と電気接触した状態にある。本発明はまた、埋め込まれたeヒューズが、トレンチ分離領域とほぼ同時に形成される半導体構造体を製造する方法も提供する。
【選択図】 図11
Description
埋め込まれたeヒューズを含む少なくとも1つのヒューズ開口部を有する半導体基板が備わり、埋め込まれたeヒューズは、少なくとも1つのヒューズ開口部の側壁部分及び底壁部分上に配置され、かつ、側壁部分において半導体基板内に配置された隣接するドープ領域と電気接触した状態にある。
少なくとも1つのヒューズ開口部の側壁部分及び底壁部分の内側を少なくともヒューズ材料が覆うように、少なくとも1つのヒューズ開口部を半導体基板内に提供することと、
隣接する浅いトレンチ分離領域を半導体基板内に形成することであって、隣接する浅いトレンチ分離領域の形成中に、少なくとも1つの開口部内のヒューズ材料の外縁部分がトリミングされて、残りの半導体アイランドによって定められる少なくとも1つのヒューズ開口部の側壁部分に位置合わせされた埋め込まれたeヒューズが形成されるようにすることと、
埋め込まれたeヒューズと電気接触した状態のドープ領域を残りの半導体アイランド内に形成することと
を含む。
10A:下部半導体層
10B:埋込み絶縁層
10C:上部半導体層
12:誘電体キャップ
14:ヒューズ開口部
16:フォトレジト層
18:ヒューズ材料
20:浅いトレンチ分離(STI)領域
24:ゲート誘電体
26:ゲート導体
32:第1の導電性のイオン
36:第2の導電性のイオン
38:スペーサ
40:シリサイド領域
42:第1の相互接続レベル
44:層間誘電体
50:バルク半導体基板
Claims (18)
- 埋め込まれたeヒューズを含む少なくとも1つのヒューズ開口部を有する半導体基板を備え、
前記埋め込まれたeヒューズは、前記少なくとも1つのヒューズ開口部の側壁部分及び底壁部分上に配置され、かつ、前記側壁部分において前記半導体基板内に配置された隣接するドープ領域と電気接触した状態にある、半導体構造体。 - 前記半導体基板が半導体オン・インシュレータである、請求項1に記載の半導体構造体。
- 前記半導体基板がバルク半導体である、請求項1に記載の半導体構造体。
- 少なくとも前記底壁部分上に存在する酸化物又は別の電気絶縁及び熱絶縁の材料をさらに備える、請求項3に記載の半導体構造体。
- 前記少なくとも1つのヒューズ開口部がトレンチ誘電体材料で充填されている、請求項1に記載の半導体構造体。
- 前記eヒューズは、金属、金属合金、及びこれらの多層スタックからなる群から選択されるヒューズ材料からなる、請求項1に記載の半導体構造体。
- 前記ヒューズ材料は、Ti、Ta、TiN、TaN、W、WN、WSi、TiSi、又はこれらの混合物及び組み合わせの1つからなる、請求項6に記載の半導体構造体。
- 前記埋め込まれたeヒューズを含む前記少なくとも1つの開口部と前記半導体基板の前記隣接するドープ領域とを囲む浅いトレンチ分離領域をさらに備える、請求項1に記載の半導体構造体。
- 前記eヒューズは、前記少なくとも1つのヒューズ開口部の底部コーナー部に配置されたネック部を有するヒューズ材料からなる、請求項1に記載の半導体構造体。
- 前記ドーピング領域が、前記少なくとも1つのヒューズ開口部に隣接する前記半導体基板内に配置されたn型イオン又はp型イオンからなる、請求項1に記載の半導体構造体。
- 半導体構造体を製造する方法であって、
少なくとも1つのヒューズ開口部の側壁部分及び底壁部分の内側を少なくともヒューズ材料が覆うように、少なくとも1つのヒューズ開口部を半導体基板内に提供することと、
隣接する浅いトレンチ分離領域を前記半導体基板内に形成することであって、前記隣接する浅いトレン分離領域の形成中に、前記少なくとも1つの開口部内の前記ヒューズ材料の外縁部分がトリミングされて、残りの半導体アイランドによって定められる該少なくとも1つのヒューズ開口部の前記側壁部分に位置合わせされた埋め込まれたeヒューズが形成されるようにすることと、
前記埋め込まれたeヒューズと電気接触した状態のドープ領域を前記残りの半導体アイランド内に形成することと
を含む前記の方法。 - 前記少なくとも1つのヒューズ開口部を形成することは、リソグラフィ及びエッチングを含み、前記エッチングを、半導体オン・インシュレータ基板の埋込み絶縁層の上で停止させる、請求項11に記載の方法。
- 前記少なくとも1つのヒューズ開口部を形成することは、前記ヒューズ材料を形成する前に、少なくとも前記底壁上に電気絶縁材料又は熱絶縁材料を形成することを含む、請求項11に記載の方法。
- 前記隣接する浅いトレンチ分離領域を形成する間に、トレンチ誘電体材料が、前記少なくとも1つのヒューズ開口部内に充填される、請求項11に記載の方法。
- 前記eヒューズは、金属、金属合金、及び付着によって形成されたこれらの多層スタックからなる群から選択されるヒューズ材料からなる、請求項11に記載の方法。
- 前記ドープ領域を前記残りの半導体アイランド内に形成することは、イオン注入プロセスを用いる少なくとも1つの半導体デバイスの形成中に行われる、請求項11に記載の方法。
- 前記少なくとも1つの半導体デバイスは電界効果トランジスタを含む、請求項16に記載の方法。
- 前記半導体基板の上に、導電性に充填された接触開口部を有する層間誘電体を含む相互接続レベルを提供することをさらに含む、請求項11に記載の方法。
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US11/290,890 US7381594B2 (en) | 2005-11-30 | 2005-11-30 | CMOS compatible shallow-trench efuse structure and method |
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Cited By (2)
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KR20160119761A (ko) * | 2014-02-11 | 2016-10-14 | 인텔 코포레이션 | 도전체 백필을 갖는 임베드된 퓨즈 |
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US7986029B2 (en) * | 2005-11-08 | 2011-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual SOI structure |
US7491585B2 (en) | 2006-10-19 | 2009-02-17 | International Business Machines Corporation | Electrical fuse and method of making |
US7960809B2 (en) * | 2009-01-16 | 2011-06-14 | International Business Machines Corporation | eFuse with partial SiGe layer and design structure therefor |
US8912626B2 (en) | 2011-01-25 | 2014-12-16 | International Business Machines Corporation | eFuse and method of fabrication |
US8816473B2 (en) | 2012-04-05 | 2014-08-26 | International Business Machines Corporation | Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication |
US9293414B2 (en) | 2013-06-26 | 2016-03-22 | Globalfoundries Inc. | Electronic fuse having a substantially uniform thermal profile |
US9159667B2 (en) | 2013-07-26 | 2015-10-13 | Globalfoundries Inc. | Methods of forming an e-fuse for an integrated circuit product and the resulting e-fuse structure |
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KR20160119759A (ko) * | 2014-02-11 | 2016-10-14 | 인텔 코포레이션 | 백필링된 단자들을 갖는 안티퓨즈 |
KR20160119761A (ko) * | 2014-02-11 | 2016-10-14 | 인텔 코포레이션 | 도전체 백필을 갖는 임베드된 퓨즈 |
KR102207042B1 (ko) * | 2014-02-11 | 2021-01-25 | 인텔 코포레이션 | 임베드된 퓨즈, 집적 회로, 임베드된 퓨즈를 제조하는 방법 및 집적 회로를 형성하는 방법 |
KR102212151B1 (ko) | 2014-02-11 | 2021-02-04 | 인텔 코포레이션 | 안티퓨즈 구조, 안티퓨즈 비트 셀 구조, 안티퓨즈 구조를 제조하는 방법 및 모놀리식 안티퓨즈 비트 셀을 형성하는 방법 |
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US7381594B2 (en) | 2008-06-03 |
CN1976035A (zh) | 2007-06-06 |
US20070120218A1 (en) | 2007-05-31 |
JP4856523B2 (ja) | 2012-01-18 |
CN100483715C (zh) | 2009-04-29 |
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