JP2007158080A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2007158080A JP2007158080A JP2005351976A JP2005351976A JP2007158080A JP 2007158080 A JP2007158080 A JP 2007158080A JP 2005351976 A JP2005351976 A JP 2005351976A JP 2005351976 A JP2005351976 A JP 2005351976A JP 2007158080 A JP2007158080 A JP 2007158080A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
【解決手段】半導体装置1は、基板10、配線12(第1の配線)、配線14(第2の配線)、半導体チップ20、およびヒートシンク30(導電性部材)を備えている。配線12は、半導体チップ20の内部配線と電気的に接続された配線である。一方、配線14は、半導体チップ20の裏面S1(第1面)と電気的に接続された配線である。これらの配線12と配線14とは、基板10中において、互いに電気的に絶縁されている。基板10上には、半導体チップ20が設けられている。半導体チップ20の裏面S1には、配線14を介して所定の固定電位が与えられる。
【選択図】図1
Description
10 基板
12 配線
14 配線
16 半田バンプ
20 半導体チップ
22 半田バンプ
30 ヒートシンク
32 導電性接着剤
40 支持枠
52 アンダーフィル樹脂
54 サイドフィル樹脂
Claims (8)
- 基板と、
前記基板上に設けられた半導体チップと、
前記半導体チップの前記基板と反対側の面である第1面上に設けられた導電性部材と、
前記基板中に設けられ、前記半導体チップの内部配線と電気的に接続された第1の配線と、
前記基板中に設けられ、前記半導体チップの前記第1面と電気的に接続された第2の配線と、を備え、
前記半導体チップの前記第1面には、前記第2の配線を介して所定の固定電位が与えられ、
前記基板中において、前記第1の配線と前記第2の配線とは、互いに電気的に絶縁されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記固定電位は、グランド電位である半導体装置。 - 請求項1または2に記載の半導体装置において、
前記半導体チップの厚みは、300μm以下である半導体装置。 - 請求項1乃至3いずれかに記載の半導体装置において、
前記導電性部材は、前記半導体チップの前記第1面の全体を覆っている半導体装置。 - 請求項1乃至4いずれかに記載の半導体装置において、
前記導電性部材は、ヒートシンクである半導体装置。 - 請求項5に記載の半導体装置において、
前記ヒートシンクは、導電性接着剤を介して前記半導体チップの前記第1面に固定されている半導体装置。 - 請求項1乃至6いずれかに記載の半導体装置において、
前記基板上に設けられ、前記導電性部材を支持する導電性の支持部材を備え、
前記半導体チップの前記第1面には、前記第2の配線および前記支持部材を介して、前記固定電位が与えられる半導体装置。 - 請求項1乃至7いずれかに記載の半導体装置において、
前記半導体チップは、前記基板上にフリップチップ実装されている半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005351976A JP4860994B2 (ja) | 2005-12-06 | 2005-12-06 | 半導体装置 |
US11/607,009 US20070126113A1 (en) | 2005-12-06 | 2006-12-01 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005351976A JP4860994B2 (ja) | 2005-12-06 | 2005-12-06 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007158080A true JP2007158080A (ja) | 2007-06-21 |
JP4860994B2 JP4860994B2 (ja) | 2012-01-25 |
Family
ID=38117883
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005351976A Expired - Fee Related JP4860994B2 (ja) | 2005-12-06 | 2005-12-06 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20070126113A1 (ja) |
JP (1) | JP4860994B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011513970A (ja) * | 2008-02-28 | 2011-04-28 | エルエスアイ コーポレーション | はんだとフィルム接着剤を用いてヒートスプレッダ/補強材をフリップチップパッケージに接地する方法 |
JP2019021763A (ja) * | 2017-07-18 | 2019-02-07 | 株式会社ダイレクト・アール・エフ | 半導体装置、及び基板 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9831190B2 (en) | 2014-01-09 | 2017-11-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device package with warpage control structure |
US9460980B2 (en) | 2015-02-18 | 2016-10-04 | Qualcomm Incorporated | Systems, apparatus, and methods for heat dissipation |
CN111092062B (zh) * | 2018-10-24 | 2021-06-08 | 欣兴电子股份有限公司 | 晶片封装结构及其制造方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02281737A (ja) * | 1989-04-24 | 1990-11-19 | Toshiba Corp | 半田バンプ型半導体装置 |
JPH07202064A (ja) * | 1993-12-28 | 1995-08-04 | Toshiba Corp | 半導体装置 |
JPH11145333A (ja) * | 1997-09-02 | 1999-05-28 | Oki Electric Ind Co Ltd | 半導体装置 |
JP2000183208A (ja) * | 1998-12-10 | 2000-06-30 | Kyocera Corp | 電子部品収納用パッケージ |
JP2003068899A (ja) * | 2001-08-29 | 2003-03-07 | Pfu Ltd | Lsiパッケージ |
JP2003086737A (ja) * | 2001-09-11 | 2003-03-20 | Toshiba Corp | 半導体装置 |
Family Cites Families (21)
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JP3034180B2 (ja) * | 1994-04-28 | 2000-04-17 | 富士通株式会社 | 半導体装置及びその製造方法及び基板 |
EP0740340B1 (en) * | 1995-04-07 | 2002-06-26 | Shinko Electric Industries Co. Ltd. | Structure and process for mounting semiconductor chip |
US6351389B1 (en) * | 1996-05-07 | 2002-02-26 | Sun Microsystems, Inc. | Device and method for packaging an electronic device |
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JP3466443B2 (ja) * | 1997-11-19 | 2003-11-10 | 新光電気工業株式会社 | 多層回路基板 |
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JP2001035957A (ja) * | 1999-07-19 | 2001-02-09 | Mitsubishi Electric Corp | 電子部品収納用パッケージならびに半導体装置およびパッケージ製造方法 |
TW478119B (en) * | 2000-06-26 | 2002-03-01 | Siliconware Precision Industries Co Ltd | Semiconductor package having heat sink which can be anchored on the substrate |
US6580167B1 (en) * | 2001-04-20 | 2003-06-17 | Amkor Technology, Inc. | Heat spreader with spring IC package |
EP1263043A1 (en) * | 2001-05-30 | 2002-12-04 | Alcatel | Electronic element with a shielding |
US6635970B2 (en) * | 2002-02-06 | 2003-10-21 | International Business Machines Corporation | Power distribution design method for stacked flip-chip packages |
US20030178719A1 (en) * | 2002-03-22 | 2003-09-25 | Combs Edward G. | Enhanced thermal dissipation integrated circuit package and method of manufacturing enhanced thermal dissipation integrated circuit package |
US6775140B2 (en) * | 2002-10-21 | 2004-08-10 | St Assembly Test Services Ltd. | Heat spreaders, heat spreader packages, and fabrication methods for use with flip chip semiconductor devices |
CA2409912C (en) * | 2002-10-25 | 2008-04-01 | Ibm Canada Limited-Ibm Canada Limitee | Improvements in grounding and thermal dissipation for integrated circuit packages |
US6956285B2 (en) * | 2003-01-15 | 2005-10-18 | Sun Microsystems, Inc. | EMI grounding pins for CPU/ASIC chips |
TWI235469B (en) * | 2003-02-07 | 2005-07-01 | Siliconware Precision Industries Co Ltd | Thermally enhanced semiconductor package with EMI shielding |
US7575955B2 (en) * | 2004-01-06 | 2009-08-18 | Ismat Corporation | Method for making electronic packages |
US20060002092A1 (en) * | 2004-07-02 | 2006-01-05 | Tyco Electronics Power Systems, Inc., A Nevada Corporation | Board mounted heat sink using edge plating |
US20060091516A1 (en) * | 2004-11-01 | 2006-05-04 | Akira Matsunami | Flexible leaded stacked semiconductor package |
US7388284B1 (en) * | 2005-10-14 | 2008-06-17 | Xilinx, Inc. | Integrated circuit package and method of attaching a lid to a substrate of an integrated circuit |
-
2005
- 2005-12-06 JP JP2005351976A patent/JP4860994B2/ja not_active Expired - Fee Related
-
2006
- 2006-12-01 US US11/607,009 patent/US20070126113A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02281737A (ja) * | 1989-04-24 | 1990-11-19 | Toshiba Corp | 半田バンプ型半導体装置 |
JPH07202064A (ja) * | 1993-12-28 | 1995-08-04 | Toshiba Corp | 半導体装置 |
JPH11145333A (ja) * | 1997-09-02 | 1999-05-28 | Oki Electric Ind Co Ltd | 半導体装置 |
JP2000183208A (ja) * | 1998-12-10 | 2000-06-30 | Kyocera Corp | 電子部品収納用パッケージ |
JP2003068899A (ja) * | 2001-08-29 | 2003-03-07 | Pfu Ltd | Lsiパッケージ |
JP2003086737A (ja) * | 2001-09-11 | 2003-03-20 | Toshiba Corp | 半導体装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011513970A (ja) * | 2008-02-28 | 2011-04-28 | エルエスアイ コーポレーション | はんだとフィルム接着剤を用いてヒートスプレッダ/補強材をフリップチップパッケージに接地する方法 |
JP2019021763A (ja) * | 2017-07-18 | 2019-02-07 | 株式会社ダイレクト・アール・エフ | 半導体装置、及び基板 |
Also Published As
Publication number | Publication date |
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JP4860994B2 (ja) | 2012-01-25 |
US20070126113A1 (en) | 2007-06-07 |
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