JP2007103789A - Wiring board and manufacturing method therefor - Google Patents

Wiring board and manufacturing method therefor Download PDF

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JP2007103789A
JP2007103789A JP2005293806A JP2005293806A JP2007103789A JP 2007103789 A JP2007103789 A JP 2007103789A JP 2005293806 A JP2005293806 A JP 2005293806A JP 2005293806 A JP2005293806 A JP 2005293806A JP 2007103789 A JP2007103789 A JP 2007103789A
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core
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main surface
resin
ceramic
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JP4880277B2 (en
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Shinji Yuri
伸治 由利
Kazuhiro Urashima
和浩 浦島
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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Priority to US11/445,288 priority patent/US7696442B2/en
Priority to TW095119500A priority patent/TWI396481B/en
Priority to CN2006100887735A priority patent/CN1874648B/en
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Priority to US12/706,695 priority patent/US8863378B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01041—Niobium [Nb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
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    • H01L2924/30107—Inductance

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a wiring board that can favorably form insulating resin layers on a core substrate and via holes prepared thereon when manufacturing a wiring board having a core substrate in which a ceramic sub-core is housed. <P>SOLUTION: The manufacturing method for a wiring board 1 includes a sub-core housing step that houses a ceramic sub-core 3 in a sub-core housing 25, and a film forming-filling step that alternately pressure-bonds a resin film 91 to a core main body 2 and the ceramic sub-core 3 from the side of double main planes MP1 and MP2 to form each of resinous insulating layers B11 and B21 that become bottom layers of the wiring laminations L1 and L2 at the side of the double main planes MP1 and MP2 and fill a groove filler 4 into a gap between the core main body 2 and the ceramic sub-core 3, the groove filler 4 connecting to the respective resinous insulating layers B11 and B21 at the side of the double main planes MP1 and MP2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、セラミックを主体とするセラミック副コアが収容されたコア基板を備える配線基板及びその製造方法に関する。   The present invention relates to a wiring board including a core substrate in which a ceramic sub-core mainly composed of ceramic is accommodated, and a manufacturing method thereof.

従来より、半導体集積回路素子（以下「ＩＣチップ」という）が搭載される配線基板には、ＩＣチップのスイッチングノイズの低減や動作電源電圧の安定化を図るために、コンデンサを配設することが行われている。コンデンサを配線基板に設ける場合、ＩＣチップとコンデンサとの間の配線長が長くなるほど配線のインダクタンス成分が増加して、上記の効果を十分に得ることが難しくなることから、コンデンサはなるべくＩＣチップの近傍に設けるほうが望ましい。そこで、特許文献１では、ＩＣチップの直下領域となるコア基板内に、コンデンサが組込まれたセラミック副コアを収容した構造を有する配線基板が提案されている。   Conventionally, a capacitor is provided on a wiring board on which a semiconductor integrated circuit element (hereinafter referred to as an “IC chip”) is mounted in order to reduce switching noise of the IC chip and stabilize the operating power supply voltage. Has been done. When the capacitor is provided on the wiring board, the longer the wiring length between the IC chip and the capacitor, the more the wiring inductance component increases, making it difficult to obtain the above effects sufficiently. It is desirable to provide it near. Therefore, Patent Document 1 proposes a wiring board having a structure in which a ceramic sub-core in which a capacitor is incorporated is accommodated in a core board that is a region directly under an IC chip.

特開２００５−３９２４３号公報JP-A-2005-39243

ところで、上記のようなコア基板を得るには、例えば、図１４（ａ）に示すように、副コア収容部（貫通孔）が形成されたコア本体ＣＭの第２主面ＭＰ２を、粘着剤ａｄを有する粘着シート材Ｓで覆い、セラミック副コアＣＳを第１主面ＭＰ１側の開口から粘着剤ａｄに固着させることで収容し、その後、コア本体ＣＭとセラミック副コアＣＳの隙間に、シリカフィラー等の無機フィラーを含む充填樹脂ＪＪを公知のディスペンス装置ＤＳにより注入する。   By the way, in order to obtain the core substrate as described above, for example, as shown in FIG. 14A, the second main surface MP2 of the core main body CM in which the sub-core housing portion (through hole) is formed is formed with an adhesive. It is covered with an adhesive sheet material S having ad and accommodated by adhering the ceramic sub-core CS to the adhesive ad from the opening on the first main surface MP1 side, and then silica in the gap between the core body CM and the ceramic sub-core CS. Filling resin JJ containing an inorganic filler such as a filler is injected by a known dispensing apparatus DS.

しかしながら、このようにディスペンス装置ＤＳを用いて充填樹脂ＪＪを注入する場合、セラミック副コアＣＳの第２主面ＭＰ２側には、次のような問題が生じる。すなわち、図１４（ｂ）に示すように、注入された充填樹脂ＪＪが第２主面ＭＰ２と粘着シート材Ｓの粘着剤ａｄとの間に潜り込んで、第２主面ＭＰ２に形成された導体パッドを覆ってしまうことがある。この状態で、コア基板ＣＢ上に絶縁樹脂層が形成されると、導体パッド上には特性の異なる樹脂層が複数重なって形成されることになるため、ビア孔をレーザ等で穿設する場合に樹脂層の界面で段差が生じたり、穿設後の樹脂残渣を除去しきれないなど、ビア孔を良好に形成することができなくなる。また、導体パッドを覆った充填樹脂ＪＪを研磨等により除去することも考えられるが、これは工程数が増えるため好ましくない。   However, when the filling resin JJ is injected using the dispensing device DS in this way, the following problem occurs on the second main surface MP2 side of the ceramic sub-core CS. That is, as shown in FIG. 14B, the filled resin JJ injected between the second main surface MP2 and the adhesive ad of the adhesive sheet material S is a conductor formed on the second main surface MP2. The pad may be covered. When an insulating resin layer is formed on the core substrate CB in this state, a plurality of resin layers having different characteristics are formed on the conductor pad, so that a via hole is formed by a laser or the like. In other words, there is a step at the interface of the resin layer, and the resin residue after drilling cannot be completely removed. It is also conceivable to remove the filling resin JJ covering the conductor pads by polishing or the like, but this is not preferable because the number of steps increases.

また、セラミック副コアＣＳの第１主面ＭＰ１側には、次のような問題が生じる。すなわち、副コア収容部（貫通孔）の形状や、セラミック副コアＣＳの大きさや位置精度には多少のバラつきがあることから、ディスペンス装置ＤＳによる充填樹脂ＪＪの注入量が一定であっても、注入された充填樹脂ＪＪがコア本体ＣＭとセラミック副コアＣＳの隙間から盛り上がる等して第１主面に凹凸が生じてしまう。この場合、その上に形成される絶縁樹脂層に凹凸が反映されたりして、樹脂絶縁層を均一な厚みとすることがことができなくなってしまう。また、場合によっては、盛り上がり過ぎた充填樹脂が広がって導体パッドを覆ってしまい、上述のような問題が生じることもある。   Further, the following problem occurs on the first main surface MP1 side of the ceramic sub-core CS. That is, since there is some variation in the shape of the sub-core housing part (through hole) and the size and position accuracy of the ceramic sub-core CS, even if the injection amount of the filling resin JJ by the dispensing device DS is constant, The injected filling resin JJ rises from the gap between the core body CM and the ceramic sub-core CS, and unevenness is generated on the first main surface. In this case, unevenness is reflected on the insulating resin layer formed thereon, and the resin insulating layer cannot be made to have a uniform thickness. In some cases, the overfilled filling resin spreads and covers the conductor pads, which may cause the problems described above.

本発明は、上記問題を鑑みて為されたものであり、セラミック副コアが収容されたコア基板を備える配線基板を製造するにあたって、コア基板上の絶縁樹脂層に設けられるビア孔を良好に形成することができる配線基板の製造方法、及びそれにより得られる配線基板を提供することを目的とする。   The present invention has been made in view of the above problems, and in manufacturing a wiring board including a core substrate in which a ceramic sub-core is accommodated, the via hole provided in the insulating resin layer on the core substrate is well formed. It is an object of the present invention to provide a method for manufacturing a wiring board, and a wiring board obtained thereby.

課題を解決するための手段及び発明の効果Means for Solving the Problems and Effects of the Invention

上記課題を解決するため、本発明の配線基板の製造方法は、
板状のコア本体に主面間を貫通する貫通孔あるいは第１主面に開口する凹部として副コア収容部が形成され、その内部にセラミックを主体とする板状のセラミック副コアが収容されたコア基板と、該コア基板の主面上に樹脂絶縁層と導体層とが交互に積層して形成された配線積層部と、を備える配線基板の製造方法であって、
セラミック副コアを、副コア収容部の第１主面の開口側から収容する副コア収容工程と、
コア本体及びセラミック副コアに第１主面側から樹脂材料を付着させることで、第１主面側の配線積層部の最下層となる樹脂絶縁層を形成するとともに、コア本体とセラミック副コアの隙間に当該樹脂絶縁層と連続する溝埋め部を充填形成する成膜充填工程と、
をこの順に含むことを特徴とする。 In order to solve the above problems, a method for manufacturing a wiring board according to the present invention includes:
The plate-shaped core body is formed with a sub-core housing portion as a through hole penetrating between the main surfaces or a recess opening in the first main surface, and a plate-shaped ceramic sub-core mainly composed of ceramic is housed therein. A wiring board manufacturing method comprising: a core board; and a wiring laminated part formed by alternately laminating resin insulating layers and conductor layers on a main surface of the core board,
A sub core housing step of housing the ceramic sub core from the opening side of the first main surface of the sub core housing portion;
By attaching a resin material to the core main body and the ceramic sub-core from the first main surface side, a resin insulating layer that is the lowest layer of the wiring laminated portion on the first main surface side is formed, and the core main body and the ceramic sub-core A film filling process for filling the gap with a groove filling portion continuous with the resin insulating layer,
Are included in this order.

また、これにより得られる本発明の配線基板は、
板状のコア本体に主面間を貫通する貫通孔あるいは第１主面に開口する凹部として副コア収容部が形成され、その内部にセラミックを主体とする板状のセラミック副コアが収容されたコア基板と、該コア基板の主面上に樹脂絶縁層と導体層とが交互に積層して形成された配線積層部と、を備える配線基板であって、
コア本体とセラミック副コアの隙間に充填形成された溝埋め部が、第１主面側の配線積層部の最下層となる樹脂絶縁層と連続して形成されてなり、
第１主面側の配線積層部の最下層となる単層の樹脂絶縁層には、当該樹脂絶縁層下でコア本体またはセラミック副コアの主面に形成されている導体パターンと、当該樹脂絶縁層上に形成された導体層と、を導通させるためのビア導体が形成されてなることを特徴とする。 Moreover, the wiring board of the present invention obtained thereby is
The plate-shaped core body is formed with a sub-core housing portion as a through hole penetrating between the main surfaces or a recess opening in the first main surface, and a plate-shaped ceramic sub-core mainly composed of ceramic is housed therein. A wiring board comprising: a core substrate; and a wiring laminated portion formed by alternately laminating resin insulating layers and conductor layers on the main surface of the core substrate,
The groove filling portion filled in the gap between the core body and the ceramic sub-core is formed continuously with the resin insulating layer that is the lowest layer of the wiring laminated portion on the first main surface side,
The single-layer resin insulation layer, which is the lowermost layer of the wiring laminate on the first main surface side, includes a conductor pattern formed on the main surface of the core body or ceramic sub-core under the resin insulation layer, and the resin insulation A via conductor is formed to electrically connect the conductor layer formed on the layer.

上記本発明によると、第１主面側の配線積層部の最下層となる樹脂絶縁層と、コア本体とセラミック副コアの隙間に充填形成された溝埋め部と、を連続・一体のものとして一括して形成しており、上述のような充填樹脂を必要とせず、セラミック副コア上に特性の異なる樹脂層が２層重なって形成されるようなことがないため、ビア孔を良好に形成することが可能となる。また、樹脂絶縁層と溝埋め部とを一括して形成することから、コア基板上に形成される樹脂絶縁層を均一な厚みを有するものとすることができる。また、従来の工程と比べて充填樹脂を注入する工程を省略することができ、製造工程が簡略なものとなる。さらに、これにより得られる配線基板は、樹脂絶縁層と溝埋め部とが連続・一体に形成されることによりコア基板と配線積層部との密着性が高まるとともに、セラミック副コアが取り囲まれることになるためコア本体とセラミック副コアとの密着性も高まる。   According to the present invention, the resin insulating layer, which is the lowermost layer of the wiring laminated portion on the first main surface side, and the groove filling portion that is formed by filling the gap between the core body and the ceramic sub-core are continuous and integrated. It is formed in a lump and does not require the filling resin as described above, and it does not form two layers of resin layers with different characteristics on the ceramic sub-core, so the via hole is formed well. It becomes possible to do. Moreover, since the resin insulating layer and the groove filling portion are formed together, the resin insulating layer formed on the core substrate can have a uniform thickness. Further, the step of injecting the filling resin can be omitted as compared with the conventional step, and the manufacturing process is simplified. Furthermore, the wiring board obtained in this way has a resin insulating layer and a groove filling portion formed continuously and integrally, thereby improving the adhesion between the core substrate and the wiring laminated portion and surrounding the ceramic sub-core. Therefore, the adhesion between the core body and the ceramic sub-core is also increased.

次に、本発明の配線基板の製造方法は、
板状のコア本体に主面間を貫通する貫通孔として副コア収容部が形成され、その内部にセラミックを主体とする板状のセラミック副コアが収容されたコア基板と、該コア基板の主面上に樹脂絶縁層と導体層とが交互に積層して形成された配線積層部と、を備える配線基板の製造方法であって、
セラミック副コアを副コア収容部に収容する副コア収容工程と、
コア本体及びセラミック副コアに両主面側から交互に樹脂材料を付着させることで、両主面側の配線積層部の最下層となる樹脂絶縁層を各々形成するとともに、コア本体とセラミック副コアの隙間に当該両主面側の各樹脂絶縁層と連続する溝埋め部を充填形成する成膜充填工程と、
をこの順に含むことを特徴とする。 Next, the manufacturing method of the wiring board of the present invention includes
A sub-core housing portion is formed in the plate-shaped core body as a through-hole penetrating between the main surfaces, and a core substrate in which a plate-shaped ceramic sub-core mainly composed of ceramic is housed, and a main substrate of the core substrate A wiring laminated part formed by alternately laminating resin insulation layers and conductor layers on a surface, and a method of manufacturing a wiring board comprising:
A sub-core housing step of housing the ceramic sub-core in the sub-core housing portion;
By alternately adhering resin materials to the core body and the ceramic sub-core from both main surface sides, a resin insulating layer that is the lowest layer of the wiring laminated portion on both main surface sides is formed, and the core main body and the ceramic sub-core are formed. A film-filling step of filling and forming a groove filling portion that is continuous with the resin insulation layers on both principal surfaces in the gap,
Are included in this order.

また、これにより得られる本発明の配線基板は、
板状のコア本体に主面間を貫通する貫通孔として副コア収容部が形成され、その内部にセラミックを主体とする板状のセラミック副コアが収容されたコア基板と、該コア基板の主面上に樹脂絶縁層と導体層とが交互に積層して形成された配線積層部と、を備える配線基板であって、
コア本体とセラミック副コアの隙間に充填形成された溝埋め部が、両主面側の配線積層部の最下層となる各樹脂絶縁層と連続して形成されてなり、
両主面側の配線積層部の最下層となる単層の樹脂絶縁層には、当該樹脂絶縁層下でコア本体またはセラミック副コアの主面に形成されている導体パターンと、当該樹脂絶縁層上に形成された導体層と、を導通させるためのビア導体が形成されてなることを特徴とする。 Moreover, the wiring board of the present invention obtained thereby is
A sub-core housing portion is formed in the plate-shaped core body as a through-hole penetrating between the main surfaces, and a core substrate in which a plate-shaped ceramic sub-core mainly composed of ceramic is housed, and a main substrate of the core substrate A wiring board comprising a wiring laminated portion formed by alternately laminating resin insulating layers and conductor layers on a surface,
The groove filling portion filled in the gap between the core body and the ceramic sub-core is formed continuously with each resin insulating layer which is the lowermost layer of the wiring laminated portion on both main surface sides,
The single-layer resin insulation layer, which is the lowermost layer of the wiring laminate on both main surfaces, includes a conductor pattern formed on the main surface of the core body or ceramic sub-core under the resin insulation layer, and the resin insulation layer A via conductor is formed to electrically connect the conductor layer formed above.

上記本発明によると、両主面側の配線積層部の最下層となるそれぞれの樹脂絶縁層と、コア本体とセラミック副コアの隙間に充填形成された溝埋め部と、を連続・一体のものとして形成しており、上述のような充填樹脂を必要とせず、セラミック副コア上に特性の異なる樹脂層が２層重なって形成されるようなことがないため、ビア孔を良好に形成することなどが可能となる。また、溝埋め部を少なくとも一方の樹脂絶縁層とを一括して形成することから、コア基板上に形成される樹脂絶縁層を均一な厚みを有するものとすることができる。また、従来の工程と比べて充填樹脂を注入する工程を省略することができ、製造工程が簡略なものとなる。さらに、これにより得られる配線基板は、両主面側のそれぞれの樹脂絶縁層と溝埋め部とが連続・一体に形成されることによりコア基板と配線積層部との密着性が高まるとともに、セラミック副コアが取り囲まれることになるためコア本体とセラミック副コアとの密着性も高まる。   According to the present invention, each resin insulation layer which is the lowermost layer of the wiring laminated portion on both main surfaces side, and the groove filling portion formed by filling the gap between the core body and the ceramic sub-core are continuous and integrated. As the above-mentioned filling resin is not required and two resin layers with different characteristics are not formed on the ceramic sub-core, the via hole should be formed well. It becomes possible. Further, since the groove filling portion is formed together with at least one of the resin insulation layers, the resin insulation layer formed on the core substrate can have a uniform thickness. Further, the step of injecting the filling resin can be omitted as compared with the conventional step, and the manufacturing process is simplified. Furthermore, the wiring board obtained by this is formed such that the resin insulation layers and the groove filling portions on both main surfaces are continuously and integrally formed, so that the adhesion between the core substrate and the wiring laminated portion is increased, and the ceramic Since the sub-core is surrounded, the adhesion between the core body and the ceramic sub-core is enhanced.

また、本発明の配線基板の製造方法は、
成膜充填工程後に、配線積層部の最下層となる単層の樹脂絶縁層に、当該樹脂絶縁層下でコア本体またはセラミック副コアの主面に形成されている導体パターンと、当該樹脂絶縁層上に形成される導体層と、を導通させるためのビア導体を形成する工程を含むようにすることができる。 Moreover, the manufacturing method of the wiring board of the present invention includes:
After the film-filling step, the conductor pattern formed on the main surface of the core body or the ceramic sub-core under the resin insulation layer and the resin insulation layer on the single-layer resin insulation layer that is the lowermost layer of the wiring laminated portion It is possible to include a step of forming a via conductor for conducting the conductive layer formed on the conductive layer.

次に、本発明の配線基板の製造方法は、成膜充填工程において、
コア本体の主面間を貫通する貫通孔として形成された副コア収容部内にセラミック副コアが第２主面側から支持された状態で、コア本体及びセラミック副コアに第１主面側から樹脂フィルムを圧着することで、第１主面側の配線積層部の最下層となる第１側樹脂絶縁層を形成するとともに、コア本体とセラミック副コアの隙間のうち少なくとも第１主面側の隙間を埋めるように、当該第１側樹脂絶縁層と連続する第１側溝埋め部を充填形成する操作と、
第１側樹脂絶縁層および第１側溝埋め部によりセラミック副コアが第１主面側から支持された状態で、コア本体及びセラミック副コアに第２主面側から樹脂フィルムを圧着することで、第２主面側の配線積層部の最下層となる第２側樹脂絶縁層を形成するとともに、コア本体とセラミック副コアの隙間のうち第１側溝埋め部に埋められていない残部を埋めるように、当該第２側樹脂絶縁層と連続する第２側溝埋め部を充填形成する操作と、を行うようにすることができる。 Next, the method for manufacturing a wiring board according to the present invention, in the film filling step,
Resin from the first main surface side to the core main body and the ceramic sub core in a state where the ceramic sub core is supported from the second main surface side in the sub core housing portion formed as a through hole penetrating between the main surfaces of the core main body. By crimping the film, the first side resin insulation layer which is the lowermost layer of the first main surface side wiring laminated portion is formed, and at least the first main surface side gap among the gaps between the core body and the ceramic sub-core. Filling and forming a first side groove filling portion continuous with the first side resin insulation layer,
In a state where the ceramic sub core is supported from the first main surface side by the first side resin insulation layer and the first side groove filling portion, by pressing the resin film from the second main surface side to the core body and the ceramic sub core, A second resin insulation layer is formed as a lowermost layer of the wiring laminated portion on the second main surface side, and a remaining portion of the gap between the core body and the ceramic sub-core that is not buried in the first groove filling portion is filled. Then, an operation of filling and forming the second side groove filling portion continuous with the second side resin insulation layer can be performed.

上記本発明によると、まず、第１主面側から樹脂フィルムを圧着することで第１側樹脂絶縁層と第１側溝埋め部とを連続・一体のものとして一括して形成し、次に、第２主面側から樹脂フィルムを圧着することで第２側樹脂絶縁層と第２側溝埋め部とを連続・一体のものとして一括して形成しており、第１側溝埋め部と第２側溝埋め部とが合わさって上記の溝埋め部となる。このように樹脂フィルムを圧着することにより、樹脂絶縁層を均一な厚さを有するものとして構成できるとともに、それと同時に溝埋め部を連続・一体に一括して形成できる。また、第１側溝埋め部と第２側溝埋め部とが合わさって溝埋め部となる構成にすることによって、第１主面側および第２主面側のどちらにもセラミック副コアの密着性をより高めることができる。   According to the present invention, first, the first side resin insulation layer and the first side groove filling portion are collectively formed as a continuous and integrated body by crimping a resin film from the first main surface side, The second side resin insulation layer and the second side groove filling portion are formed together as a continuous and integrated body by pressing the resin film from the second main surface side, and the first side groove filling portion and the second side groove are formed. The groove filling portion is combined with the filling portion. By pressing the resin film in this way, the resin insulating layer can be configured to have a uniform thickness, and at the same time, the groove filling portion can be formed continuously and integrally in a lump. Further, by combining the first side groove filling portion and the second side groove filling portion to form a groove filling portion, the adhesion of the ceramic sub-core to both the first main surface side and the second main surface side is improved. Can be increased.

次に、本発明の配線基板の製造方法は、成膜充填工程において、コア本体及びセラミック副コアに第１主面側から樹脂フィルムを圧着して形成された第１側樹脂絶縁層および第１側溝埋め部が半硬化の状態で、第２主面側から樹脂フィルムを圧着して第２側樹脂絶縁層および第２側溝埋め部を形成するようにすることができる。   Next, in the method for manufacturing a wiring board of the present invention, in the film forming and filling step, the first side resin insulation layer formed by press-bonding a resin film from the first main surface side to the core body and the ceramic sub-core and the first With the side groove filling portion being semi-cured, the resin film can be pressure-bonded from the second main surface side to form the second side resin insulation layer and the second side groove filling portion.

上記本発明によると、第１側樹脂絶縁層および第１側溝埋め部が半硬化の状態で第２主面側から樹脂フィルムを圧着して第２側樹脂絶縁層および第２側溝埋め部を形成することによって、溝埋め部となる第１側溝埋め部と第２側溝埋め部とが連続・一体のものとなるため、コア基板と配線積層部との密着性がより高まることになる。   According to the present invention, the second side resin insulation layer and the second side groove filling portion are formed by pressure-bonding the resin film from the second main surface side with the first side resin insulation layer and the first side groove filling portion being semi-cured. By doing so, the first side groove filling portion and the second side groove filling portion, which become the groove filling portion, are continuous and integrated, so that the adhesion between the core substrate and the wiring laminated portion is further increased.

次に、本発明の配線基板の製造方法は、副コア収容工程前に、コア本体の主面間を貫通する貫通孔として形成された副コア収容部の第２主面側の開口を、表面に粘着剤を有するシート材で、該粘着剤が副コア収容部の内側に露出するように塞ぐ工程を行い、副コア収容工程では、セラミック副コアを、副コア収容部の第１主面側の開口から収容するとともに粘着剤に固着させることで第２主面側から支持するようにすることができる。   Next, in the method for manufacturing a wiring board according to the present invention, before the sub-core housing step, the opening on the second main surface side of the sub-core housing portion formed as a through hole penetrating between the main surfaces of the core body is formed on the surface. A sheet material having a pressure sensitive adhesive on the first core surface side of the secondary core housing portion, wherein the adhesive is exposed to the inside of the secondary core housing portion. It can be supported from the second main surface side by being accommodated from the opening and being fixed to the adhesive.

上記本発明によると、粘着剤を有するシート材によりセラミック副コアを固着させて副コア収容部に収容することにより、樹脂絶縁層および溝埋め部を形成する前のセラミック副コアの位置決めを簡易かつ精度良く行うことができる。   According to the present invention, the ceramic sub-core is fixed by the sheet material having the adhesive and is accommodated in the sub-core accommodating portion, thereby easily and easily positioning the ceramic sub-core before forming the resin insulating layer and the groove filling portion. It can be performed with high accuracy.

次に、本発明の配線基板の製造方法は、
副コア収容工程前に、コア本体の両主面に形成された導体パターンのうち第１主面側の導体パターンに対してのみ、樹脂材料との密着性を向上させるための表面化学処理を施す工程と、副コア収容部の第２主面側の開口をシート材で塞ぐことにより、当該表面化学処理が施されていない第２主面側の導体パターンが粘着剤で覆われる工程とを行い、
副コア収容工程では、セラミック副コアの両主面に形成された導体パターンのうち、第１主面側の導体パターンに対してのみ予め表面化学処理が施されたセラミック副コアを副コア収容部に収容し、
成膜充填工程では、コア本体及びセラミック副コアに第１主面側から樹脂フィルムを圧着し、第１側樹脂絶縁層および第１側溝埋め部を形成する操作を行った後、コア本体及びセラミック副コアの第２主面に貼付されているシート材を剥離し、コア本体の第２主面側の導体パターン及びセラミック副コアの第２主面側の導体パターンに対して一括して表面化学処理を施す操作を行い、その後、コア本体及びセラミック副コアに第２主面側から樹脂フィルムを圧着し、第２側樹脂絶縁層および第２側溝埋め部を形成する操作を行うようにすることができる。 Next, the manufacturing method of the wiring board of the present invention includes
Prior to the sub-core accommodation step, only the conductor pattern on the first main surface side among the conductor patterns formed on both main surfaces of the core body is subjected to surface chemical treatment for improving adhesion with the resin material. And a step of covering the second main surface side conductor pattern not subjected to the surface chemical treatment with an adhesive by closing the opening on the second main surface side of the sub-core housing portion with a sheet material. ,
In the sub-core housing step, among the conductor patterns formed on both main surfaces of the ceramic sub-core, the ceramic sub-core that has been subjected to surface chemical treatment only for the conductor pattern on the first main surface side is used as the sub-core housing portion. Housed in
In the film-filling step, after the operation of forming a first side resin insulation layer and a first side groove filling portion by pressing a resin film on the core main body and the ceramic sub-core from the first main surface side, the core main body and the ceramic The sheet material affixed to the second main surface of the sub core is peeled off, and the surface chemistry is collectively performed on the conductor pattern on the second main surface side of the core body and the conductor pattern on the second main surface side of the ceramic sub core. An operation for performing the treatment is performed, and then, an operation of pressing the resin film on the core main body and the ceramic sub-core from the second main surface side to form the second side resin insulating layer and the second side groove filling portion is performed. Can do.

樹脂材料との密着性を向上させるための表面化学処理（例えば、粗化処理）を施したコア本体またはセラミック副コアの導体パターンに粘着剤を接触させてシール材を貼付した場合、粘着剤が付着したことによって、シール材を剥離した後の導体パターンが表面化学処理の効果を消失してしまうような事態（例えば、粗化面の凹凸を粘着剤が埋めてしまうような事態）が起こり得る。そこで、上記本発明に示した順序に従ってコア本体およびセラミック副コアの導体パターンに表面化学処理を施すことによって、そのような事態を回避し得る。   When the adhesive is applied to the conductor pattern of the core body or ceramic sub-core that has been subjected to surface chemical treatment (for example, roughening treatment) to improve the adhesion to the resin material, Due to the adhesion, there may occur a situation in which the conductive pattern after peeling off the sealing material loses the effect of the surface chemical treatment (for example, a situation in which the unevenness of the roughened surface is filled with an adhesive). . Therefore, such a situation can be avoided by subjecting the conductor pattern of the core body and the ceramic sub-core to the surface chemical treatment according to the order shown in the present invention.

本発明の配線基板の実施形態を、図面を参照しながら説明する。図１は、配線基板１の断面構造を概略的に表す図である。なお、本実施形態において板状の部材は、図中で上側に表れている面を第１主面ＭＰ１とし、下側に表れている面を第２主面ＭＰ２とする。配線基板１は、コア基板ＣＢのうち半田バンプ７の下部領域に、積層セラミックコンデンサとして構成されたセラミック副コア３を有しており、半導体集積回路素子（ＩＣチップ）Ｃのスイッチングノイズの低減や動作電源電圧の安定化を図るうえで、ＩＣチップＣとセラミック副コア（積層セラミックコンデンサ）３との間の配線長の短縮化により、配線のインダクタンス成分の減少に寄与している。また、絶縁材料からなるコア本体２よりも線膨張係数の小さいセラミックからなるセラミック副コア３が、コア基板ＣＢのうち半田バンプ７の下部領域に設けられることにより、ＩＣチップＣとの線膨張係数差を縮減し、熱応力による断線等を生じ難くしている。以下、詳細な説明を行う。   An embodiment of a wiring board of the present invention will be described with reference to the drawings. FIG. 1 schematically shows a cross-sectional structure of the wiring board 1. In the present embodiment, the plate-like member has a surface appearing on the upper side in the drawing as the first main surface MP1 and a surface appearing on the lower side as the second main surface MP2. The wiring substrate 1 has a ceramic sub-core 3 configured as a multilayer ceramic capacitor in a lower region of the solder bump 7 in the core substrate CB, so that switching noise of the semiconductor integrated circuit element (IC chip) C can be reduced. In order to stabilize the operating power supply voltage, the wiring length between the IC chip C and the ceramic sub-core (multilayer ceramic capacitor) 3 is shortened, thereby contributing to the reduction of the wiring inductance component. Further, the ceramic sub-core 3 made of ceramic having a smaller linear expansion coefficient than the core body 2 made of an insulating material is provided in the lower region of the solder bump 7 in the core substrate CB, so that the linear expansion coefficient with the IC chip C is increased. The difference is reduced to make it difficult to cause disconnection due to thermal stress. Detailed description will be given below.

図２は、ＩＣチップＣと主基板（マザーボード等）ＧＢとの間に配置された配線基板１を表す図である。ＩＣチップＣは、信号端子，電源端子，グランド端子を第２主面に有し（図示せず）、配線基板１の第１主面ＭＰ１に形成された半田バンプ７（Ｐｂ−Ｓｎ系，Ｓｎ−Ａｇ系，Ｓｎ−Ｓｂ系，Ｓｎ−Ｚｎ系の半田等）にフリップチップ接続されている。また、ＩＣチップＣと配線基板１の第１主面ＭＰ１の間には、半田バンプ７の熱疲労寿命を向上させるために、熱硬化性樹脂からなるアンダーフィル材（図示せず）が充填形成される。他方、主基板（マザーボード等）ＧＢは、セラミック粒子や繊維をフィラーとして強化された樹脂材料を主体に構成されており、配線基板１の第２主面ＭＰ２に形成された半田ボールＢＬを介して端子パッド５６に接続されている。   FIG. 2 is a diagram showing the wiring board 1 arranged between the IC chip C and the main board (motherboard or the like) GB. The IC chip C has a signal terminal, a power supply terminal, and a ground terminal on the second main surface (not shown), and solder bumps 7 (Pb-Sn series, Sn) formed on the first main surface MP1 of the wiring board 1. -Ag-based, Sn-Sb-based, Sn-Zn-based solder, etc.). Also, an underfill material (not shown) made of a thermosetting resin is filled between the IC chip C and the first main surface MP1 of the wiring board 1 in order to improve the thermal fatigue life of the solder bumps 7. Is done. On the other hand, the main board (motherboard or the like) GB is mainly composed of a resin material reinforced with ceramic particles and fibers as fillers, and via solder balls BL formed on the second main surface MP2 of the wiring board 1. It is connected to the terminal pad 56.

図３は、配線基板１の第１主面ＭＰ１を表す図である。半田バンプ７は、格子状（あるいは千鳥状でもよい）に配列しており、このうち、中央部には電源端子７ａとグランド端子７ｂとが互い違いに配置され、また、これらを取り囲む形で信号端子７ｓが配置されている。これらは、ＩＣチップＣの端子に対応する。   FIG. 3 is a diagram illustrating the first main surface MP1 of the wiring board 1. FIG. The solder bumps 7 are arranged in a grid pattern (or may be a staggered pattern). Among these, the power terminals 7a and the ground terminals 7b are alternately arranged in the center, and the signal terminals surround the signal terminals. 7s is arranged. These correspond to the terminals of the IC chip C.

コア本体２は、耐熱性樹脂板（例えば、ビスマレイミド−トリアジン樹脂板）や繊維強化樹脂板（例えば、ガラス繊維強化エポキシ樹脂）等で板状に構成される。コア本体２内に配線パターン（内層パターン）が形成されていてもよい。このように構成すれば、配線基板１のよりいっそうの高機能化を図ることができる。また、コア本体２は、コアに対して薄い絶縁層を積層することで形成されていてもよい。そして、半田バンプ７の下部領域を含む位置には、主面ＭＰ１，ＭＰ２間を貫通する副コア収容部２５（貫通孔）が形成され、その内部には板状のセラミック副コア３が収容され、コア基板ＣＢを為している。   The core body 2 is configured in a plate shape with a heat-resistant resin plate (for example, bismaleimide-triazine resin plate), a fiber reinforced resin plate (for example, glass fiber reinforced epoxy resin), or the like. A wiring pattern (inner layer pattern) may be formed in the core body 2. If comprised in this way, the further functional enhancement of the wiring board 1 can be achieved. The core body 2 may be formed by laminating a thin insulating layer on the core. A sub-core accommodating portion 25 (through hole) penetrating between the main surfaces MP1 and MP2 is formed at a position including the lower region of the solder bump 7, and a plate-shaped ceramic sub-core 3 is accommodated therein. The core substrate CB is used.

セラミック副コア３は、積層セラミックコンデンサとして構成されている。これは、複数のセラミック層３３と複数の電極導体層３６，３７とが交互に積層されたものである。電極導体層３６，３７は、一方を電源端子７ａに対応する電源側電極導体層とし、他方をグランド端子７ｂに対応するグランド側電極導体層として、セラミック層３３により隔てられた形で直流的に分離されて積層方向に交互に配列している。また、セラミック副コアの各主面ＭＰ１，ＭＰ２には、電源側電極導体層またはグランド側電極導体層と繋がるメタライズパッド３１、及びそれを取り囲むダムメタライズ層３９が形成されている。   The ceramic sub-core 3 is configured as a multilayer ceramic capacitor. In this example, a plurality of ceramic layers 33 and a plurality of electrode conductor layers 36 and 37 are alternately stacked. One of the electrode conductor layers 36 and 37 is a power supply side electrode conductor layer corresponding to the power supply terminal 7a, and the other is a ground side electrode conductor layer corresponding to the ground terminal 7b. They are separated and arranged alternately in the stacking direction. Further, a metallized pad 31 connected to the power-side electrode conductor layer or the ground-side electrode conductor layer and a dam metallized layer 39 surrounding the metallized pad 31 are formed on the main surfaces MP1 and MP2 of the ceramic sub-core.

具体的には、図１１の面内方向の断面図に示すように、電極導体層３６が面内に拡がっている層では（図１１（ａ）参照）、面内に拡がった電極導体層３６と、セラミック層３３を隔てた上下に設けられたもう一方の電極導体層３７に接続される貫通導体３２と、が互いに分離されており、その隙間がセラミック層３３の一部で埋められている。これに対し、電極導体層３７が面内に拡がっている層では（図１１（ｂ）参照）、面内に拡がった電極導体層３７と、セラミック層３３を隔てた上下に設けられたもう一方の電極導体層３６に接続される貫通導体３２と、が互いに分離されており、その隙間がセラミック層３３の一部で埋められている。このような構造によって、セラミック副コア３は、積層セラミックコンデンサとして機能する。   Specifically, as shown in the cross-sectional view in the in-plane direction of FIG. 11, in the layer in which the electrode conductor layer 36 extends in the plane (see FIG. 11A), the electrode conductor layer 36 expanded in the plane. And the through conductor 32 connected to the other electrode conductor layer 37 provided above and below the ceramic layer 33 are separated from each other, and the gap is filled with a part of the ceramic layer 33. . On the other hand, in the layer in which the electrode conductor layer 37 extends in the plane (see FIG. 11B), the electrode conductor layer 37 expanded in the plane and the other provided above and below the ceramic layer 33. The through conductors 32 connected to the electrode conductor layer 36 are separated from each other, and the gap is filled with a part of the ceramic layer 33. With such a structure, the ceramic sub-core 3 functions as a multilayer ceramic capacitor.

このような積層セラミックコンデンサは、セラミック材料と金属材料との同時焼成によって得ることができる。すなわち、図１２に示すように、セラミック材料の粉末を含有したセラミックグリーンシート（セラミック層３３となる）に、パンチングあるいはレーザ穿孔等により貫通孔を形成して、金属材料の粉末を含有した金属ペーストを印刷塗布によって、貫通孔を充填するとともに（貫通導体３２となる）、その表面に電極導体層３６，３７、メタライズパッド３１、ダムメタライズ層３９となるパターンを形成することで得られるセラミック板単位３Ｐを積層し、積層体を同時焼成することにより積層セラミックコンデンサを得ることができる。電極導体層３６同士あるいは３７同士は、貫通導体３２により積層方向に連結されており、これらは金属ペーストの印刷パターニング時に互いに分離されて形成される。   Such a multilayer ceramic capacitor can be obtained by simultaneous firing of a ceramic material and a metal material. That is, as shown in FIG. 12, a metal paste containing a metal material powder is formed by forming a through hole in a ceramic green sheet containing the ceramic material powder (which becomes the ceramic layer 33) by punching or laser drilling. The ceramic plate unit obtained by filling the through-holes by printing and coating (to become the through conductors 32) and forming the patterns to be the electrode conductor layers 36 and 37, the metallized pads 31 and the dam metallized layer 39 on the surface thereof A laminated ceramic capacitor can be obtained by laminating 3P and simultaneously firing the laminated body. The electrode conductor layers 36 or 37 are connected to each other in the stacking direction by the through conductors 32, and these are formed to be separated from each other during the printing patterning of the metal paste.

セラミック層３３を構成するセラミック材料としては、アルミナ，窒化珪素，窒化アルミニウム等や、ホウケイ酸系ガラス，ホウケイ酸鉛系ガラスにアルミナ等の無機セラミックフィラーを４０重量部以上６０重量部以下添加したガラスセラミック等を使用できる。また、メタライズパッド３１、貫通導体３２、電極導体層３６，３７、ダムメタライズ層３９を構成する金属材料としては、ＮｉまたはＡｇを主成分とする金属を用いることができる。また、メタライズパッド３１及びダムメタライズ層３９の表面には、Ｃｕメッキが施されている。   The ceramic material constituting the ceramic layer 33 includes alumina, silicon nitride, aluminum nitride or the like, or borosilicate glass or lead borosilicate glass added with 40 to 60 parts by weight of an inorganic ceramic filler such as alumina. Ceramic etc. can be used. Moreover, as a metal material which comprises the metallization pad 31, the penetration conductor 32, the electrode conductor layers 36 and 37, and the dam metallization layer 39, the metal which has Ni or Ag as a main component can be used. Further, Cu plating is applied to the surfaces of the metallized pad 31 and the dam metallized layer 39.

本実施形態のセラミック副コア３（積層セラミックコンデンサ）は、縦１２．０ｍｍ×横１２．０ｍｍ×厚さ０．８ｍｍの矩形平板状である。なお、セラミック副コア３の厚さは、０．２ｍｍ以上１．０ｍｍ以下であることが好ましい。仮に、０．２ｍｍ未満であると、その上部にある半田バンプ７に搭載されるＩＣチップＣを確実に支持できなくなる。他方、１．０ｍｍを越えると、配線基板１が肉厚になってしまう。また、セラミック副コア３は、四隅が面取りされている。   The ceramic sub-core 3 (multilayer ceramic capacitor) of this embodiment has a rectangular flat plate shape of 12.0 mm long × 12.0 mm wide × 0.8 mm thick. In addition, it is preferable that the thickness of the ceramic subcore 3 is 0.2 mm or more and 1.0 mm or less. If it is less than 0.2 mm, the IC chip C mounted on the solder bump 7 on the upper part cannot be reliably supported. On the other hand, if it exceeds 1.0 mm, the wiring board 1 becomes thick. The ceramic sub-core 3 is chamfered at the four corners.

図１に戻り、副コア収容部２５内でセラミック副コア３とコア本体部２との隙間をなす空間には、樹脂材料からなる溝埋め部４が充填形成されている。この溝埋め部４は、各主面ＭＰ１，ＭＰ２側に形成された配線積層部Ｌ１，Ｌ２の最下層の樹脂絶縁層Ｂ１１，Ｂ２１のそれぞれと連続・一体のものとして構成されており、セラミック副コア３をコア本体部２に対して固定するとともに、セラミック副コア３とコア本体部２との面内方向及び厚さ方向の線膨張係数差を自身の弾性変形により吸収する役割を果たす。また、樹脂絶縁層Ｂ１１，Ｂ２１と連続・一体に構成されているため、コア基板ＣＢと配線積層部Ｌ１，Ｌ２との密着性が高いものとなっている。   Returning to FIG. 1, a groove filling portion 4 made of a resin material is filled and formed in a space forming a gap between the ceramic sub core 3 and the core main body portion 2 in the sub core housing portion 25. The groove filling portion 4 is configured to be continuous and integral with the lowermost resin insulation layers B11 and B21 of the wiring laminated portions L1 and L2 formed on the main surfaces MP1 and MP2, respectively. While fixing the core 3 with respect to the core main-body part 2, it plays the role which absorbs the linear expansion coefficient difference of the in-plane direction and thickness direction of the ceramic subcore 3 and the core main-body part 2 by own elastic deformation. Further, since the resin insulating layers B11 and B21 are continuously and integrally formed, the adhesiveness between the core substrate CB and the wiring laminated portions L1 and L2 is high.

コア基板ＣＢの両主面ＭＰ１，ＭＰ２上に設けられた配線積層部Ｌ１，Ｌ２は、樹脂絶縁層Ｂ１１〜Ｂ１４，Ｂ２１〜Ｂ２４と導体層Ｍ１１〜Ｍ１４，Ｍ２１〜Ｍ２４とが交互に積層された構造を有する。導体層Ｍ１１〜Ｍ１４，Ｍ２１〜Ｍ２４は、Ｃｕメッキからなる配線５１，５３やパッド５５，５６などにより構成されている。導体層Ｍ１１〜Ｍ１４，Ｍ２１〜Ｍ２４間は、ビア導体６によって層間接続がなされており、これによって、パッド５５からパッド５６への導通経路（信号用，電源用，グランド用）が形成されている。また、パッド５５，５６は半田バンプ７や半田ボールＢＬを形成するためのものであり、その表面にはＮｉ−Ａｕメッキが施されている。   In the wiring laminated portions L1 and L2 provided on both main surfaces MP1 and MP2 of the core substrate CB, the resin insulating layers B11 to B14 and B21 to B24 and the conductor layers M11 to M14 and M21 to M24 are alternately laminated. It has a structure. The conductor layers M11 to M14, M21 to M24 are configured by wirings 51 and 53 made of Cu plating, pads 55 and 56, and the like. Between the conductor layers M11 to M14 and M21 to M24, interlayer connection is made by the via conductor 6, thereby forming a conduction path (for signal, power supply, and ground) from the pad 55 to the pad 56. . The pads 55 and 56 are for forming the solder bumps 7 and the solder balls BL, and the surface thereof is Ni-Au plated.

樹脂絶縁層Ｂ１１〜Ｂ１４，Ｂ２１〜Ｂ２４は、エポキシ樹脂等の樹脂材料からなり、誘電率や絶縁耐圧を調整するシリカ粉末等の無機フィラーを適宜含んでいる。このうち樹脂絶縁層Ｂ１１〜Ｂ１３，Ｂ２１〜Ｂ２３は、ビルドアップ層，ビア層とも呼ばれ、導体層Ｍ１１〜Ｍ１４，Ｍ２１〜Ｍ２４間を絶縁するとともに、層間接続のためのビア導体６が貫通形成されている。他方、樹脂絶縁層Ｂ１４，Ｂ２４は、ソルダーレジスト層であり、パッド５５，５６を露出させるための開口が形成されている。また、樹脂絶縁層Ｂ１１，Ｂ２１は、コア基板ＣＢにおけるセラミック副コア３とコア本体部２との隙間を充填する溝埋め部４と連続・一体に形成されている。   The resin insulating layers B11 to B14 and B21 to B24 are made of a resin material such as an epoxy resin, and appropriately include an inorganic filler such as silica powder that adjusts the dielectric constant and dielectric strength. Among these, the resin insulating layers B11 to B13 and B21 to B23 are also called build-up layers and via layers, and insulate the conductor layers M11 to M14 and M21 to M24, and the via conductor 6 for interlayer connection is formed through. Has been. On the other hand, the resin insulating layers B14 and B24 are solder resist layers, and openings for exposing the pads 55 and 56 are formed. The resin insulating layers B11 and B21 are formed continuously and integrally with the groove filling portion 4 that fills the gap between the ceramic sub-core 3 and the core body portion 2 in the core substrate CB.

また、コア基板ＣＢのコア本体部２及び樹脂絶縁層Ｂ１１，Ｂ２１には、貫通孔が形成され、その内壁には配線積層部Ｌ１，Ｌ２間の導通を図るスルーホール導体２１が形成されている。このスルーホール導体２１は、信号端子７ｓに対応するものである。スルーホール導体２１の内側には、シリカフィラーなどの無機フィラーを含むエポキシ系の樹脂からなる樹脂製穴埋め材２３が充填形成されており、スルーホール導体２１の端部にはＣｕメッキからなる蓋導体５２が形成されている。なお、スルーホール導体２１及び蓋導体５２が形成された、コア基板を中心とする導体層Ｍ１２からＭ２２までの領域はコア領域ＣＲと称される。   Further, a through hole is formed in the core main body portion 2 and the resin insulating layers B11 and B21 of the core substrate CB, and a through-hole conductor 21 is formed on the inner wall thereof to achieve conduction between the wiring laminated portions L1 and L2. . The through-hole conductor 21 corresponds to the signal terminal 7s. Inside the through-hole conductor 21, a resin hole filling material 23 made of an epoxy resin containing an inorganic filler such as a silica filler is filled and formed, and the end portion of the through-hole conductor 21 is a lid conductor made of Cu plating. 52 is formed. In addition, the area | region from the conductor layers M12 to M22 centering on a core board | substrate in which the through-hole conductor 21 and the cover conductor 52 were formed is called core area | region CR.

次に、本発明の配線基板の製造方法の実施形態を、図面を参照しながら説明する。図４〜図１０は、配線基板１の製造工程を表す図である。   Next, an embodiment of a method for manufacturing a wiring board according to the present invention will be described with reference to the drawings. 4-10 is a figure showing the manufacturing process of the wiring board 1. FIG.

工程１では、コア本体部２の両主面ＭＰ１，ＭＰ２に導体パターン５４（導体層Ｍ１１）を形成する。これには、縦４００ｍｍ×横４００ｍｍ×厚み０．８ｍｍの耐熱性樹脂板（例えばビスマレイミド−トリアジン樹脂板）または繊維強化樹脂板（例えばガラス繊維強化エポキシ樹脂）の両主面に厚み３５μｍの銅箔が貼付された銅貼積層板を用いる。銅箔は、マスク材を用いてパターンエッチングされて、導体パターン５４となる。   In step 1, a conductor pattern 54 (conductor layer M11) is formed on both main surfaces MP1 and MP2 of the core body 2. For this purpose, a heat-resistant resin plate (for example, bismaleimide-triazine resin plate) having a length of 400 mm, a width of 400 mm, and a thickness of 0.8 mm, or a fiber-reinforced resin plate (for example, glass fiber-reinforced epoxy resin) on both main surfaces has a thickness of 35. A copper-clad laminate with a foil attached is used. The copper foil is pattern-etched using a mask material to form a conductor pattern 54.

工程２では、主面ＭＰ１，ＭＰ２間を貫通する貫通孔をルータにより形成して、副コア収容部２５を設ける。副コア収容部２５となる貫通孔は、一辺が１４．０ｍｍで四隅にフィレットを有する断面略正方形状の孔である。また、副コア収容部２５（貫通孔）の側壁に対しては、過マンガン酸カリウム等により粗化処理を施すことにより、後に充填される溝埋め部４との密着性を向上させることができる。更には、有機系化合物（カップリング剤）を塗布しても良い。   In step 2, a through-hole penetrating between the main surfaces MP1 and MP2 is formed by a router, and the sub-core housing portion 25 is provided. The through-hole serving as the sub-core housing part 25 is a hole having a substantially square cross section with one side of 14.0 mm and fillets at the four corners. In addition, the side wall of the sub-core housing part 25 (through hole) can be roughened with potassium permanganate or the like, thereby improving the adhesion with the groove filling part 4 to be filled later. . Furthermore, an organic compound (coupling agent) may be applied.

工程３では、コア本体２の両主面ＭＰ１，ＭＰ２に形成された導体パターン５４のうち、第１主面ＭＰ１側の導体パターン５４に対してのみ、樹脂材料との密着性を向上させるための表面化学処理を施す。このような表面化学処理の例としては、銅表面を粗化するＣｕ粗化処理（公知のマイクロエッチング法や黒化処理等の方法）が挙げられる。銅表面を粗化させることで、アンカー効果により配線積層部Ｌ１の最下層の樹脂絶縁層Ｂ１１との密着性が十分なものとなる。この効果を十分に得るには、ＪＩＳ−Ｂ−０６０１に規定する十点平均粗さ（Ｒｚ）が０．３μｍ以上２０μｍ以下程度となるようにＣｕ粗化処理が施されていることが好ましい。また、Ｃｕ粗化処理が終了したら、洗浄処理を実施する。また、必要に応じて、シランカップリング剤を用いて、カップリング処理を行ってもよい。   In step 3, among the conductor patterns 54 formed on both main surfaces MP1 and MP2 of the core body 2, only the conductor pattern 54 on the first main surface MP1 side is improved in adhesion to the resin material. Surface chemical treatment is applied. Examples of such surface chemical treatment include Cu roughening treatment (a known method such as microetching or blackening treatment) for roughening the copper surface. By roughening the copper surface, the adhesion with the lowermost resin insulation layer B11 of the wiring laminated portion L1 becomes sufficient due to the anchor effect. In order to sufficiently obtain this effect, Cu roughening treatment is preferably performed so that the ten-point average roughness (Rz) specified in JIS-B-0601 is about 0.3 μm or more and 20 μm or less. When the Cu roughening process is completed, a cleaning process is performed. Moreover, you may perform a coupling process using a silane coupling agent as needed.

また、表面化学処理のその他の例としては、銅表面にＣｕとＳｎを含む合金からなる極薄の接着層を形成する処理を挙げることもできる。かかる処理によれば、銅表面を粗化させることなく、配線積層部Ｌ１の最下層の樹脂絶縁層Ｂ１１との密着性を十分なものとすることができる。具体的には、接着層は、ＣｕとＳｎに加えて第３の金属（Ａｇ，Ｚｎ，Ａｌ，Ｔｉ，Ｂｉ，Ｃｒ，Ｆｅ，Ｃｏ，Ｎｉ，Ｐｄ，Ａｕ，Ｐｔから選ばれる少なくとも１種の金属）からなる合金を含む。また、例えば、Ｃｕを１原子％以上５０原子％以下程度、Ｓｎを２０原子％以上９８原子％以下程度、第３の金属を１原子％以上５０原子％以下程度含むものである。また、接着層の厚さは、十分な密着効果を得るため０．００１μｍ以上１μｍ以下とするのがよい。   As another example of the surface chemical treatment, a treatment for forming an extremely thin adhesive layer made of an alloy containing Cu and Sn on the copper surface can also be mentioned. According to this process, the adhesiveness with the lowermost resin insulation layer B11 of the wiring laminated portion L1 can be made sufficient without roughening the copper surface. Specifically, the adhesive layer includes at least one selected from a third metal (Ag, Zn, Al, Ti, Bi, Cr, Fe, Co, Ni, Pd, Au, and Pt in addition to Cu and Sn. (Metal) alloy. Further, for example, Cu is contained in an amount of about 1 to 50 atomic percent, Sn is contained in an amount of about 20 to 98 atomic percent, and a third metal is contained in an amount of about 1 to 50 atomic percent. The thickness of the adhesive layer is preferably 0.001 μm or more and 1 μm or less in order to obtain a sufficient adhesion effect.

工程４では、副コア収容部２５（貫通孔）の第２主面ＭＰ２側の開口２５Ｂを、表面に粘着剤ａｄを有する粘着シート材Ｓで、粘着剤ａｄが副コア収容部２５の内側に露出するように塞ぐ。粘着シート材Ｓとしては、粘着材ａｄの粘着力が８．０N／25mm以上であるものが好ましい（１８０°引きはがし法（JIS Z 0237）により測定）。なお、単位［N／25mm］は、幅２５ｍｍの粘着シート材を試料として測定された力を意味する。粘着シート材Ｓの材質（基材）は、例えばポリエステルやポリイミド、ＰＥＴ等の樹脂シートを用いることができる。また、粘着シート材Ｓの表面に付される粘着剤ａｄは、例えばシリコン系の粘着剤、アクリル系の粘着剤、熱可塑性ゴム系の粘着剤などを用いることができる。   In step 4, the opening 25 </ b> B on the second main surface MP <b> 2 side of the sub core housing part 25 (through hole) is made of an adhesive sheet material S having the adhesive ad on the surface, and the adhesive ad is placed inside the sub core housing part 25. Block it to be exposed. As the adhesive sheet material S, an adhesive material ad having an adhesive strength of 8.0 N / 25 mm or more is preferable (measured by 180 ° peeling method (JIS Z 0237)). The unit [N / 25mm] means a force measured using a 25 mm wide adhesive sheet material as a sample. As the material (base material) of the pressure-sensitive adhesive sheet material S, for example, a resin sheet such as polyester, polyimide, or PET can be used. As the adhesive ad applied to the surface of the adhesive sheet material S, for example, a silicon adhesive, an acrylic adhesive, a thermoplastic rubber adhesive, or the like can be used.

工程５は、本発明の副コア収容工程に該当する。本工程では、副コア収容部２５の第１主面ＭＰ１側の開口２５Ａからセラミック副コア３を収容するとともに粘着剤ａｄに固着させる。これにより、セラミック副コア３は、第２主面ＭＰ２側から支持される。セラミック副コア３の収容は、マウント装置を用いることにより、セラミック副コア３を精度良く収容することができる。   Step 5 corresponds to the sub-core accommodation step of the present invention. In this step, the ceramic sub-core 3 is accommodated from the opening 25A on the first main surface MP1 side of the sub-core accommodating portion 25 and is fixed to the adhesive ad. Thereby, the ceramic sub-core 3 is supported from the second main surface MP2 side. The ceramic sub-core 3 can be accommodated with high accuracy by using a mounting device.

また、ここで収容するセラミック副コア３は、第１主面ＭＰ１側のメタライズパッド３１及び導体パターン３９に対してのみ予めＣｕ粗化処理が施されている。図に示すように、コア本体２の第２主面ＭＰ２側の導体パターン５４およびセラミック副コア３の第２主面ＭＰ２側のメタライズパッド３１及び導体パターン３９には、粘着シート材Ｓの粘着剤ａｄが接着するが、これらには上記したＣｕ粗化処理が施されていないため、粗化面の凹凸に粘着剤ａｄが埋まってしまうようなことはない。   Further, the ceramic sub-core 3 accommodated here is preliminarily subjected to Cu roughening treatment only on the metallized pad 31 and the conductor pattern 39 on the first main surface MP1 side. As shown in the figure, the adhesive of the adhesive sheet material S is applied to the conductor pattern 54 on the second main surface MP2 side of the core body 2 and the metallized pad 31 and the conductor pattern 39 on the second main surface MP2 side of the ceramic sub-core 3. Although ad adhere | attaches, since the above-mentioned Cu roughening process is not performed to these, the adhesive ad is not buried in the unevenness | corrugation of a roughening surface.

なお、配線基板１の製造工程は、図１３（上方から見た図）に示すように、配線基板１となるべき製品部分が複数配列した製品部分領域ＰＲと、これを取り囲む捨代部分領域ＤＲとから構成される多数個取り製造基板Ｒに対して行われる。図１３は、工程５の終了時点、すなわちセラミック副コア３を副コア収容部２５に収容した時点の様子を表す。コア本体２とセラミック副コア３との間には隙間が生じており、以後の工程でこの隙間が樹脂絶縁層Ｂ１１，Ｂ２１と連続する樹脂材料に充填されて溝埋め部４が形成される。また、副コア収容部（貫通孔）２５及びセラミック副コア３は、矩形状に形成されるとともに、隙間に充填された溝埋め部４に亀裂を生じさせないために、副コア収容部（貫通孔）２５の角部分にはフィレットが施され、セラミック副コア３の角部分には面取りが施されている。   As shown in FIG. 13 (viewed from above), the manufacturing process of the wiring substrate 1 includes a product partial region PR in which a plurality of product portions to be the wiring substrate 1 are arranged, and an abandoned partial region DR surrounding the product partial region DR. This is performed on a multi-piece manufacturing substrate R composed of FIG. 13 shows a state at the end of step 5, that is, when the ceramic sub-core 3 is accommodated in the sub-core accommodating portion 25. A gap is formed between the core body 2 and the ceramic sub-core 3, and the gap filling portion 4 is formed by filling the gap with a resin material continuous with the resin insulating layers B11 and B21 in the subsequent processes. Further, the sub-core housing portion (through hole) 25 and the ceramic sub-core 3 are formed in a rectangular shape, and the sub-core housing portion (through-hole) is formed so as not to cause a crack in the groove filling portion 4 filled in the gap. ) 25 corners are filled, and the ceramic sub-core 3 corners are chamfered.

工程６ないし８は、本発明の成膜充填工程に該当する。まず、工程６では、副コア収容部２５内にセラミック副コア３が粘着シート材Ｓにより第２主面ＭＰ２側から支持された状態で、コア本体２及びセラミック副コア３に第１主面ＭＰ１側から樹脂フィルム９１を圧着することで、第１主面ＭＰ１側の配線積層部Ｌ１の最下層となる樹脂絶縁層Ｂ１１を形成するとともに、コア本体２とセラミック副コア３の隙間のうち第１主面側の隙間を埋める、当該樹脂絶縁層Ｂ１１と連続する第１側溝埋め部４１を充填形成する。   Steps 6 to 8 correspond to the film-filling step of the present invention. First, in step 6, the ceramic main core 3 is supported by the adhesive sheet material S from the second main surface MP2 side in the sub core housing portion 25, and the first main surface MP1 is attached to the core body 2 and the ceramic sub core 3. By pressing the resin film 91 from the side, the resin insulating layer B11 that is the lowest layer of the wiring laminated portion L1 on the first main surface MP1 side is formed, and the first of the gaps between the core body 2 and the ceramic sub-core 3 is formed. A first side groove filling portion 41 that is continuous with the resin insulating layer B11 and fills the gap on the main surface side is filled and formed.

樹脂フィルム９１は、離型シート９２が付された状態の離型シート付き樹脂フィルム９の状態で、真空ラミネーション法を実現するラミネート機により、減圧雰囲気下で、コア本体２及びセラミック副コア３の第１主面に圧着される。圧着はラミネート機の加熱・加圧ロールにより行われ、これにより、樹脂フィルム９１の一部が、コア本体２とセラミック副コア３の隙間のうち第１主面ＭＰ１側の途中（例えば、半分程度）まで充填され、第１溝埋め部４１となる。また、かかる隙間のうち、第１溝埋め部４１が形成されなかった第２主面ＭＰ２側の残部４Ｓは、後の工程で埋められる。かかる方法によれば、充填される第１溝埋め部４１が隙間の途中で止まるため、第２主面ＭＰ２側へ潜り込むこともない。   The resin film 91 is in a state of the release sheet-attached resin film 9 with the release sheet 92 attached thereto, and the core body 2 and the ceramic sub-core 3 are formed under a reduced pressure atmosphere by a laminating machine that realizes a vacuum lamination method. Crimped to the first main surface. The pressure bonding is performed by a heating / pressurizing roll of a laminating machine, whereby a part of the resin film 91 is in the middle of the gap between the core body 2 and the ceramic sub-core 3 on the first main surface MP1 side (for example, about half). ) Until the first groove filling portion 41 is formed. Moreover, the remaining part 4S by the side of 2nd main surface MP2 in which the 1st groove | channel filling part 41 was not formed among this clearance gap is filled by a subsequent process. According to this method, the first groove filling portion 41 to be filled stops in the middle of the gap, so that it does not sink into the second main surface MP2 side.

また、離型シート付き樹脂フィルム９における樹脂フィルム９１の厚さは、１００μｍ程度とされており、第１溝埋め部４を形成する必要から、他の樹脂絶縁層Ｂ１２〜Ｂ１３，Ｂ２２〜Ｂ２３をラミネート形成する場合の樹脂フィルムよりも厚いものが用いられる。具体的には、樹脂フィルム９１の厚さは、樹脂絶縁層Ｂ１１の硬化前の厚さに対しては１．５倍以上２倍以下程度、形成する樹脂絶縁層Ｂ１１の厚さに対しては３倍以上４倍以下程度、また、セラミック副コア３の板厚に対しては１０％以上２０％以上程度とされる。   Moreover, the thickness of the resin film 91 in the resin film 9 with a release sheet is about 100 μm, and since it is necessary to form the first groove filling portion 4, the other resin insulation layers B12 to B13 and B22 to B23 are formed. A film thicker than the resin film in the case of laminating is used. Specifically, the thickness of the resin film 91 is about 1.5 to 2 times the thickness of the resin insulation layer B11 before curing, and the thickness of the resin insulation layer B11 to be formed About 3 to 4 times, and the thickness of the ceramic sub-core 3 is about 10% to 20%.

工程７では、コア本体２及びセラミック副コア３の第２主面ＭＰ２に貼付されている粘着シート材Ｓを剥離する。粘着シート材Ｓの剥離後は、アルコール系溶剤（ＩＰＡ）等の有機溶媒により粘着剤ａｄの残渣を除去する。その後、コア本体２の第２主面ＭＰ２側の導体パターン５４及びセラミック副コア３の第２主面ＭＰ２側の導体パターン（メタライズパッド３１及びダムメタライズ層３９）に対し、後に形成される樹脂絶縁層Ｂ２１との密着性を高めるためのＣｕ粗化処理を施す。   In step 7, the pressure-sensitive adhesive sheet material S attached to the second main surface MP2 of the core body 2 and the ceramic sub-core 3 is peeled off. After peeling off the pressure-sensitive adhesive sheet material S, the residue of the pressure-sensitive adhesive ad is removed with an organic solvent such as an alcohol solvent (IPA). Thereafter, a resin insulation formed later on the conductor pattern 54 on the second main surface MP2 side of the core body 2 and the conductor pattern (metallized pad 31 and dam metallized layer 39) on the second main surface MP2 side of the ceramic sub-core 3. A Cu roughening treatment is performed to improve the adhesion with the layer B21.

工程８では、樹脂絶縁層Ｂ１１および第１側溝埋め部４１によりセラミック副コア３が第１主面ＭＰ１側から支持された状態で、コア本体２及びセラミック副コア３に第２主面ＭＰ２側から樹脂フィルム９１を圧着することで、第２主面ＭＰ２側の配線積層部Ｌ２の最下層となる樹脂絶縁層Ｂ２１を形成するとともに、コア本体２とセラミック副コア３の隙間のうち第１側溝埋め部４１に埋められていない残部４Ｓを埋めるように、当該側樹脂絶縁層Ｂ２１と連続する第２側溝埋め部４２を充填形成する。   In step 8, the ceramic sub-core 3 is supported from the first main surface MP1 side by the resin insulating layer B11 and the first side groove filling portion 41, and the core body 2 and the ceramic sub-core 3 from the second main surface MP2 side. The resin film 91 is pressure-bonded to form the resin insulating layer B21 which is the lowermost layer of the wiring laminated portion L2 on the second main surface MP2 side, and the first side groove in the gap between the core body 2 and the ceramic sub-core 3 is filled. A second side groove filling portion 42 continuous with the side resin insulation layer B21 is filled and formed so as to fill the remaining portion 4S not filled in the portion 41.

第２主面ＭＰ２側の樹脂フィルム９１の圧着も、第１主面ＭＰ１側と同様に、樹脂フィルム９１に離型シート９２が付された状態の離型シート付き樹脂フィルム９の状態で、真空ラミネーション法を実現するラミネート機により、減圧雰囲気下で行われる。また、かかる樹脂フィルム９１の圧着は、第１主面ＭＰ１側の樹脂絶縁層Ｂ１１および第１側溝埋め部４１が半硬化の状態で行われる。これにより、工程９に示すように、完全硬化後の第１側溝埋め部４１と第２側溝埋め部４２とが一体となって、コア本体２とセラミック副コア３との隙間を全て埋める溝埋め部４となる。なお、工程９の図は、樹脂フィルム９１から離型シート９２を剥離した後の図である。   The pressure bonding of the resin film 91 on the second main surface MP2 side is also performed in the state of the resin film 9 with the release sheet in a state where the release sheet 92 is attached to the resin film 91 in the same manner as the first main surface MP1 side. It is carried out under a reduced-pressure atmosphere by a laminating machine that realizes a lamination method. The pressure bonding of the resin film 91 is performed in a state where the resin insulating layer B11 on the first main surface MP1 side and the first side groove filling portion 41 are semi-cured. Thereby, as shown in Step 9, the first side groove filling portion 41 and the second side groove filling portion 42 after complete curing are integrated to fill the gap between the core body 2 and the ceramic sub-core 3. It becomes part 4. In addition, the figure of the process 9 is a figure after peeling the release sheet 92 from the resin film 91. FIG.

工程１０以降は、樹脂絶縁層Ｂ１１，Ｂ２１上に、導体層Ｍ１２〜Ｍ１４，Ｍ２２〜Ｍ２４と樹脂絶縁層Ｂ１２〜１４，Ｂ２２〜２４とを交互に積層して配線積層部Ｌ１，Ｌ２を形成する。これには、公知のビルドアップ工程（セミアディティブ法やフォトリソグラフィ技術などを組み合わせた工程）を用いることで実現できる。   In step 10 and subsequent steps, the conductive layers M12 to M14 and M22 to M24 and the resin insulating layers B12 to B14 and B22 to 24 are alternately stacked on the resin insulating layers B11 and B21 to form the wiring stacked portions L1 and L2. . This can be realized by using a known build-up process (a process in which a semi-additive method or a photolithography technique is combined).

工程１０では、レーザビアプロセスあるいはフォトビアプロセスなどの手法により、樹脂絶縁層Ｂ１１，Ｂ２１にビア孔６ａを穿設する。これにより、ビア孔６ａの底には、メタライズパッド３１が露出する。また、ビア孔６ａの形成後には、過マンガン酸カリウム等によりデスミア処理（樹脂残渣除去処理）が施されて、メタライズパッド３１の表面が洗浄される。ここで、メタライズパッド３１上には、上記工程によって樹脂絶縁層Ｂ１１，Ｂ２１の１層のみが形成されており、従来の如く特性の異なる複数の樹脂絶縁層が重なっていることがないため、ビア孔６ａの穿設およびデスミア処理を良好に行うことができる。   In step 10, via holes 6a are formed in the resin insulating layers B11 and B21 by a technique such as a laser via process or a photo via process. As a result, the metallized pad 31 is exposed at the bottom of the via hole 6a. In addition, after the via hole 6a is formed, a desmear process (resin residue removal process) is performed with potassium permanganate or the like, and the surface of the metallized pad 31 is cleaned. Here, only one layer of the resin insulating layers B11 and B21 is formed on the metallized pad 31 by the above process, and a plurality of resin insulating layers having different characteristics are not overlapped as in the prior art. Drilling of the hole 6a and desmearing can be performed satisfactorily.

工程１１では、コア基板ＣＢ及びその両主面ＭＰ１，ＭＰ２に形成された導体層Ｍ１１，Ｍ２１、樹脂絶縁層Ｂ１１，Ｂ２１を板厚方向に貫く形でドリル等により貫通孔ＴＨを穿設する。工程１２では、Ｃｕメッキ（無電解Ｃｕメッキ後に電解Ｃｕメッキ）を全面に施すことにより、ビア孔６ａ内を充填してビア導体６を形成するとともに、貫通孔ＴＨの内面にスルーホール導体２１を形成する。工程１３では、スルーホール導体２１の内側に樹脂製穴埋め材２３を充填し、更にＣｕメッキを全面に施すことにより、蓋導体５２を形成する。工程１４では、樹脂絶縁層Ｂ１１，Ｂ２１を覆うＣｕメッキをパターンエッチングすることにより、配線５１等をパターン形成する。   In step 11, a through hole TH is formed by a drill or the like so as to penetrate the core substrate CB and the conductor layers M11 and M21 and the resin insulating layers B11 and B21 formed on both main surfaces MP1 and MP2 in the plate thickness direction. In step 12, by applying Cu plating (electrolytic Cu plating after electroless Cu plating) to the entire surface, the via hole 6a is filled to form the via conductor 6, and the through hole conductor 21 is formed on the inner surface of the through hole TH. Form. In step 13, a resin conductor filling material 23 is filled inside the through-hole conductor 21, and further, Cu plating is applied to the entire surface to form a lid conductor 52. In step 14, the wiring 51 and the like are pattern-formed by pattern etching of Cu plating covering the resin insulating layers B11 and B21.

以上により、コア領域ＣＲが得られる。そして、同様に、樹脂絶縁層Ｂ１２〜Ｂ１４、Ｂ２２〜Ｂ２４と導体層Ｍ１３〜Ｍ１４、Ｍ２３〜Ｍ２４とを交互に積層し、樹脂絶縁層Ｂ１４，Ｂ２４にはレーザビアプロセスあるいはフォトビアプロセスなどの手法により開口を形成し、パッド５５，５６を露出させる。また、パッド５５，５６の表面にＮｉ−Ａｕメッキが施され、パッド５５には半田バンプ７が形成される。その後、電気的検査，外観検査等の所定の検査を経て、図１に示す配線基板１が完成する。   Thus, the core region CR is obtained. Similarly, the resin insulation layers B12 to B14 and B22 to B24 and the conductor layers M13 to M14 and M23 to M24 are alternately stacked, and the resin insulation layers B14 and B24 have a technique such as a laser via process or a photo via process. To form an opening and expose the pads 55 and 56. Further, Ni—Au plating is applied to the surfaces of the pads 55 and 56, and solder bumps 7 are formed on the pads 55. Thereafter, the wiring board 1 shown in FIG. 1 is completed through predetermined inspections such as electrical inspection and appearance inspection.

以上、本発明の実施形態について説明したが、本発明はこれらの形式に限定されるものではなく、これらに具現された発明と同一性の範囲内において適宜変更して実施し得る。   As mentioned above, although embodiment of this invention was described, this invention is not limited to these forms, In the range of the same identity as the invention embodied in these, it can change suitably and can implement.

本発明の配線基板の断面構造を概略的に表す図The figure which represents roughly the cross-section of the wiring board of this invention 半導体集積回路素子（ＩＣチップ）と主基板（マザーボード等）との間に配置された配線基板を表す図The figure showing the wiring board arrange | positioned between a semiconductor integrated circuit element (IC chip) and main boards (motherboard etc.) 配線基板の第１主面を表す図The figure showing the 1st principal surface of a wiring board 配線基板の製造工程を表す図Diagram showing manufacturing process of wiring board 図４に続く図Figure following Figure 4 図５に続く図Figure following Figure 5 図６に続く図Figure following Figure 6 図７に続く図Figure following Figure 7 図８に続く図Figure following Figure 8 図９に続く図Figure following Figure 9 セラミック副コア（積層セラミックコンデンサ）の面内方向の断面図Cross section in the in-plane direction of the ceramic sub-core (multilayer ceramic capacitor) セラミック副コア（積層セラミックコンデンサ）の製造工程を表す図Diagram showing the manufacturing process of ceramic sub-core (multilayer ceramic capacitor) 工程５（副コア収容工程）終了後の基板上面図Substrate top view after completion of step 5 (sub-core accommodation step) 従来の配線基板の製造工程を示す図The figure which shows the manufacturing process of the conventional wiring board

符号の説明Explanation of symbols

１ 配線基板
２ コア本体
２５ 副コア収容部（貫通孔）
３ セラミック副コア（積層セラミックコンデンサ）
３１ 導体パッド
３２ 貫通導体
３３ セラミック層
３６，３７ 電極導体層
４（４１，４２） 溝埋め部（第１側溝埋め部，第２側溝埋め部）
６ ビア導体
７ 半田バンプ（電源端子７ａ，グランド端子７ｂ，信号端子７ｓ）
ＣＢ コア基板
ＣＲ コア領域
Ｌ（Ｌ１，Ｌ２） 配線積層部
Ｂ 樹脂絶縁層
Ｂ１１ 最下層となる第１側樹脂絶縁層
Ｂ２１ 最下層となる第２側樹脂絶縁層
Ｍ 導体層
Ｍ１１ コア本体及びセラミック副コアの第１主面に形成された導体パターン
Ｍ２１ コア本体及びセラミック副コアの第２主面に形成された導体パターン
Ｍ１２ 第１側樹脂絶縁層上の導体層
Ｍ２２ 第２側樹脂絶縁層上の導体層
Ｃ 半導体集積回路素子（ＩＣチップ）
ＧＢ 主基板（マザーボード等）
Ｓ 粘着シート材
２５Ａ 第１主面側の開口
２５Ｂ 第２主面側の開口
DESCRIPTION OF SYMBOLS 1 Wiring board 2 Core main body 25 Sub core accommodating part (through-hole)
3 Ceramic sub-core (multilayer ceramic capacitor)
31 conductor pad 32 through conductor 33 ceramic layer 36, 37 electrode conductor layer 4 (41, 42) groove filling portion (first side groove filling portion, second side groove filling portion)
6 Via conductor 7 Solder bump (power terminal 7a, ground terminal 7b, signal terminal 7s)
CB Core substrate CR Core region L (L1, L2) Wiring laminate B Resin insulation layer B11 First side resin insulation layer B21 as the bottom layer Second side resin insulation layer M as the bottom layer Conductor layer M11 Core body and ceramic sub Conductor pattern M21 formed on the first main surface of the core Conductor pattern M12 formed on the second main surface of the core body and the ceramic sub-core Conductor layer M22 on the first side resin insulation layer On the second side resin insulation layer Conductor layer C Semiconductor integrated circuit element (IC chip)
GB main board (motherboard etc.)
S Adhesive sheet material 25A First main surface side opening 25B Second main surface side opening

Claims (8)

板状のコア本体に主面間を貫通する貫通孔あるいは第１主面に開口する凹部として副コア収容部が形成され、その内部にセラミック副コアが収容されたコア基板と、該コア基板の主面上に樹脂絶縁層と導体層とが交互に積層して形成された配線積層部と、を備える配線基板の製造方法であって、
前記セラミック副コアを、前記副コア収容部の第１主面の開口側から収容する副コア収容工程と、
前記コア本体及び前記セラミック副コアに第１主面側から樹脂材料を付着させることで、第１主面側の前記配線積層部の最下層となる樹脂絶縁層を形成するとともに、前記コア本体と前記セラミック副コアの隙間に当該樹脂絶縁層と連続する溝埋め部を充填形成する成膜充填工程と、
をこの順に含むことを特徴とする配線基板の製造方法。 A sub-core housing portion is formed in the plate-shaped core body as a through-hole penetrating between the main surfaces or a recess opening in the first main surface, and a ceramic substrate is accommodated therein, and a core substrate of the core substrate A wiring laminated part formed by alternately laminating resin insulating layers and conductor layers on a main surface, and a method of manufacturing a wiring board comprising:
A sub core housing step of housing the ceramic sub core from the opening side of the first main surface of the sub core housing portion;
By attaching a resin material from the first main surface side to the core main body and the ceramic sub-core, a resin insulating layer serving as a lowermost layer of the wiring laminated portion on the first main surface side is formed, and the core main body and A film-filling step of filling and forming a groove filling portion continuous with the resin insulating layer in the gap between the ceramic sub-cores;
A method of manufacturing a wiring board, comprising: 板状のコア本体に主面間を貫通する貫通孔として副コア収容部が形成され、その内部にセラミック副コアが収容されたコア基板と、該コア基板の主面上に樹脂絶縁層と導体層とが交互に積層して形成された配線積層部と、を備える配線基板の製造方法であって、
前記セラミック副コアを前記副コア収容部に収容する副コア収容工程と、
前記コア本体及び前記セラミック副コアに両主面側から交互に樹脂材料を付着させることで、両主面側の前記配線積層部の最下層となる樹脂絶縁層を各々形成するとともに、前記コア本体と前記セラミック副コアの隙間に当該両主面側の各樹脂絶縁層と連続する溝埋め部を充填形成する成膜充填工程と、
をこの順に含むことを特徴とする配線基板の製造方法。 A core substrate in which a sub-core accommodating portion is formed as a through-hole penetrating between main surfaces in a plate-shaped core body, and a ceramic sub-core is accommodated therein, and a resin insulating layer and a conductor on the main surface of the core substrate A wiring laminated portion formed by alternately laminating layers, and a method of manufacturing a wiring board comprising:
A sub-core housing step of housing the ceramic sub-core in the sub-core housing portion;
By alternately attaching a resin material to the core main body and the ceramic sub-core from both main surface sides, a resin insulating layer that is a lowermost layer of the wiring laminated portion on both main surface sides is formed, and the core main body And a film filling step for filling the gap between the ceramic sub-core with a groove filling portion continuous with the resin insulation layers on both main surfaces,
A method of manufacturing a wiring board, comprising: 前記成膜充填工程では、
前記コア本体の主面間を貫通する貫通孔として形成された前記副コア収容部内に前記セラミック副コアが第２主面側から支持された状態で、前記コア本体及び前記セラミック副コアに第１主面側から樹脂フィルムを圧着することで、第１主面側の前記配線積層部の最下層となる第１側樹脂絶縁層を形成するとともに、前記コア本体と前記セラミック副コアの隙間のうち少なくとも第１主面側の隙間を埋めるように、当該第１側樹脂絶縁層と連続する第１側溝埋め部を充填形成する操作と、
前記第１側樹脂絶縁層および前記第１側溝埋め部により前記セラミック副コアが第１主面側から支持された状態で、前記コア本体及び前記セラミック副コアに第２主面側から樹脂フィルムを圧着することで、第２主面側の前記配線積層部の最下層となる第２側樹脂絶縁層を形成するとともに、前記コア本体と前記セラミック副コアの隙間のうち前記第１側溝埋め部に埋められていない残部を埋めるように、当該第２側樹脂絶縁層と連続する第２側溝埋め部を充填形成する操作と、が行われる請求項１または２に記載の配線基板の製造方法。 In the film filling step,
In the state where the ceramic sub-core is supported from the second main surface side in the sub-core housing portion formed as a through hole penetrating between the main surfaces of the core main body, the core main body and the ceramic sub-core are first By crimping the resin film from the main surface side, a first side resin insulating layer which is the lowest layer of the wiring laminated portion on the first main surface side is formed, and among the gaps between the core body and the ceramic sub-core An operation of filling and forming the first side groove filling portion continuous with the first side resin insulation layer so as to fill at least the gap on the first main surface side;
In a state where the ceramic sub core is supported from the first main surface side by the first side resin insulation layer and the first side groove filling portion, a resin film is applied to the core body and the ceramic sub core from the second main surface side. By crimping, a second side resin insulation layer that is the lowermost layer of the wiring laminated portion on the second main surface side is formed, and the first side groove filling portion in the gap between the core body and the ceramic sub-core is formed. The method of manufacturing a wiring board according to claim 1, wherein an operation of filling and forming a second side groove filling portion continuous with the second side resin insulating layer is performed so as to fill a remaining portion that is not filled. 前記成膜充填工程では、前記コア本体及び前記セラミック副コアに第１主面側から樹脂フィルムを圧着して形成された前記第１側樹脂絶縁層および前記第１側溝埋め部が半硬化の状態で、第２主面側から樹脂フィルムを圧着して前記第２側樹脂絶縁層および前記第２側溝埋め部を形成する請求項３に記載の配線基板の製造方法。   In the film-filling step, the first-side resin insulation layer and the first-side groove filling portion formed by pressure-bonding a resin film from the first main surface side to the core body and the ceramic sub-core are in a semi-cured state The method for manufacturing a wiring board according to claim 3, wherein a resin film is pressure-bonded from the second main surface side to form the second side resin insulation layer and the second side groove filling portion. 前記副コア収容工程前に、前記コア本体の主面間を貫通する貫通孔として形成された前記副コア収容部の第２主面側の開口を、表面に粘着剤を有するシート材で、該粘着剤が前記副コア収容部の内側に露出するように塞ぐ工程を行い、
前記副コア収容工程では、前記セラミック副コアを、前記副コア収容部の第１主面側の開口から収容するとともに前記粘着剤に固着させることで第２主面側から支持する請求項３または４に記載の配線基板の製造方法。 Before the sub-core housing step, the opening on the second main surface side of the sub-core housing portion formed as a through-hole penetrating between the main surfaces of the core body is a sheet material having an adhesive on the surface, Performing a step of closing the pressure-sensitive adhesive so as to be exposed inside the sub-core housing portion;
The said sub core accommodation process WHEREIN: The said ceramic sub core is accommodated from the opening of the 1st main surface side of the said sub core accommodating part, and it is supported from the 2nd main surface side by making it adhere to the said adhesive. 5. A method for manufacturing a wiring board according to 4. 前記副コア収容工程前に、前記コア本体の両主面に形成された導体パターンのうち第１主面側の導体パターンに対してのみ、樹脂材料との密着性を向上させるための表面化学処理を施す工程と、前記副コア収容部の第２主面側の開口を前記シート材で塞ぐことにより、当該表面化学処理が施されていない第２主面側の導体パターンが前記粘着剤で覆われる工程とを行い、
前記副コア収容工程では、前記セラミック副コアの両主面に形成された導体パターンのうち、第１主面側の導体パターンに対してのみ予め前記表面化学処理が施された前記セラミック副コアを前記副コア収容部に収容し、
前記成膜充填工程では、前記コア本体及び前記セラミック副コアに第１主面側から樹脂フィルムを圧着し、前記第１側樹脂絶縁層および前記第１側溝埋め部を形成する操作を行った後、前記コア本体及び前記セラミック副コアの第２主面に貼付されている前記シート材を剥離し、前記コア本体の第２主面側の導体パターン及び前記セラミック副コアの第２主面側の導体パターンに対して一括して前記表面化学処理を施す操作を行い、その後、前記コア本体及び前記セラミック副コアに第２主面側から樹脂フィルムを圧着し、前記第２側樹脂絶縁層および前記第２側溝埋め部を形成する操作を行う請求項５に記載の配線基板の製造方法。 Surface chemical treatment for improving adhesion to the resin material only for the conductor pattern on the first main surface side among the conductor patterns formed on both main surfaces of the core body before the sub-core housing step And by covering the opening on the second main surface side of the sub-core housing portion with the sheet material, the conductor pattern on the second main surface side that has not been subjected to the surface chemical treatment is covered with the adhesive. And the process
In the sub-core housing step, the ceramic sub-core that has been subjected to the surface chemical treatment in advance only for the conductor pattern on the first main surface side among the conductor patterns formed on both main surfaces of the ceramic sub-core. Housed in the sub-core housing part,
In the film forming and filling step, after performing an operation of pressing a resin film on the core body and the ceramic sub-core from the first main surface side to form the first side resin insulating layer and the first side groove filling portion. The sheet material attached to the second main surface of the core main body and the ceramic sub core is peeled off, and the conductor pattern on the second main surface side of the core main body and the second main surface side of the ceramic sub core are removed. The conductor pattern is collectively subjected to the surface chemical treatment, and then a resin film is pressure-bonded to the core main body and the ceramic sub-core from the second main surface side, and the second side resin insulating layer and the The method for manufacturing a wiring board according to claim 5, wherein an operation for forming the second side groove filling portion is performed. 前記成膜充填工程後に、前記配線積層部の最下層となる単層の樹脂絶縁層に、当該樹脂絶縁層下で前記コア本体または前記セラミック副コアの主面に形成されている導体パターンと、当該樹脂絶縁層上に形成される前記導体層と、を導通させるためのビア導体を形成する工程を含む請求項１ないし６のいずれか１項に記載の配線基板の製造方法。   After the film forming and filling step, a conductor pattern formed on the main surface of the core main body or the ceramic sub-core under the resin insulating layer, on the single layer resin insulating layer which is the lowermost layer of the wiring laminated portion, The manufacturing method of the wiring board of any one of Claim 1 thru | or 6 including the process of forming the via conductor for electrically connecting with the said conductor layer formed on the said resin insulating layer. 板状のコア本体に主面間を貫通する貫通孔あるいは第１主面に開口する凹部として副コア収容部が形成され、その内部にセラミック副コアが収容されたコア基板と、該コア基板の主面上に樹脂絶縁層と導体層とが交互に積層して形成された配線積層部と、を備える配線基板であって、
前記コア本体と前記セラミック副コアの隙間に充填形成された溝埋め部が、第１主面側の前記配線積層部の最下層となる樹脂絶縁層と連続して形成されてなり、
第１主面側の前記配線積層部の最下層となる単層の樹脂絶縁層には、当該樹脂絶縁層下で前記コア本体または前記セラミック副コアの主面に形成されている導体パターンと、当該樹脂絶縁層上に形成された前記導体層と、を導通させるためのビア導体が形成されてなることを特徴とする配線基板。
A sub-core housing portion is formed in the plate-shaped core body as a through-hole penetrating between the main surfaces or a recess opening in the first main surface, and a ceramic substrate is accommodated therein, and a core substrate of the core substrate A wiring board comprising: a wiring laminate formed by alternately laminating resin insulation layers and conductor layers on a main surface;
A groove filling portion filled in a gap between the core main body and the ceramic sub-core is formed continuously with a resin insulating layer that is a lowermost layer of the wiring laminated portion on the first main surface side,
A single-layer resin insulation layer, which is the lowest layer of the wiring laminated portion on the first main surface side, has a conductor pattern formed on the main surface of the core body or the ceramic sub-core under the resin insulation layer; A wiring board, wherein a via conductor is formed to electrically connect the conductive layer formed on the resin insulating layer.
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US11/445,288 US7696442B2 (en) 2005-06-03 2006-06-02 Wiring board and manufacturing method of wiring board
TW095119500A TWI396481B (en) 2005-06-03 2006-06-02 Wiring board and manufacturing method of wiring board
CN2006100887735A CN1874648B (en) 2005-06-03 2006-06-05 Wiring board and manufacturing method of wiring board
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JP2013211479A (en) * 2012-03-30 2013-10-10 Fujikura Ltd Multilayer wiring board
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