JP2004200201A - Multilayer substrate with built-in electronic part - Google Patents

Multilayer substrate with built-in electronic part Download PDF

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Publication number
JP2004200201A
JP2004200201A JP2002363339A JP2002363339A JP2004200201A JP 2004200201 A JP2004200201 A JP 2004200201A JP 2002363339 A JP2002363339 A JP 2002363339A JP 2002363339 A JP2002363339 A JP 2002363339A JP 2004200201 A JP2004200201 A JP 2004200201A
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Prior art keywords
electronic component
core member
electronic components
built
opening
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Tatsuro Saruwatari
達郎 猿渡
Masashi Miyazaki
政志 宮崎
Mitsuhiro Takayama
光広 高山
Narutoshi Murota
考俊 室田
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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Priority to JP2002363339A priority Critical patent/JP2004200201A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a cost by avoiding an increase in a man-hour by eliminating the necessity of forming and polishing a transition layer for aligning the surface level of a substrate. <P>SOLUTION: A multilayer substrate (30) with built-in electronic part contains a first electronic part (31) having a thickness Ha, and a second electronic part (32) having a thickness Hb (Ha<Hb). In the multilayer substrate (30) with built-in electronic part, an opening (35a) having a depth corresponding to the size X is formed at a core member (35) having a thickness X (X=Ha+Z; Z>0). The first electronic part (31) is inserted into the opening (35a) and openings (35b, 36a) each having a depth corresponding to a size (X+Y) are formed at the core member (35) and an insulating resin layer (36) laminated on the core member (35) and having a thickness Y (X+Y=Hb+Z), and the second electronic part (32) is inserted into the openings (35b, 36a). <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、電子部品をモジュール基板、パッケージ基板、マザーボード等の基板内部に内蔵（「埋め込み」ともいう。）した電子部品内蔵型多層基板に関する。
【０００２】
【従来の技術】
＜第１の従来例＞
図７、図８は、従来の電子部品内蔵型多層基板の製造工程の一部を示すその構造図である（たとえば、特許文献１参照。）。
図７（ａ）に示すように、絶縁材料からなる回路基板１は、いわゆる両面基板であり、上下面にそれぞれ配線パターン２、３が形成されていると共に、上面側の回路と下面側の回路とを接続するスルーホール４が形成されているものである。
【０００３】
電子部品内蔵型多層基板を製造する場合は、まず、内蔵用の電子部品として、ベアチップ状態の半導体ＩＣ（集積回路）（以下、単に「ベアチップ」という。）５を用意し、そのベアチップ５の下面に予め形成されているバンプ６と、回路基板１の上面に形成されているランド（図では便宜的に配線パターン２とする。）との間を接続する。一般にこの接続はバンプ６と配線パターン２との間に異方性導電フィルムを介在させて、あるいは、半田フリップチップ等により直接行われるが、図では当該フィルムの存在を省略している。
【０００４】
次に、図７（ｂ）に示すように、ベアチップ５を包囲して絶縁層７を形成し、その絶縁層７の上に銅メッキ層８を形成した後、銅メッキ層８の上にレジスト９を被着してレジスト９を所望の回路形状にパターニングし、パターニング後のレジスト９を介して銅メッキ層８を選択エッチング（レジスト９に覆われていない銅メッキ層８をエッチング）する。これにより、レジスト９を除去した後は、図７（ｃ）に示すように、絶縁層７の表面に２層目の配線パターン１０が形成される。
【０００５】
２層以上の多層構造にする場合は、次に、図８（ａ）に示すように、１層目の絶縁層７の上にさらに絶縁層１１を積層する。この絶縁層１１の積層厚さは、１層目の内蔵電子部品（ベアチップ５）が完全に覆われるように調節する。したがって、この２層目の絶縁層１１の表面は、１層目の凹凸（ベアチップ５や配線パターン１０等による凹凸）を吸収してフラットな状態になる。
【０００６】
次に、２層目の絶縁層１１の上に銅メッキ層を形成した後、銅メッキ層の上にレジストを被着してレジストを所望の回路形状にパターニングし、パターニング後のレジストを介して銅メッキ層を選択エッチングすることにより、レジストの除去後には、図８（ｂ）に示すように、絶縁層１１の表面に３層目の配線パターン１２が形成される。したがって、ここで止めておけば、回路基板１を含めて３層構造の電子部品内蔵型多層基板が得られる。
【０００７】
さらに多層化を行う場合は、図８（ｃ）に示すように、２層目の絶縁層１１の上に３層目の絶縁層１３を積層し、絶縁層１３の上に銅メッキ層を形成した後、銅メッキ層の上にレジストを被着してレジストを所望の回路形状にパターニングし、パターニング後のレジストを介して銅メッキ層を選択エッチングすることにより、レジストの除去後には、絶縁層１３の表面に４層目の配線パターン１４が形成される。したがって、たとえば、最上層（この場合、４層目）の配線パターン１４に所望の電子部品１５〜１７を表面実装することにより、この例の場合、全体として、１個の電子部品（ベアチップ５）を内蔵すると共に、３個の電子部品１５〜１７を表面実装した多層基板が得られる。
【０００８】
このような第１の従来例の不都合な点は、電子部品（ベアチップ５）の下面に予め形成されているバンプ６と回路基板１のランド（配線パターン２）とを接続する、いわゆる「フリップチップ接合」によって電子部品を内蔵する仕組みであるため、内蔵電子部品（ベアチップ５）と表面実装部品（電子部品１５〜１７）との間の信号伝達距離が長くなり、高周波特性の劣化が懸念されることにある。すなわち、ベアチップ５と回路基板１との接続箇所はベアチップ５の下面側であり、一方、電子部品１５〜１７などの表面実装部品の実装位置は回路基板１の最上面であるから、両者の最短距離をとって信号伝達を行うことができず、経路長の増大に伴って電気抵抗や分布容量が増加し、それにより、高周波特性の悪化（波形の歪み等）が懸念されるという不都合を内在している。
【０００９】
＜第２の従来例＞
図９は、信号伝達経路の短縮を可能とする、従来の電子部品内蔵型多層基板の製造工程の一部を示すその構造図である（たとえば、特許文献２参照。）。
【００１０】
図９（ａ）において、銅等の金属素材からなるベース基板２０の上には、複数（図では二つ）の半導体ＩＣベアチップ（以下、単に「ベアチップ」という。）２１Ａ、２１Ｂが熱伝導性接着剤２２によって固定されている。二つのベアチップ２１Ａ、２１Ｂは、いずれもシリコン等の共通基板２３Ａ、２３Ｂの上面にダイパッド２４Ａ、２４Ｂや配線（不図示）を有し、且つ、ダイパッド２４Ａ、２４Ｂの上にトランジション層２５Ａ、２５Ｂが設けられている。ここで、一方のベアチップ２１Ａの底面からそのダイパッド２４Ａの上面までの高さをＨＡとし、同様に、他方のベアチップ２１Ｂの底面からそのダイパッド２４Ｂの上面までの高さをＨＢとした場合、図示の例ではＨＡ＜ＨＢである。つまり、ＨＡ≠ＨＢである。これは、二つのベアチップ２１Ａ、２１Ｂの厚さ寸法（ＨＡ、ＨＢ）が異なっていることを意味する。
【００１１】
また、二つのベアチップ２１Ａ、２１Ｂのそれぞれのトランジション層２５Ａ、２５Ｂの厚さ寸法（トランジション層２５Ａの底面から上面までの厚さ寸法ＨＣとトランジション層２５Ｂの底面から上面までの厚さ寸法ＨＤ）は、上記の二つのベアチップ２１Ａ、２１Ｂの厚さ寸法（ＨＡ、ＨＢ）の差を吸収するように設定されている。たとえば、式「ＨＡ＋α＝ＨＢ」が成立する場合、一方のベアチップ２１Ａのトランジション層２５Ａの厚さ寸法ＨＣが、他方のベアチップ２１Ｂのトランジション層２５Ｂの厚さ寸法ＨＤよりも「α」だけ大きくなるように設定（ＨＣ＋α＝ＨＤ）されている。このことは、要するに、「厚さ寸法の異なる二つのベアチップ２１Ａ、２１Ｂの各々のトランジション層２５Ａ、２５Ｂの上面レベルを、ほぼ同一の高さに揃える」ことを意味し、かかる高さ調整の目的は、次の工程によって理解される。
【００１２】
まず、ベース基板２０の上に、二つのベアチップ２１Ａ、２１Ｂを包囲する側壁部として機能する半硬化状態のコア基板２６を載置する。
次いで、図９（ｂ）に示すように、コア基板２６の内側の開口２７内に硬化性樹脂２８を減圧下で充填し、所定時間所定温度で加熱して硬化性樹脂２８を半硬化させる。
【００１３】
その後、図９（ｃ）に示すように、半硬化状態のコア基板２６と硬化性樹脂２８の上面を研磨していくと、前記のとおり、「厚さ寸法の異なる二つのベアチップ２１Ａ、２１Ｂの各々のトランジション層２５Ａ、２５Ｂの上面レベルを、ほぼ同一の高さに揃えている」ため、二つのベアチップ２１Ａ、２１Ｂの各々のトランジション層２５Ａ、２５Ｂの頂部（上面）がほぼ同時に露出するので、それらの露出面を若干研磨（露出面の凹凸がなくなる程度）したところで研磨をストップし、その後、さらに加熱して硬化性樹脂２８とコア基板２６を本硬化させる。
【００１４】
このように、以上説明した第２の従来例における部品内蔵多層基板は、厚さ寸法の異なる複数（図では二つ）のベアチップ２１Ａ、２１Ｂを内蔵できると共に、それらの内蔵部品（ベアチップ２１Ａ、２１Ｂ）のトランジション層２５Ａ、２５Ｂを基板表面に露出させることができる。したがって、内蔵電子部品と基板表面との間の信号伝達経路を最短長とすることができ、前記の第１の従来例の不都合（高周波特性劣化の懸念）を解消することができる。
【００１５】
【特許文献１】
特開平１１−２７４７３４号公報（〔００１６〕〜〔００２３〕、図２〜図１３）
【特許文献２】
特開２００２−１８５１４５号公報（〔００４５〕〜〔００５２〕、図７）
【００１６】
【発明が解決しようとする課題】
しかしながら、上記の第２の従来例にあっては、内蔵電子部品（図ではベアチップ２１Ａ、２１Ｂ）のダイパッド２４Ａ、２４Ｂの上に、基板の表面レベルを揃えるためのトランジション層２５Ａ、２５Ｂを作り込む必要があるうえ、硬化性樹脂２８やトランジション層２５Ａ、２５Ｂを研磨する必要があり、工数が増加してコストアップにつながるという問題点がある。
【００１７】
したがって、本発明の目的は、厚さ寸法の異なる複数の電子部品を内蔵する電子部品内蔵型多層基板において、基板の表面レベルを揃えるためのトランジション層の作り込みと研磨を不要にし、工数の増加を回避してコストの削減を図ることを目的とする。
【００１８】
【課題を解決するための手段】
本発明は、上記目的を達成するために、厚さ寸法Ｈａの第１の電子部品と厚さ寸法Ｈｂ（ただし、Ｈａ＜Ｈｂ）の第２の電子部品とを内蔵する電子部品内蔵型多層基板において、厚さ寸法Ｘ（ただし、Ｘ＝Ｈａ＋Ｚ；Ｚ＞０）のコア部材に寸法Ｘに相当する深さの開口を形成してその開口に前記第１の電子部品を入れ、且つ、前記コア部材とそのコア部材に張り合わせた厚さ寸法Ｙ（ただし、Ｘ＋Ｙ＝Ｈｂ＋Ｚ）の絶縁樹脂層とに寸法Ｘ＋Ｙに相当する深さの開口を形成してその開口に前記第２の電子部品を入れることを特徴とするものである。
この発明では、厚さ寸法の異なる二つの電子部品の実装時上面レベルが同一のレベル（図１の符号Ｌ参照）に揃えられる。したがって、冒頭で説明した第２の従来例のように、基板の表面レベルを揃えるためのトランジション層（図９の符号２５Ａ、２５Ｂ参照）を作り込む必要がなく、当然ながら、トランジション層の研磨も必要ないので、工数の増加を回避してコストの削減を図ることができる。
ここで、コア部材としては、熱伝導性と高剛性とを共に有する、たとえば、銅板などを用いることができる。この場合、コア部材の下面に厚さ寸法Ｙ（ただし、Ｘ＋Ｙ＝Ｈｂ＋Ｚ）の絶縁樹脂層を張り合わせる必要があるが、内蔵電子部品の発熱が少ない場合は、熱伝導性を考慮せず、もっぱら高剛性を有する素材でコア部材を構成可能である。そのような素材としては、たとえば、ガラス繊維又はアラミド繊維に樹脂を含浸させて硬化させたものが存在し、かかる繊維素材を用いた場合、コア部材に絶縁樹脂層を張り合わせる必要はない。
【００１９】
【発明の実施の形態】
以下、図面を参照して本発明の実施の形態を詳細に説明する。
図１（ａ）は、本発明の思想を適用し、モジュール基板として製造された電子部品内蔵型多層基板の構造図である。図示の電子部品内蔵型多層基板３０は、厚さ寸法の異なる複数（図では二つ）の電子部品３１、３２を内蔵（又は「埋め込み」ともいう。）すると共に、必要により、一つないしは複数（図では二つ）の電子部品３３、３４を表面実装したものである。以下、基板内部に埋め込まれた電子部品３１、３２のことを「第１及び第２の電子部品３１、３２」と称し、且つ、表面実装された電子部品３３、３４のことを「表面実装部品３３、３４」と称して両者を区別することにする。
【００２０】
表面実装部品３３、３４は、たとえば、ＬＲＣ等のチップ部品又はその他の電子回路部品とすることができる。また、第１及び第２の電子部品３１、３２は、たとえば、ＬＲＣ等のチップ部品又はその他の電子回路部品とすることができるが、この第１及び第２の電子部品３１、３２は、少なくとも、図１（ｂ）に示すように、その部品上面（“上下”は図面に正対したときの上下をいう。）に電極３１ａ、３１ｂ、３２ａ、３２ｂを有しているものである。
【００２１】
第１及び第２の電子部品３１、３２の厚さ寸法は既述のとおり異なっている。すなわち、第１の電子部品３１の厚さ寸法を“Ｈａ”、第２の電子部品３２の厚さ寸法を“Ｈｂ”としたとき、図示の例では、Ｈａ＜Ｈｂとなっており、Ｈａ≠Ｈｂであるから、これら第１及び第２の電子部品３１、３２の厚さ寸法（Ｈａ、Ｈｂ）は異なっている。
【００２２】
電子部品内蔵型多層基板３０のコア部材（芯材）３５は、熱伝導性がよく且つ高剛性で所定の厚さ寸法（Ｘ）を有する素材（たとえば、銅板など）であり、コア部材３５の下面には、所定の厚さ寸法（Ｙ）を有する絶縁樹脂層３６と導電性金属箔（以下「銅箔３７」）とが張り合わされている。また、コア部材３５と絶縁樹脂層３６には、第１及び第２の電子部品３１、３２を埋め込むための開口３５ａ、３５ｂ、３６ａが形成されており、それらの開口３５ａ、３５ｂ、３６ａに所望の電子部品（第１及び第２の電子部品３１、３２）を入れて載置固定し、その上を樹脂層３８で封止し、当該樹脂層３８に配線パターン３９〜４１やビア４２〜４５を形成した後、所定の配線パターン３９〜４１上に所望の表面実装部品３３、３４をマウントする。なお、図において、４６〜４９は表面実装部品３３、３４をマウントするための半田、５０、５１は第１及び第２の電子部品３１、３２を固定するための接着剤（発熱性の電子部品には熱伝導性接着剤を用いることが好ましい）である。
【００２３】
ここで、接着剤５０、５１の塗布厚を無視（０）したとき、次式▲１▼、▲２▼が共に成立するように、コア部材３５の厚さ寸法（Ｘ）と絶縁樹脂層３６の厚さ寸法（Ｙ）を設定する。
Ｘ＝Ｈａ＋Ｚ ・・・・▲１▼
Ｘ＋Ｙ＝Ｈｂ＋Ｚ ・・・・▲２▼
ただし、Ｚは、第１及び第２の電子部品３１、３２の上面レベルとコア部材３５の上面レベルとの差であり、Ｚ＞０である。
【００２４】
このようにすると、（Ａ）第１及び第２の電子部品３１、３２の上面レベルを同一のレベルＬに揃えることができると共に、（Ｂ）レベルＬをコア部材３５の上面レベルよりも所定量Ｚだけ下げることができる。したがって、（Ａ）により、第１及び第２の電子部品３１、３２の上面から樹脂層３８の上面までの距離を均一にすることができ、たとえば、ビア４２〜４５の深さを揃えるなどして信頼性を向上することができる。また、（Ｂ）により、樹脂層３８を形成する際のプレス応力のほとんどをコア部材３５で受け止めることができ、第１及び第２の電子部品３１、３２への応力印加を緩和して当該部品の破損等を防止することができる。
【００２５】
次に、電子部品内蔵型多層基板３０の製造工程について説明する。
＜第１の工程：図２（ａ）＞
まず、コア部材３５として厚さ寸法Ｘの銅板を用意する。ここで、Ｘの値は、前式▲１▼、▲２▼に従い、第１及び第２の電子部品３１、３２の厚さ寸法（図１（ｂ）のＨａ、Ｈｂ参照）を考慮したものである。次に、コア部材３５の片面に厚さ寸法Ｙの絶縁樹脂層３６と任意厚の銅箔３７とを張り合わせる。なお、絶縁樹脂層３６及び銅箔３７は、あらかじめ片面に銅箔を張り合わせた、いわゆる「樹脂付銅箔」であってもよい。樹脂の厚さ寸法がＹであればよい。ここで、Ｙの値は、前式▲２▼に従い、第２の電子部品３２の厚さ寸法（図１（ｂ）のＨｂ参照）を考慮したものである。
【００２６】
＜第２の工程：図２（ｂ）＞
次に、コア部材３５に開口３５ａ、３５ｂを、たとえば、エッチングにより形成する。開口３５ａ、３５ｂの深さはコア部材３５の厚さ寸法Ｘに相当する。この開口３５ａ、３５ｂは、第１及び第２の電子部品３１、３２の実装穴（いわゆるキャビティ）として用いられるものであり、コア部材３５を上から俯瞰したときの開口３５ａ、３５ｂの形状は、第１及び第２の電子部品３１、３２を余裕をもって入れることができる適切な形に設定する。また、このとき、図２（ｃ）に示すように、コア部材３５の任意位置に、コア部材３５の厚み方向に貫通する所望数の環状エッチング部３５ｃを形成してもよい。コア部材３５が導電材料である場合、環状エッチング部３５ｃの内側残存部３５ｄ（コア部材３５の残存部分）が、コア部材３５を挟んで上層と下層とを電気的に接続するポストの役目を果たす。
【００２７】
＜第３の工程：図２（ｄ）＞
次に、厚さ寸法の大きい方の電子部品（第２の電子部品３２）を実装するための開口３５ｂについては、その底面部分の絶縁樹脂層３６をさらに同型状で掘り下げる。この掘り下げ部分についても“開口”ということにすると、この開口３６ａの深さは絶縁樹脂層３６の厚さ寸法Ｙに相当する。したがって、厚さ寸法の大きい方の電子部品（第２の電子部品３２）の実装穴の深さは、開口３５ｂの深さ（Ｘ）と開口３６ａの深さ（Ｙ）を足し合わせたもの（Ｘ＋Ｙ）になる。なお、絶縁樹脂層３６の掘り下げは、ＣＯ2やＹＡＧ等のレーザ加工を用いることができる。
【００２８】
＜第４の工程：図３（ａ）＞
次に、厚さ寸法の小さい方の電子部品（第１の電子部品３１）を左側の開口３５ａに入れ、厚さ寸法の大きい方の電子部品（第２の電子部品３２）を右側の開口３５ｂ、３６ａに入れ、第１及び第２の電子部品３１、３２の下面に接着剤５０、５１を塗布して固定する。先に説明したように、左側の開口３５ａの深さは「Ｘ」であり、右側の開口３５ｂ、３６ａの深さは「Ｘ＋Ｙ」である。そして、第１の電子部品３１の厚さ寸法は「Ｈａ」であり、第２の電子部品３２の厚さ寸法は「Ｈｂ」であり、これらのＸ、Ｙ、Ｈａ、Ｈｂの間には前式▲１▼、▲２▼の関係が成立するから、結局、厚さ寸法の異なる第１及び第２の電子部品３１、３２を実装後の時点では、それらの第１及び第２の電子部品３１、３２の上面レベルが同一のレベルＬに揃い、且つ、レベルＬは、コア部材３５の上面レベルよりも所定量Ｚだけ低い位置になる。
【００２９】
＜第５の工程：図３（ｂ）＞
次に、樹脂層３８を形成して第１及び第２の電子部品３１、３２を封止するが、前記の工程において、「第１及び第２の電子部品３１、３２の上面レベルが同一のレベルＬに揃っている」ため、第１及び第２の電子部品３１、３２の直上における樹脂層３８の形成厚（膜厚ともいう。）を均一化することができる。樹脂層３８の形成は、たとえば、樹脂フィルムのラミネートや真空プレス圧着によって行うことができる。この場合、圧着等に伴う応力が発生して第１及び第２の電子部品３１、３２への悪影響（破損等）が心配されるが、前記の工程において、「第１及び第２の電子部品３１、３２の上面レベルがコア部材３５の上面レベルよりも所定量Ｚだけ低い位置になっている」ため、ほとんどの応力はコア部材３５で受け止められ、第１及び第２の電子部品３１、３２に悪影響を与えることはない。したがって、樹脂層３８の形成時において、第１及び第２の電子部品３１、３２の破損等を確実に回避することができる。
【００３０】
＜第６の工程：図３（ｃ）＞
次に、樹脂層３８にビアホール５２〜５５を形成（たとえば、レーザ加工により）し、第１及び第２の電子部品３１、３２の電極３１ａ、３１ｂ、３２ａ、３２ｂを露出させる。このとき、前記の工程で、「第１及び第２の電子部品３１、３２の直上における樹脂層３８の形成厚が均一化されている」ため、すべてのビアホール５２〜５５の深さを同一にすることができる。したがって、ビアホール５２〜５５の加工条件を統一することができ、加工バラツキを回避して良好なビアホール５２〜５５を形成することができる。また、このとき、コア部材３５に電気的接続のためのポスト（図２（ｃ）参照）を形成してある場合は、ポストを露出するビアホールを併せて形成することができる。
【００３１】
＜第７の工程：図４（ａ）＞
次に、ビアホール５２〜５５の内部にフィルドメッキを施してビア４２〜４５を形成すると共に、樹脂層３８の表面に所望形状の回路パターン３９〜４１を形成（たとえば、セミアディティブ法により）する。かかるビア４２〜４５の形成も、上記のビアホール５２〜５５の形成と同様に、すべてのビアホール５２〜５５の深さが同一であるため、ビア４２〜４５の加工条件を統一し、加工バラツキを回避して均一なメッキが施された良好なビア４２〜４５を形成することができる。
【００３２】
＜第８の工程：図４（ｂ）＞
次に、基板下面の銅箔３７をパターニング（たとえば、サブトラクティブ法により）して所望形状の回路パターン（ＬＧＡパターン）３７ａ〜３７ｃを形成する。
＜第９の工程：図４（ｃ）＞
最後に、所望の表面実装部品３３、３４を回路パターン３９〜４１の上にマウントして、図１（ａ）の電子部品内蔵型多層基板３０を完成する。
なお、上記実施の形態では、コア部材３５を挟んで上下に各一層の回路パターンを設けたが、これに限定するものではなく、たとえば、同様にして、上下にそれぞれ多層の回路パターンを形成してもよい。
【００３３】
以上のとおりであるから、本実施の形態では、次の効果を得ることができる。
（１）厚さ寸法Ｈａの第１の電子部品３１と厚さ寸法Ｈｂ（ただし、Ｈａ＜Ｈｂ）の第２の電子部品３２とを埋め込む際に、厚さ寸法Ｘ（ただし、Ｘ＝Ｈａ＋Ｚ；前式▲１▼参照）のコア部材３５に寸法Ｘに相当する深さの開口３５ａを形成して、その開口３５ａに第１の電子部品３１を入れ、さらに、コア部材３５と、そのコア部材３５に張り合わせた厚さ寸法Ｙ（ただし、Ｘ＋Ｙ＝Ｈｂ＋Ｚ；前式▲２▼参照）の絶縁樹脂層３６とに寸法Ｘ＋Ｙに相当する深さの開口３５ｂ、３６ａを形成して、その開口３５ｂ、３６ａに第２の電子部品３２を入れるようにしたから、厚さ寸法の異なる第１及び第２の電子部品３１、３２の実装時上面レベルを同一のレベル（図１の符号Ｌ参照）に揃えることができる。したがって、冒頭で説明した第２の従来例のように、基板の表面レベルを揃えるためのトランジション層（図９の符号２５Ａ、２５Ｂ参照）を作り込む必要がなく、当然ながら、トランジション層の研磨も必要ないので、工数の増加を回避してコストの削減を図ることができ、本発明の課題を達成することができる。
【００３４】
（２）また、厚さ寸法の異なる第１及び第２の電子部品３１、３２の実装時上面レベルを同一のレベル（図１の符号Ｌ参照）に揃えることができるため、それらの第１及び第２の電子部品３１、３２を封止するための樹脂層３８の膜厚を、当該電子部品の直上において均一化することができる。これにより、樹脂層３８に形成するビア４２〜４５の深さを揃え、ビア形成の加工条件を統一してバラツキのない良好なビア４２〜４５を形成し、信頼性の向上を図ることができる。
【００３５】
（３）加えて、第１及び第２の電子部品３１、３２の上面レベル（Ｌ）を、コア部材３５の上面レベルよりも所定量Ｚだけ低い位置にすることができるため、樹脂層３８の形成時に発生する応力（たとえば、樹脂フィルムのラミネートや真空プレス圧着に伴って発生する応力）のほとんどをコア部材３５によって受け止めることができ、第１及び第２の電子部品３１、３２に対して悪影響を与えることがない。したがって、樹脂層３８の形成時において、第１及び第２の電子部品３１、３２の破損等を確実に回避することができ、この点においても、信頼性の向上を図ることができる。
【００３６】
なお、以上の実施の形態では、基板の芯材として、熱伝導性がよく且つ高剛性で所定の厚さ寸法（Ｘ）を有する素材、たとえば、銅板などを用いたが、本発明の思想はこれに限定されない。第１及び第２の電子部品３１、３２の発熱が少ない場合は、熱伝導性を考慮しなくてもよい。
【００３７】
図５は、本発明の思想を適用して製造された他の電子部品内蔵型多層基板３０′の構造図である。なお、前記の実施の形態（図１）と同じ構成要素については同一の符号を付してその説明を省略する。図１との相違は、コア部材３５及び絶縁樹脂層３６を使用せず、その代わりに、ガラス繊維やアラミド繊維などの繊維体に樹脂を含浸させて硬化させたコア部材６０を用いている点にある。
【００３８】
コア部材６０の厚さ寸法は、前記の実施の形態におけるコア部材３５の厚さ寸法（Ｘ）と絶縁樹脂層３６の厚さ寸法（Ｙ）を加えた値（Ｘ＋Ｙ）に等しい。コア部材６０には、第１及び第２の電子部品３１、３２を埋め込むための開口６０ａ、６０ｂが形成されており、一方の開口６０ａの深さは「Ｘ」、他方の開口６０Ｂの深さは「Ｘ＋Ｙ」である。
【００３９】
ここで、「Ｘ」や「Ｙ」は、前式▲１▼、▲２▼を満たす値である。したがって、前記の実施の形態と同様に、厚さ寸法の異なる第１及び第２の電子部品３１、３２の実装時上面レベルを同一のレベル（図１の符号Ｌ参照）に揃えることができ、冒頭で説明した第２の従来例のように、基板の表面レベルを揃えるためのトランジション層（図９の符号２５Ａ、２５Ｂ参照）を作り込む必要がなく、当然ながら、トランジション層の研磨も必要ないので、工数の増加を回避してコストの削減を図ることができ、本発明の課題を達成することができる。
【００４０】
また、厚さ寸法の異なる第１及び第２の電子部品３１、３２の実装時上面レベルを同一のレベル（図１の符号Ｌ参照）に揃えることができるため、それらの第１及び第２の電子部品３１、３２を封止するための樹脂層３８の膜厚を、当該電子部品の直上において均一化することができる。これにより、樹脂層３８に形成するビア４２〜４５の深さを揃え、ビア形成の加工条件を統一してバラツキのない良好なビア４２〜４５を形成し、信頼性の向上を図ることができる。
【００４１】
加えて、第１及び第２の電子部品３１、３２の上面レベル（Ｌ）を、コア部材６０の上面レベルよりも所定量Ｚだけ低い位置にすることができるため、樹脂層３８の形成時に発生する応力（たとえば、樹脂フィルムのラミネートや真空プレス圧着に伴って発生する応力）のほとんどをコア部材６０によって受け止めることができ、第１及び第２の電子部品３１、３２に対して悪影響を与えない。したがって、樹脂層３８の形成時において、第１及び第２の電子部品３１、３２の破損等を確実に回避することができ、この点においても、信頼性の向上を図ることができる。
【００４２】
また、以上の各実施の形態においては、電子部品を埋設後の基板の上下面を平坦にできるため、たとえば、図６に示すように、電子部品を埋設後の基板７１の上面や下面に、複数層にわたって積み重ねられたスタックドビア７４〜８１を有する配線層７２、７３を積層した電子部品内蔵型多層基板７０を構成することができる。この電子部品内蔵型多層基板７０によれば、内蔵された各電子部品とビアを介して接続される回路パターンの高さが均一であるため、層間接続する際に各部にかかる圧力が均一となり、各配線層７２、７３の一括積層による任意層間接続（“一括積層”とは、多層基板を製造する際に、あらかじめ回路パターンを形成した各層の接着及び電気的接続を１回のプレスで行うことをいう。）をバラツキなく確実に可能とすることができる。一括積層による任意層間接続の手法としては、層間接続部に金属バンプ、金属ペーストバンプ、及び接着層（プリプレグ等にレーザー・ドリル等で任意の位置の穴を開け、導電性樹脂を充填したもの）等を利用した手法が挙げられる。また、電子部品を埋設後の基板７１の上面や下面が平坦であるため、各配線層７２、７３の膜厚を均一化することができ、積層不良や層間接続不良を防止することができる。さらに、あらかじめ所定の厚さ寸法に揃えられた“特注”の電子部品を準備できない場合、言い換えれば、異なる厚さ寸法を持つ複数の電子部品しか準備できない場合でも、各部品と回路パターンとを接続するビアの深さを均一にすることができるため、多層基板の内部に異なる厚さ寸法の汎用部品（たとえば、積層コンデンサやインダクタ、汎用ＩＣ等）を同時に使用可とすることができる。
【００４３】
【発明の効果】
本発明によれば、厚さ寸法Ｈａの第１の電子部品と厚さ寸法Ｈｂ（ただし、Ｈａ＜Ｈｂ）の第２の電子部品とを内蔵する電子部品内蔵型多層基板において、厚さ寸法Ｘ（ただし、Ｘ＝Ｈａ＋Ｚ；Ｚ＞０）のコア部材に寸法Ｘに相当する深さの開口を形成してその開口に前記第１の電子部品を入れ、且つ、前記コア部材とそのコア部材に張り合わせた厚さ寸法Ｙ（ただし、Ｘ＋Ｙ＝Ｈｂ＋Ｚ）の絶縁樹脂層とに寸法Ｘ＋Ｙに相当する深さの開口を形成してその開口に前記第２の電子部品を入れることを特徴としたので、厚さ寸法の異なる二つの電子部品の実装時上面レベルを同一のレベル（図１の符号Ｌ参照）に揃えることができる。したがって、冒頭で説明した第２の従来例のように、基板の表面レベルを揃えるためのトランジション層（図９の符号２５Ａ、２５Ｂ参照）を作り込む必要がなく、当然ながら、トランジション層の研磨も必要ないので、工数の増加を回避してコストの削減を図ることができる。
【図面の簡単な説明】
【図１】本発明の思想を適用して製造された電子部品内蔵型多層基板の構造図及び内蔵電子部品の外観図である。
【図２】本実施の形態の工程図（第１の工程〜第３の工程）である。
【図３】本実施の形態の工程図（第４の工程〜第６の工程）である。
【図４】本実施の形態の工程図（第７の工程〜第９の工程）である。
【図５】本発明の思想を適用して製造された他の電子部品内蔵型多層基板３０′の構造図である。
【図６】複数層にわたって積み重ねられたスタックドビア７４〜８１を有する配線層７２、７３を積層した電子部品内蔵型多層基板７０の構造図である。
【図７】第１の従来例の工程図（その１）である。
【図８】第１の従来例の工程図（その２）である。
【図９】第２の従来例の工程図である。
【符号の説明】
３０ 電子部品内蔵型多層基板
３１ 内蔵電子部品（第１の電子部品）
３２ 内蔵電子部品（第２の電子部品）
３５ コア部材
３５ａ 開口
３５ｂ 開口
３６ 絶縁樹脂層
３６ａ 開口
６０ コア部材[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic component built-in type multilayer substrate in which electronic components are embedded (also referred to as “embedded”) inside a substrate such as a module substrate, a package substrate, or a motherboard.
[0002]
[Prior art]
<First Conventional Example>
7 and 8 are structural views showing a part of a manufacturing process of a conventional multilayer substrate with built-in electronic components (see, for example, Patent Document 1).
As shown in FIG. 7A, a circuit board 1 made of an insulating material is a so-called double-sided board, and wiring patterns 2 and 3 are formed on the upper and lower surfaces, respectively, and an upper surface circuit and a lower surface circuit. Through-holes 4 are formed.
[0003]
When manufacturing a multilayer substrate with a built-in electronic component, first, as a built-in electronic component, a semiconductor IC (integrated circuit) 5 (hereinafter simply referred to as “bare chip”) 5 in a bare chip state is prepared, and the bottom surface of the bare chip 5 is prepared. The bumps 6 formed in advance are connected to the lands formed on the upper surface of the circuit board 1 (in the drawing, for convenience, the wiring pattern 2). In general, this connection is made by interposing an anisotropic conductive film between the bump 6 and the wiring pattern 2 or directly by a solder flip chip or the like, but the presence of the film is omitted in the figure.
[0004]
Next, as shown in FIG. 7B, an insulating layer 7 is formed surrounding the bare chip 5, a copper plating layer 8 is formed on the insulating layer 7, and then a resist is formed on the copper plating layer 8. 9 is applied and the resist 9 is patterned into a desired circuit shape, and the copper plating layer 8 is selectively etched through the patterned resist 9 (the copper plating layer 8 not covered with the resist 9 is etched). Thus, after the resist 9 is removed, a second-layer wiring pattern 10 is formed on the surface of the insulating layer 7 as shown in FIG.
[0005]
In the case of a multilayer structure of two or more layers, next, an insulating layer 11 is further laminated on the first insulating layer 7 as shown in FIG. The laminated thickness of the insulating layer 11 is adjusted so that the first built-in electronic component (bare chip 5) is completely covered. Therefore, the surface of the second insulating layer 11 absorbs the first layer unevenness (unevenness caused by the bare chip 5, the wiring pattern 10, etc.) and becomes flat.
[0006]
Next, after a copper plating layer is formed on the second insulating layer 11, a resist is deposited on the copper plating layer, and the resist is patterned into a desired circuit shape. By selectively etching the copper plating layer, a third-layer wiring pattern 12 is formed on the surface of the insulating layer 11 as shown in FIG. Therefore, if it stops here, the multilayer board | substrate with a built-in electronic component of 3 layers structure including the circuit board 1 will be obtained.
[0007]
When further multilayering is performed, as shown in FIG. 8C, a third insulating layer 13 is laminated on the second insulating layer 11, and a copper plating layer is formed on the insulating layer 13. Then, a resist is deposited on the copper plating layer, the resist is patterned into a desired circuit shape, and the copper plating layer is selectively etched through the patterned resist. A fourth wiring pattern 14 is formed on the surface 13. Therefore, for example, in this example, one electronic component (bare chip 5) is formed by surface-mounting desired electronic components 15 to 17 on the wiring pattern 14 of the uppermost layer (in this case, the fourth layer). Is obtained, and a multilayer board on which three electronic components 15 to 17 are surface-mounted is obtained.
[0008]
The disadvantage of the first conventional example is that the so-called “flip chip” connects the bump 6 formed in advance on the lower surface of the electronic component (bare chip 5) and the land (wiring pattern 2) of the circuit board 1. Since the electronic component is built in by “joining”, the signal transmission distance between the built-in electronic component (bare chip 5) and the surface mount component (electronic components 15 to 17) becomes long, and there is a concern that the high-frequency characteristics may deteriorate. There is. That is, the connection location of the bare chip 5 and the circuit board 1 is on the lower surface side of the bare chip 5, while the mounting position of the surface mounting components such as the electronic components 15 to 17 is the uppermost surface of the circuit board 1. There is an inconvenience that signal transmission cannot be performed over a long distance, and electrical resistance and distributed capacity increase with increasing path length, which may cause deterioration of high-frequency characteristics (such as waveform distortion). doing.
[0009]
<Second Conventional Example>
FIG. 9 is a structural diagram showing a part of a manufacturing process of a conventional electronic component built-in multilayer substrate that enables shortening of a signal transmission path (see, for example, Patent Document 2).
[0010]
In FIG. 9A, a plurality (two in the figure) of semiconductor IC bare chips (hereinafter simply referred to as “bare chips”) 21A and 21B are thermally conductive on a base substrate 20 made of a metal material such as copper. It is fixed by an adhesive 22. Each of the two bare chips 21A and 21B has die pads 24A and 24B and wiring (not shown) on the upper surface of a common substrate 23A and 23B such as silicon, and transition layers 25A and 25B are formed on the die pads 24A and 24B. Is provided. Here, when the height from the bottom surface of one bare chip 21A to the top surface of the die pad 24A is HA, and similarly, the height from the bottom surface of the other bare chip 21B to the top surface of the die pad 24B is HB, In the example, HA <HB. That is, HA ≠ HB. This means that the thickness dimensions (HA, HB) of the two bare chips 21A, 21B are different.
[0011]
The thickness dimensions of the transition layers 25A and 25B of the two bare chips 21A and 21B (the thickness dimension HC from the bottom surface to the top surface of the transition layer 25A and the thickness dimension HD from the bottom surface to the top surface of the transition layer 25B) are as follows: The difference between the thickness dimensions (HA, HB) of the two bare chips 21A, 21B is set to be absorbed. For example, when the formula “HA + α = HB” is satisfied, the thickness dimension HC of the transition layer 25A of one bare chip 21A is set to be larger by “α” than the thickness dimension HD of the transition layer 25B of the other bare chip 21B. (HC + α = HD). In short, this means that “the top surface levels of the transition layers 25A and 25B of the two bare chips 21A and 21B having different thickness dimensions are made to be substantially the same height”. Is understood by the following steps.
[0012]
First, a semi-cured core substrate 26 that functions as a side wall portion surrounding the two bare chips 21 </ b> A and 21 </ b> B is placed on the base substrate 20.
Next, as shown in FIG. 9B, the curable resin 28 is filled in the opening 27 inside the core substrate 26 under reduced pressure, and the curable resin 28 is semi-cured by heating at a predetermined temperature for a predetermined time.
[0013]
Thereafter, as shown in FIG. 9C, when the upper surfaces of the semi-cured core substrate 26 and the curable resin 28 are polished, as described above, “the two bare chips 21A and 21B having different thickness dimensions” Since the upper surface levels of the respective transition layers 25A and 25B are aligned at substantially the same height, ”the top portions (upper surfaces) of the respective transition layers 25A and 25B of the two bare chips 21A and 21B are exposed almost simultaneously. Polishing is stopped when the exposed surfaces are slightly polished (the degree of unevenness of the exposed surfaces is eliminated), and then further heated to fully cure the curable resin 28 and the core substrate 26.
[0014]
As described above, the component-embedded multilayer substrate in the second conventional example described above can incorporate a plurality (two in the figure) of bare chips 21A and 21B having different thickness dimensions, and these built-in components (bare chips 21A and 21B). ) Transition layers 25A and 25B can be exposed on the substrate surface. Therefore, the signal transmission path between the built-in electronic component and the substrate surface can be made the shortest length, and the inconvenience (the concern about deterioration of the high frequency characteristics) of the first conventional example can be solved.
[0015]
[Patent Document 1]
JP-A-11-274734 ([0016] to [0023], FIGS. 2 to 13)
[Patent Document 2]
JP 2002-185145 A ([0045] to [0052], FIG. 7)
[0016]
[Problems to be solved by the invention]
However, in the second conventional example, transition layers 25A and 25B for aligning the surface level of the substrate are formed on the die pads 24A and 24B of the built-in electronic components (bare chips 21A and 21B in the figure). In addition, it is necessary to polish the curable resin 28 and the transition layers 25A and 25B, which increases the number of steps and leads to a cost increase.
[0017]
Accordingly, an object of the present invention is to eliminate the need for creating and polishing a transition layer for aligning the surface level of a substrate in an electronic component built-in type multi-layer substrate incorporating a plurality of electronic components having different thickness dimensions, thereby increasing the number of steps. The purpose is to reduce the cost by avoiding the above.
[0018]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides an electronic component-embedded multilayer substrate in which a first electronic component having a thickness dimension Ha and a second electronic component having a thickness dimension Hb (Ha <Hb) are embedded. , An opening having a depth corresponding to the dimension X is formed in a core member having a thickness dimension X (where X = Ha + Z; Z> 0), and the first electronic component is placed in the opening, and the core An opening having a depth corresponding to the dimension X + Y is formed in the member and an insulating resin layer having a thickness Y (X + Y = Hb + Z) bonded to the core member, and the second electronic component is inserted into the opening. It is characterized by.
According to the present invention, the upper surface level of two electronic components having different thickness dimensions is aligned to the same level (see symbol L in FIG. 1). Therefore, unlike the second conventional example described at the beginning, it is not necessary to create a transition layer (see reference numerals 25A and 25B in FIG. 9) for aligning the surface level of the substrate. Of course, polishing of the transition layer is also possible. Since this is not necessary, the cost can be reduced by avoiding an increase in man-hours.
Here, as the core member, for example, a copper plate or the like having both thermal conductivity and high rigidity can be used. In this case, an insulating resin layer having a thickness dimension Y (X + Y = Hb + Z) needs to be attached to the lower surface of the core member. However, when the built-in electronic component generates little heat, the thermal conductivity is not considered and is exclusively considered. The core member can be made of a material having high rigidity. As such a material, for example, a glass fiber or an aramid fiber impregnated with a resin and cured, and when such a fiber material is used, it is not necessary to attach an insulating resin layer to the core member.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1A is a structural diagram of a multilayer substrate with built-in electronic components manufactured as a module substrate by applying the idea of the present invention. The electronic component built-in type multilayer substrate 30 shown in the drawing incorporates (or is also referred to as “embedding”) a plurality (two in the figure) of electronic components 31 and 32 having different thickness dimensions, and, if necessary, one or thru. A plurality (two in the figure) of electronic components 33 and 34 are surface-mounted. Hereinafter, the electronic components 31 and 32 embedded in the substrate are referred to as “first and second electronic components 31 and 32”, and the surface-mounted electronic components 33 and 34 are referred to as “surface-mounted components”. 33 and 34 "will be distinguished from each other.
[0020]
The surface mount components 33 and 34 can be, for example, chip components such as LRC or other electronic circuit components. The first and second electronic components 31 and 32 can be, for example, chip components such as LRC or other electronic circuit components, and the first and second electronic components 31 and 32 are at least As shown in FIG. 1B, electrodes 31a, 31b, 32a and 32b are provided on the upper surface of the component ("upper and lower" means the upper and lower when facing the drawing).
[0021]
The thickness dimensions of the first and second electronic components 31 and 32 are different as described above. That is, when the thickness dimension of the first electronic component 31 is “Ha” and the thickness dimension of the second electronic component 32 is “Hb”, Ha <Hb in the illustrated example, and Ha ≠ Since it is Hb, the thickness dimensions (Ha, Hb) of these first and second electronic components 31, 32 are different.
[0022]
The core member (core material) 35 of the electronic component built-in multilayer substrate 30 is a material (for example, a copper plate) that has a high thermal conductivity, high rigidity, and a predetermined thickness (X). An insulating resin layer 36 having a predetermined thickness dimension (Y) and a conductive metal foil (hereinafter referred to as “copper foil 37”) are bonded to the lower surface. The core member 35 and the insulating resin layer 36 are formed with openings 35a, 35b, 36a for embedding the first and second electronic components 31, 32. The openings 35a, 35b, 36a are formed in the openings 35a, 35b, 36a. The electronic parts (first and second electronic parts 31 and 32) are placed and fixed, and the top is sealed with a resin layer 38, and wiring patterns 39 to 41 and vias 42 to 45 are formed on the resin layer 38. Then, desired surface mount components 33 and 34 are mounted on predetermined wiring patterns 39 to 41. In the figure, 46 to 49 are solders for mounting the surface mount components 33 and 34, 50 and 51 are adhesives for fixing the first and second electronic components 31 and 32 (heat-generating electronic components). It is preferable to use a heat conductive adhesive.
[0023]
Here, when the coating thicknesses of the adhesives 50 and 51 are ignored (0), the thickness dimension (X) of the core member 35 and the insulating resin layer 36 are set so that both the following formulas (1) and (2) are satisfied. The thickness dimension (Y) is set.
X = Ha + Z (1)
X + Y = Hb + Z (2)
However, Z is a difference between the upper surface level of the first and second electronic components 31 and 32 and the upper surface level of the core member 35, and Z> 0.
[0024]
In this way, (A) the upper surface level of the first and second electronic components 31, 32 can be made the same level L, and (B) the level L is a predetermined amount higher than the upper surface level of the core member 35. Only Z can be lowered. Therefore, according to (A), the distance from the upper surface of the first and second electronic components 31 and 32 to the upper surface of the resin layer 38 can be made uniform, for example, the depths of the vias 42 to 45 are made uniform. Reliability can be improved. Further, according to (B), most of the press stress at the time of forming the resin layer 38 can be received by the core member 35, and the application of stress to the first and second electronic components 31, 32 is alleviated by the component. Can be prevented.
[0025]
Next, the manufacturing process of the electronic component built-in multilayer substrate 30 will be described.
<First step: FIG. 2A>
First, a copper plate having a thickness dimension X is prepared as the core member 35. Here, the value of X takes into account the thickness dimensions of the first and second electronic components 31 and 32 (see Ha and Hb in FIG. 1B) in accordance with the previous formulas (1) and (2). It is. Next, an insulating resin layer 36 having a thickness Y and a copper foil 37 having an arbitrary thickness are bonded to one side of the core member 35. The insulating resin layer 36 and the copper foil 37 may be so-called “resin-attached copper foil” in which a copper foil is bonded to one side in advance. The thickness dimension of the resin may be Y. Here, the value of Y takes into account the thickness dimension of the second electronic component 32 (see Hb in FIG. 1B) in accordance with the previous equation (2).
[0026]
<Second step: FIG. 2B>
Next, openings 35a and 35b are formed in the core member 35 by, for example, etching. The depths of the openings 35 a and 35 b correspond to the thickness dimension X of the core member 35. The openings 35a and 35b are used as mounting holes (so-called cavities) for the first and second electronic components 31 and 32. The shape of the openings 35a and 35b when the core member 35 is viewed from above is as follows. The first and second electronic components 31 and 32 are set in an appropriate shape that can be inserted with a margin. At this time, as shown in FIG. 2C, a desired number of annular etching portions 35 c penetrating in the thickness direction of the core member 35 may be formed at an arbitrary position of the core member 35. When the core member 35 is made of a conductive material, the inner remaining portion 35d of the annular etching portion 35c (the remaining portion of the core member 35) serves as a post that electrically connects the upper layer and the lower layer with the core member 35 interposed therebetween. .
[0027]
<Third Step: FIG. 2 (d)>
Next, with respect to the opening 35b for mounting the electronic component having the larger thickness dimension (second electronic component 32), the insulating resin layer 36 on the bottom surface portion thereof is further dug in the same shape. If this digging portion is also referred to as “opening”, the depth of the opening 36 a corresponds to the thickness dimension Y of the insulating resin layer 36. Accordingly, the depth of the mounting hole of the electronic component having the larger thickness (second electronic component 32) is the sum of the depth (X) of the opening 35b and the depth (Y) of the opening 36a ( X + Y). The insulating resin layer 36 is dug down by CO 2 2 Or laser processing such as YAG can be used.
[0028]
<Fourth Step: FIG. 3A>
Next, the electronic component having the smaller thickness dimension (first electronic component 31) is placed in the left opening 35a, and the electronic component having the larger thickness dimension (second electronic component 32) is placed in the right opening 35b. 36a, and adhesives 50 and 51 are applied and fixed to the lower surfaces of the first and second electronic components 31 and 32, respectively. As described above, the depth of the left opening 35a is “X”, and the depth of the right openings 35b and 36a is “X + Y”. The thickness dimension of the first electronic component 31 is “Ha”, and the thickness dimension of the second electronic component 32 is “Hb”. Between these X, Y, Ha, and Hb, Since the relations (1) and (2) are established, after the first and second electronic components 31 and 32 having different thickness dimensions are mounted, the first and second electronic components are eventually mounted. The upper surface levels of 31 and 32 are aligned with the same level L, and the level L is lower than the upper surface level of the core member 35 by a predetermined amount Z.
[0029]
<Fifth step: FIG. 3B>
Next, the resin layer 38 is formed and the first and second electronic components 31 and 32 are sealed. In the above process, the upper surface level of the first and second electronic components 31 and 32 is the same. Since they are “level L”, the formation thickness (also referred to as film thickness) of the resin layer 38 immediately above the first and second electronic components 31 and 32 can be made uniform. The resin layer 38 can be formed, for example, by laminating a resin film or vacuum press bonding. In this case, stress associated with pressure bonding or the like is generated, and there is a concern about adverse effects (breakage or the like) on the first and second electronic components 31 and 32. In the above process, “first and second electronic components” Since the upper surface level of 31 and 32 is lower than the upper surface level of the core member 35 by a predetermined amount Z, most of the stress is received by the core member 35 and the first and second electronic components 31 and 32 are received. Will not be adversely affected. Therefore, when the resin layer 38 is formed, damage to the first and second electronic components 31 and 32 can be reliably avoided.
[0030]
<Sixth Step: FIG. 3C>
Next, via holes 52 to 55 are formed in the resin layer 38 (for example, by laser processing), and the electrodes 31a, 31b, 32a, and 32b of the first and second electronic components 31 and 32 are exposed. At this time, in the above-described process, “the thickness of the resin layer 38 formed just above the first and second electronic components 31 and 32 is uniform”, all the via holes 52 to 55 have the same depth. can do. Therefore, the processing conditions of the via holes 52 to 55 can be unified, and favorable via holes 52 to 55 can be formed while avoiding processing variations. At this time, when a post (see FIG. 2C) for electrical connection is formed on the core member 35, a via hole exposing the post can be formed together.
[0031]
<Seventh step: FIG. 4A>
Next, filled plating is performed inside the via holes 52 to 55 to form vias 42 to 45, and circuit patterns 39 to 41 having a desired shape are formed on the surface of the resin layer 38 (for example, by a semi-additive method). In the formation of the vias 42 to 45, the depth of all the via holes 52 to 55 is the same as the formation of the via holes 52 to 55. Therefore, the processing conditions of the vias 42 to 45 are unified, and processing variations are reduced. By avoiding, good vias 42 to 45 with uniform plating can be formed.
[0032]
<Eighth step: FIG. 4B>
Next, the copper foil 37 on the lower surface of the substrate is patterned (for example, by a subtractive method) to form circuit patterns (LGA patterns) 37a to 37c having desired shapes.
<9th process: FIG.4 (c)>
Finally, desired surface mount components 33 and 34 are mounted on the circuit patterns 39 to 41 to complete the electronic component built-in multilayer substrate 30 of FIG.
In the above embodiment, each layer of the circuit pattern is provided above and below the core member 35. However, the present invention is not limited to this. For example, a multilayer circuit pattern is formed above and below in the same manner. May be.
[0033]
As described above, in the present embodiment, the following effects can be obtained.
(1) When embedding the first electronic component 31 having the thickness dimension Ha and the second electronic component 32 having the thickness dimension Hb (where Ha <Hb), the thickness dimension X (where X = Ha + Z; An opening 35a having a depth corresponding to the dimension X is formed in the core member 35 of the previous formula (1), and the first electronic component 31 is inserted into the opening 35a. Furthermore, the core member 35 and the core member Openings 35b and 36a having a depth corresponding to the dimension X + Y are formed in the insulating resin layer 36 having a thickness Y (X + Y = Hb + Z; refer to the above formula (2)) pasted to 35, and the openings 35b, Since the second electronic component 32 is placed in 36a, the upper surface level when mounting the first and second electronic components 31 and 32 having different thickness dimensions is made the same level (see symbol L in FIG. 1). be able to. Therefore, unlike the second conventional example described at the beginning, it is not necessary to create a transition layer (see reference numerals 25A and 25B in FIG. 9) for aligning the surface level of the substrate. Of course, polishing of the transition layer is also possible. Since it is not necessary, it is possible to reduce the cost by avoiding an increase in the number of man-hours and to achieve the object of the present invention.
[0034]
(2) Since the upper surface level when mounting the first and second electronic components 31 and 32 having different thickness dimensions can be aligned to the same level (see reference symbol L in FIG. 1), The film thickness of the resin layer 38 for sealing the second electronic components 31 and 32 can be made uniform immediately above the electronic components. As a result, the depths of the vias 42 to 45 formed in the resin layer 38 are made uniform, the processing conditions for forming the vias are unified, and good vias 42 to 45 having no variation are formed, thereby improving the reliability. .
[0035]
(3) In addition, since the upper surface level (L) of the first and second electronic components 31, 32 can be set lower than the upper surface level of the core member 35 by a predetermined amount Z, the resin layer 38 Most of the stress generated at the time of formation (for example, stress generated by laminating a resin film or vacuum press-bonding) can be received by the core member 35 and adversely affects the first and second electronic components 31 and 32. Never give. Therefore, when the resin layer 38 is formed, the first and second electronic components 31 and 32 can be reliably prevented from being damaged, and in this respect as well, the reliability can be improved.
[0036]
In the embodiment described above, a material having good thermal conductivity and high rigidity and a predetermined thickness (X), such as a copper plate, is used as the core material of the substrate. It is not limited to this. When the first and second electronic components 31 and 32 generate little heat, it is not necessary to consider thermal conductivity.
[0037]
FIG. 5 is a structural diagram of another electronic component built-in multilayer substrate 30 ′ manufactured by applying the idea of the present invention. Note that the same components as those in the above-described embodiment (FIG. 1) are denoted by the same reference numerals and description thereof is omitted. The difference from FIG. 1 is that the core member 35 and the insulating resin layer 36 are not used, but instead a core member 60 in which a fiber body such as glass fiber or aramid fiber is impregnated with resin is used. It is in.
[0038]
The thickness dimension of the core member 60 is equal to a value (X + Y) obtained by adding the thickness dimension (X) of the core member 35 and the thickness dimension (Y) of the insulating resin layer 36 in the above embodiment. Openings 60a and 60b for embedding the first and second electronic components 31 and 32 are formed in the core member 60. The depth of one opening 60a is “X” and the depth of the other opening 60B. Is “X + Y”.
[0039]
Here, “X” and “Y” are values that satisfy the preceding expressions (1) and (2). Therefore, similarly to the above-described embodiment, the upper surface level at the time of mounting the first and second electronic components 31 and 32 having different thickness dimensions can be aligned to the same level (see symbol L in FIG. 1). Unlike the second conventional example described at the beginning, it is not necessary to create a transition layer (see reference numerals 25A and 25B in FIG. 9) for aligning the surface level of the substrate, and of course, polishing of the transition layer is not necessary. Therefore, an increase in the number of man-hours can be avoided and the cost can be reduced, and the object of the present invention can be achieved.
[0040]
In addition, since the upper surface level when mounting the first and second electronic components 31 and 32 having different thickness dimensions can be set to the same level (see reference L in FIG. 1), the first and second electronic components 31 and 32 can be aligned. The film thickness of the resin layer 38 for sealing the electronic components 31 and 32 can be made uniform immediately above the electronic component. As a result, the depths of the vias 42 to 45 formed in the resin layer 38 are made uniform, the processing conditions for forming the vias are unified, and good vias 42 to 45 having no variation are formed, thereby improving the reliability. .
[0041]
In addition, since the upper surface level (L) of the first and second electronic components 31 and 32 can be lower than the upper surface level of the core member 60 by a predetermined amount Z, this occurs when the resin layer 38 is formed. The core member 60 can accept most of the stress to be generated (for example, the stress generated due to the lamination of the resin film or the vacuum press bonding), and does not adversely affect the first and second electronic components 31 and 32. . Therefore, when the resin layer 38 is formed, the first and second electronic components 31 and 32 can be reliably prevented from being damaged, and in this respect as well, the reliability can be improved.
[0042]
Further, in each of the above embodiments, since the upper and lower surfaces of the substrate after embedding the electronic component can be flattened, for example, as shown in FIG. 6, on the upper surface and the lower surface of the substrate 71 after embedding the electronic component, An electronic component built-in multilayer substrate 70 in which wiring layers 72 and 73 having stacked vias 74 to 81 stacked over a plurality of layers are stacked can be configured. According to the multilayer board 70 with a built-in electronic component, since the height of the circuit pattern connected to each built-in electronic component via the via is uniform, the pressure applied to each part at the time of interlayer connection becomes uniform, Arbitrary interlayer connection by batch stacking of the wiring layers 72 and 73 (“collective stacking” means that when a multilayer substrate is manufactured, bonding and electrical connection of each layer on which a circuit pattern has been formed in advance is performed by one press. Can be reliably achieved without variation. Arbitrary interlayer connection by batch stacking includes metal bumps, metal paste bumps, and adhesive layers in interlayer connections (perforated holes in prepreg etc. with laser drill etc. and filled with conductive resin) Etc., and the like. Further, since the upper surface and the lower surface of the substrate 71 after embedding electronic components are flat, the film thicknesses of the wiring layers 72 and 73 can be made uniform, and stacking faults and interlayer connection faults can be prevented. In addition, if you cannot prepare “custom” electronic components that are pre-arranged to a predetermined thickness dimension, in other words, even if you can only prepare multiple electronic components with different thickness dimensions, you can connect each component to the circuit pattern. Since the depth of the vias can be made uniform, general-purpose components (for example, multilayer capacitors, inductors, general-purpose ICs, etc.) having different thickness dimensions can be used simultaneously in the multilayer substrate.
[0043]
【The invention's effect】
According to the present invention, in a multilayer substrate with a built-in electronic component that includes a first electronic component having a thickness dimension Ha and a second electronic component having a thickness dimension Hb (Ha <Hb), the thickness dimension X (Where X = Ha + Z; Z> 0), an opening having a depth corresponding to the dimension X is formed in the core member, the first electronic component is placed in the opening, and the core member and the core member Since it is characterized in that an opening having a depth corresponding to the dimension X + Y is formed in the laminated resin layer of thickness Y (where X + Y = Hb + Z), and the second electronic component is placed in the opening. When mounting two electronic components having different thickness dimensions, the upper surface level can be set to the same level (see reference L in FIG. 1). Therefore, unlike the second conventional example described at the beginning, it is not necessary to create a transition layer (see reference numerals 25A and 25B in FIG. 9) for aligning the surface level of the substrate. Of course, polishing of the transition layer is also possible. Since this is not necessary, the cost can be reduced by avoiding an increase in man-hours.
[Brief description of the drawings]
FIG. 1 is a structural diagram of an electronic component built-in type multilayer substrate manufactured by applying the idea of the present invention and an external view of the built-in electronic component.
FIG. 2 is a process diagram (first process to third process) of the embodiment;
FIG. 3 is a process diagram (fourth process to sixth process) according to the present embodiment;
FIG. 4 is a process diagram (seventh process to ninth process) according to the present embodiment;
FIG. 5 is a structural diagram of another electronic component built-in multilayer substrate 30 ′ manufactured by applying the idea of the present invention.
6 is a structural diagram of a multilayer board 70 with a built-in electronic component in which wiring layers 72 and 73 having stacked vias 74 to 81 stacked over a plurality of layers are stacked. FIG.
FIG. 7 is a process diagram (part 1) of the first conventional example;
FIG. 8 is a process diagram (part 2) of the first conventional example;
FIG. 9 is a process diagram of a second conventional example.
[Explanation of symbols]
30 Multi-layer board with built-in electronic components
31 Built-in electronic component (first electronic component)
32 Built-in electronic components (second electronic components)
35 Core material
35a opening
35b opening
36 Insulating resin layer
36a opening
60 core members

Claims (4)

厚さ寸法Ｈａの第１の電子部品と厚さ寸法Ｈｂ（ただし、Ｈａ＜Ｈｂ）の第２の電子部品とを内蔵する電子部品内蔵型多層基板において、
厚さ寸法Ｘ（ただし、Ｘ＝Ｈａ＋Ｚ；Ｚ＞０）のコア部材に寸法Ｘに相当する深さの開口を形成してその開口に前記第１の電子部品を入れ、
且つ、前記コア部材とそのコア部材に張り合わせた厚さ寸法Ｙ（ただし、Ｘ＋Ｙ＝Ｈｂ＋Ｚ）の絶縁樹脂層とに寸法Ｘ＋Ｙに相当する深さの開口を形成してその開口に前記第２の電子部品を入れる
ことを特徴とする電子部品内蔵型多層基板。In an electronic component built-in type multilayer substrate in which a first electronic component having a thickness dimension Ha and a second electronic component having a thickness dimension Hb (Ha <Hb) are embedded,
An opening having a depth corresponding to the dimension X is formed in a core member having a thickness dimension X (where X = Ha + Z; Z> 0), and the first electronic component is placed in the opening,
An opening having a depth corresponding to the dimension X + Y is formed in the core member and an insulating resin layer having a thickness Y (X + Y = Hb + Z) bonded to the core member, and the second electron is formed in the opening. Electronic component built-in type multilayer board characterized by containing parts. 前記コア部材は、熱伝導性と高剛性を有する素材からなることを特徴とする請求項１記載の電子部品内蔵型多層基板。2. The electronic component built-in multilayer substrate according to claim 1, wherein the core member is made of a material having thermal conductivity and high rigidity. 厚さ寸法Ｈａの第１の電子部品と厚さ寸法Ｈｂ（ただし、Ｈａ＜Ｈｂ）の第２の電子部品とを内蔵する電子部品内蔵型多層基板において、
厚さ寸法Ｘ＋Ｙ（ただし、Ｘ＝Ｈａ＋Ｚ；Ｘ＋Ｙ＝Ｈｂ＋Ｚ；Ｚ＞０）のコア部材に寸法Ｘに相当する深さの開口を形成してその開口に前記第１の電子部品を入れ、
且つ、前記コア部材に寸法Ｘ＋Ｙに相当する深さの開口を形成してその開口に前記第２の電子部品を入れる
ことを特徴とする電子部品内蔵型多層基板。In an electronic component built-in type multilayer substrate in which a first electronic component having a thickness dimension Ha and a second electronic component having a thickness dimension Hb (Ha <Hb) are embedded,
An opening having a depth corresponding to the dimension X is formed in a core member having a thickness dimension X + Y (where X = Ha + Z; X + Y = Hb + Z; Z> 0), and the first electronic component is placed in the opening.
An electronic component built-in type multilayer board, wherein an opening having a depth corresponding to the dimension X + Y is formed in the core member, and the second electronic component is inserted into the opening. 前記コア部材は、ガラス繊維又はアラミド繊維に樹脂を含浸させて硬化させたものであることを特徴とする請求項３記載の電子部品内蔵型多層基板。4. The electronic component built-in multilayer substrate according to claim 3, wherein the core member is obtained by impregnating a resin into glass fiber or aramid fiber and curing the resin.
JP2002363339A 2002-12-16 2002-12-16 Multilayer substrate with built-in electronic part Pending JP2004200201A (en)

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