JP2006513581A - マイクロシステムの製作法 - Google Patents
マイクロシステムの製作法 Download PDFInfo
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- JP2006513581A JP2006513581A JP2004567691A JP2004567691A JP2006513581A JP 2006513581 A JP2006513581 A JP 2006513581A JP 2004567691 A JP2004567691 A JP 2004567691A JP 2004567691 A JP2004567691 A JP 2004567691A JP 2006513581 A JP2006513581 A JP 2006513581A
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Abstract
電子構成素子(13)の挿入後も基体(20)の層構成を継続し、電子構成素子のコンタクト(パッド)(22,22′)を覆って垂直方向で上昇するように、導電性/熱伝導性の材料から成る構造体(23,26)を構成し、該導体材料が、電子構成素子の上位に配置された別の電子構成素子(13′)との直接的な接続を形成するか、若しくは水平方向で延びる導体路(24)を介して、パッド(22)から上昇する導体材料から、電子構成素子の側方に離れて配置された別の1つ(複数)の電子構成素子への接続を形成することを特徴とする。
Description
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Claims (17)
- 光硬化可能な材料から複数の平面内で隣り合い且つ/又は重なり合って層状に構成される基体の構成時に切り欠かれたキャビティに挿入された、互いに導電接続又は熱伝導接続されるマイクロ電子構成素子を備えたマイクロシステムの製作法において、
電子構成素子(13)の挿入後も基体(20)の層構成を継続し、電子構成素子のコンタクト(パッド)(22,22′)を覆って垂直方向で上昇するように、導電性/熱伝導性の材料から成る構造体(23,26)を構成し、該導体材料が、電子構成素子の上位に配置された別の電子構成素子(13′)との直接的な接続を形成するか、若しくは水平方向で延びる導体路(24)を介して、パッド(22)から上昇する導体材料から、電子構成素子の側方に離れて配置された別の1つ(複数)の電子構成素子への接続を形成することを特徴とする、マイクロシステムの製作法。 - 垂直方向で上昇する導体構造を、連続した層内でパッド(22)の上位にあけられた開口内にスクリーン印刷で形成し、この場合、光硬化可能な材料層内でパッド(22)の上位にあけられた開口を導電性の材料で満たし、その後最終的に水平方向で延びる導体路を印刷する、請求項1記載の方法。
- 前記の導電性の材料が接着剤である、請求項2記載の方法。
- 垂直方向で上昇する導電性の構造体(26)を、対応する型板(25)の開口を介して各パッド(22)に付与されるはんだペースト堆積物から形成し、このはんだペースト堆積物を、次のステップで型板(25)を取り外した後に加熱によってはんだボール(バンプ)に成形し、基体(20)を引き続き層状に構成し且つ適当なキャビティ(28)を形成した後で、該キャビティに、予め形成したバンプ(27)が第2の構成素子(13′)のパッド(22′)と接続されるように、別の電子構成素子(13′)を挿入する、請求項1記載の方法。
- 請求項2及び請求項4記載の手段を組み合わせる、請求項1から4までのいずれか1項記載の方法。
- 少なくとも一方が電磁波透過性の2枚のプレート間でマイクロシステムを層状に構成し、この場合、プレート間に光硬化可能な材料から成る液体が存在しており、該液体を、層毎にメモリされた形成しようとする構造体の3Dモデルに対応して層状に露光して硬化させる、請求項1から5までのいずれか1項記載の方法。
- 少なくとも1対のローラ間でマイクロシステムを層状に構成し、ローラ間の領域に光硬化可能な液体を充填し、各液体層の露光を、ローラ及びその時々の層構造に対応したマスクを介して行う、請求項1から5までのいずれか1項記載の方法。
- ローラ(2,3)間の間隔が可変の少なくとも1対のローラ(1,1′,1″,1′″)が設けられており、該ローラ対(1,1′,1″,1′″)の各1つのローラ(2)(露光ローラ)が電磁波透過性材料から成っており、該ローラ(2)内に電磁波送出源(5)(光源)が配置されており、電磁波透過域及び非透過域を備えた、各露光ローラ(2)に対応配置されたマスク(10)が設けられており且つ少なくとも1対のローラ(1,1′,1″,1′″)を通って案内される基板支持体シート(7)が、形成される構造体(11)のためのベースとして設けられていることを特徴とする、請求項7記載の方法を実施するための装置。
- マスクが露光ローラ(2)の表面に被着されている、請求項8記載の装置。
- 露光ローラ(2)において、光源(5)とローラ表面との間に定置の露光スリット(6)が配置されており、マスクが、スリット(6)の下位で露光ローラ(2)の表面の傍らを案内される帯状シート(10)として形成されている、請求項8記載の装置。
- 複数のローラ対が連続して相前後して配置されている、請求項9又は10記載の装置。
- 個々のローラ対(1,1′,1″,1′″)間に洗浄装置が配置されている、請求項9から11までのいずれか1項記載の装置。
- ローラ対(1,1′,1″,1′″)間にシート巻成体(112,15)が配置されており、該シート巻成体のシートが、接着剤層及び/又は電気的及び/又は電子的及び/又は機械的及び/又は光学的及び/又は生物的な構成素子(13)のための支持体として形成されている、請求項9から12までのいずれか1項記載の装置。
- ローラ対(1,1′,1″,1′″)間にシート巻成体が配置されており、シートが規定された物理的若しくは化学的特性を有している、請求項9から12までのいずれか1項記載の装置。
- 少なくとも露光ローラ(2)に付着防止コーティングが施されている、請求項9から14までのいずれか1項記載の装置。
- 少なくとも1つのローラ対(1,1′,1″,1′″)に少なくとも1つの加熱装置が後置されている、請求項9から15までのいずれか1項記載の装置。
- 少なくとも1つのローラ対(1,1′,1″,1′″)に少なくとも1つのスクリーン印刷装置が後置されている、請求項9から16までのいずれか1項記載の装置。
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PCT/DE2003/000419 WO2004070835A1 (de) | 2003-01-17 | 2003-02-13 | Verfahren zur herstellung von mikrosystemen |
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US (1) | US8042267B2 (ja) |
EP (1) | EP1586117B1 (ja) |
JP (1) | JP4567466B2 (ja) |
KR (1) | KR100756104B1 (ja) |
CN (1) | CN100435331C (ja) |
AU (1) | AU2003214001B2 (ja) |
CA (1) | CA2513127C (ja) |
DE (1) | DE10394193D2 (ja) |
IS (1) | IS7981A (ja) |
NO (1) | NO20053151L (ja) |
RU (1) | RU2323504C2 (ja) |
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WO (1) | WO2004070835A1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102006008332B4 (de) * | 2005-07-11 | 2009-06-04 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zur Herstellung einer funktionellen Baueinheit und funktionelle Baueinheit |
WO2008153674A1 (en) | 2007-06-09 | 2008-12-18 | Boris Kobrin | Method and apparatus for anisotropic etching |
JP5102879B2 (ja) * | 2008-01-22 | 2012-12-19 | ローイス インコーポレイテッド | 大面積ナノパターン形成方法および装置 |
US8518633B2 (en) | 2008-01-22 | 2013-08-27 | Rolith Inc. | Large area nanopatterning method and apparatus |
US8182982B2 (en) | 2008-04-19 | 2012-05-22 | Rolith Inc | Method and device for patterning a disk |
US8192920B2 (en) * | 2008-04-26 | 2012-06-05 | Rolith Inc. | Lithography method |
US20110210480A1 (en) * | 2008-11-18 | 2011-09-01 | Rolith, Inc | Nanostructures with anti-counterefeiting features and methods of fabricating the same |
EP2609467A4 (en) | 2010-08-23 | 2014-07-30 | Rolith Inc | MASK FOR NEAR FIELD LITHOGRAPHY AND ITS MANUFACTURE |
US9398694B2 (en) | 2011-01-18 | 2016-07-19 | Sony Corporation | Method of manufacturing a package for embedding one or more electronic components |
US9763370B2 (en) | 2013-03-15 | 2017-09-12 | National Technology & Engineering Solutions Of Sandia, Llc | Apparatus for assembly of microelectronic devices |
RU2602835C9 (ru) * | 2015-05-13 | 2017-02-02 | Акционерное общество "Концерн радиостроения "Вега" | Способ экранирования в электронном модуле |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06140461A (ja) * | 1992-10-29 | 1994-05-20 | Fujitsu Ltd | 半導体チップの実装方法および実装構造体 |
JPH10229161A (ja) * | 1996-12-09 | 1998-08-25 | Sony Corp | 電子部品及び電子部品の製造方法 |
WO2000067538A1 (en) * | 1999-04-16 | 2000-11-09 | Jorma Kalevi Kivilahti | Method for manufacturing solderless high density electronic modules |
JP2002290051A (ja) * | 2001-01-19 | 2002-10-04 | Matsushita Electric Ind Co Ltd | 部品内蔵モジュールとその製造方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3712735A (en) * | 1970-09-25 | 1973-01-23 | Amp Inc | Apparatus for photo etching |
US4069916A (en) * | 1976-06-01 | 1978-01-24 | Western Electric Co., Inc. | Tape for holding electronic articles |
US4383363A (en) * | 1977-09-01 | 1983-05-17 | Sharp Kabushiki Kaisha | Method of making a through-hole connector |
DE3925455A1 (de) * | 1989-08-01 | 1991-02-14 | Robert Hanus | Belichtungsvorrichtung zum belichten eines metallkaschierten basismaterials |
DE4223371A1 (de) * | 1992-07-16 | 1994-01-20 | Thomson Brandt Gmbh | Verfahren und Platine zur Montage von Bauelementen |
DE4420996C2 (de) | 1994-06-16 | 1998-04-09 | Reiner Dipl Ing Goetzen | Verfahren und Vorrichtung zur Herstellung von mikromechanischen und mikrooptischen Bauelementen |
US5869395A (en) * | 1997-01-22 | 1999-02-09 | Lsi Logic Corporation | Simplified hole interconnect process |
DE19721170A1 (de) * | 1997-05-21 | 1998-11-26 | Emtec Magnetics Gmbh | Verfahren und Vorrichtung zum Herstellen eines Films oder einer Schicht mit beidseitiger Oberflächenstruktur |
US6833613B1 (en) * | 1997-12-18 | 2004-12-21 | Micron Technology, Inc. | Stacked semiconductor package having laser machined contacts |
US6160714A (en) * | 1997-12-31 | 2000-12-12 | Elpac (Usa), Inc. | Molded electronic package and method of preparation |
DE19826971C2 (de) | 1998-06-18 | 2002-03-14 | Reiner Goetzen | Verfahren zum mechanischen und elektrischen Verbinden von Systembauteilen |
DE19847088A1 (de) * | 1998-10-13 | 2000-05-18 | Ksw Microtec Ges Fuer Angewand | Flächig ausgebildeter Träger für Halbleiter-Chips und Verfahren zu seiner Herstellung |
JP2001237512A (ja) * | 1999-12-14 | 2001-08-31 | Nitto Denko Corp | 両面回路基板およびこれを用いた多層配線基板ならびに両面回路基板の製造方法 |
DE10144579C2 (de) | 2001-08-07 | 2003-12-04 | Reiner Goetzen | Verfahren und Vorrichtung zur Herstellung von Fein- bis Mikrostrukturen und/oder komplexen Mikrosystemen |
WO2010144579A2 (en) | 2009-06-10 | 2010-12-16 | Baker Hughes Incorporated | Source compensated formation density measurement method by using a pulsed neutron generator |
-
2003
- 2003-02-13 CN CNB038258293A patent/CN100435331C/zh not_active Expired - Fee Related
- 2003-02-13 EP EP03709608.8A patent/EP1586117B1/de not_active Expired - Lifetime
- 2003-02-13 KR KR1020057013225A patent/KR100756104B1/ko not_active IP Right Cessation
- 2003-02-13 JP JP2004567691A patent/JP4567466B2/ja not_active Expired - Fee Related
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- 2003-02-13 AU AU2003214001A patent/AU2003214001B2/en not_active Ceased
- 2003-02-13 US US10/542,237 patent/US8042267B2/en not_active Expired - Fee Related
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- 2003-02-13 CA CA2513127A patent/CA2513127C/en not_active Expired - Fee Related
- 2003-04-22 TW TW092109309A patent/TWI221827B/zh not_active IP Right Cessation
-
2005
- 2005-06-28 NO NO20053151A patent/NO20053151L/no not_active Application Discontinuation
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06140461A (ja) * | 1992-10-29 | 1994-05-20 | Fujitsu Ltd | 半導体チップの実装方法および実装構造体 |
JPH10229161A (ja) * | 1996-12-09 | 1998-08-25 | Sony Corp | 電子部品及び電子部品の製造方法 |
WO2000067538A1 (en) * | 1999-04-16 | 2000-11-09 | Jorma Kalevi Kivilahti | Method for manufacturing solderless high density electronic modules |
JP2002290051A (ja) * | 2001-01-19 | 2002-10-04 | Matsushita Electric Ind Co Ltd | 部品内蔵モジュールとその製造方法 |
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KR20050091785A (ko) | 2005-09-15 |
RU2005126055A (ru) | 2006-01-10 |
KR100756104B1 (ko) | 2007-09-05 |
US8042267B2 (en) | 2011-10-25 |
EP1586117B1 (de) | 2014-06-18 |
TW200413245A (en) | 2004-08-01 |
DE10394193D2 (de) | 2005-12-01 |
NO20053151L (no) | 2005-10-14 |
RU2323504C2 (ru) | 2008-04-27 |
IS7981A (is) | 2005-08-15 |
AU2003214001A1 (en) | 2004-08-30 |
NO20053151D0 (no) | 2005-06-28 |
AU2003214001B2 (en) | 2007-08-02 |
CN1735965A (zh) | 2006-02-15 |
TWI221827B (en) | 2004-10-11 |
CN100435331C (zh) | 2008-11-19 |
EP1586117A1 (de) | 2005-10-19 |
US20060072295A1 (en) | 2006-04-06 |
WO2004070835A1 (de) | 2004-08-19 |
JP4567466B2 (ja) | 2010-10-20 |
CA2513127A1 (en) | 2004-08-19 |
CA2513127C (en) | 2010-03-30 |
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