JP2006339221A - Semiconductor packaging tape carrier tape and its manufacturing method - Google Patents

Semiconductor packaging tape carrier tape and its manufacturing method Download PDF

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JP2006339221A
JP2006339221A JP2005158957A JP2005158957A JP2006339221A JP 2006339221 A JP2006339221 A JP 2006339221A JP 2005158957 A JP2005158957 A JP 2005158957A JP 2005158957 A JP2005158957 A JP 2005158957A JP 2006339221 A JP2006339221 A JP 2006339221A
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layer
stage
plating layer
plating
solder resist
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JP4618006B2 (en
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Yutaka Yoshikawa
吉川　　裕
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Toppan Inc
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Toppan Printing Co Ltd
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<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of restraining grooved scraping on a Cu surface and abnormal separation of an Sn plated layer or the like in electroless Sn plating processing of the manufacture of a semiconductor packaging tape carrier tape. <P>SOLUTION: The semiconductor packaging tape carrier tape comprises a base member 11 on one side of which a copper layer wiring pattern 12 is formed, first stage or second stage Sn plated layer formed on the entire surface of the pattern, and a solder resist pattern 13 formed on the entire surface of the first stage Sn plated layer. The manufacturing method thereof comprises a step of forming the solder resist pattern on a base member surface after the first stage Sn plated layer 16 is formed on the surface of a Cu layer wiring pattern prior to the formation of the solder resist pattern, removing only an exposed Sn plated layer partition taking the solder resist pattern as a mask and using predetermined chemicals for corrosion, simultaneously removing a cause material residual on the surface of the exposed Sn plated layer, and then forming an Sn plated layer 17 on the removal surface. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体実装用テープキャリアテープ及びその製造方法に関する。   The present invention relates to a tape carrier tape for semiconductor mounting and a manufacturing method thereof.

近年、半導体装置では、小型化、高機能化している。その半導体装置に用いる半導体でもさらに配線パターンが高密度化、微細化されるている。この傾向に伴い、半導体を実装する配線基板は、高密度化及び微細化に適した半導体実装用テープキャリアテープが使用される頻度が増加傾向になっている。   In recent years, semiconductor devices have become smaller and more functional. Even in the semiconductor used for the semiconductor device, the wiring pattern is further densified and miniaturized. With this tendency, the frequency of using a semiconductor carrier tape carrier tape suitable for high density and miniaturization is increasing in the wiring board for mounting the semiconductor.

図３は、従来の半導体実装用テープキャリアテープの部分拡大の側断面図である。図３（ａ）は、通常品であり、図３（ｂ）は２段めっきの半導体実装用テープキャリアテープである。   FIG. 3 is a partially enlarged side sectional view of a conventional semiconductor mounting tape carrier tape. FIG. 3A is a normal product, and FIG. 3B is a two-step plated semiconductor mounting tape carrier tape.

図３（ａ）に示す従来の半導体実装用テープキャリアテープの一例の製造方法について説明する。最初に、金型を用いてスプロケットホール及びパンチ孔の穿孔形成した後、該２０〜１２５μｍ厚のポリイミドフイルム１と、長尺の９〜２５μｍ厚の銅箔とを接着剤を介して貼り合せて銅箔フイルムを製造する。   A manufacturing method of an example of a conventional tape mounting tape for semiconductor mounting shown in FIG. First, after forming a sprocket hole and a punch hole using a mold, the polyimide film 1 having a thickness of 20 to 125 μm and a long copper foil having a thickness of 9 to 25 μm are bonded together with an adhesive. A copper foil film is produced.

次に、銅箔フイルムの銅面に感光性のレジストを形成する。次に、レジスト面にフォトマスクを介して露光処理後、該レジストへ現像処理、レジストをマスクとして露出した銅面をエッチング処理、及びレジスト剥膜処理を実行して、銅層よりなる配線パターン１２（Ｃｕ配線パターンと記す）を形成する。以上のポリイミドフイルムの準備からＣｕ配線パターン１２までの製造では、公知の方法であり、公知の材料を用いて、フォトプロセス法によるパターンを形成するものである。   Next, a photosensitive resist is formed on the copper surface of the copper foil film. Next, after the resist surface is exposed through a photomask, the resist pattern is developed, the exposed copper surface is etched using the resist as a mask, and the resist stripping process is performed to form a wiring pattern 12 made of a copper layer. (Referred to as Cu wiring pattern). The manufacture from the preparation of the polyimide film to the Cu wiring pattern 12 is a known method, and a pattern is formed by a photo process method using a known material.

次に、Ｃｕ配線パターン１２を形成した銅箔フイルム１では、Ｃｕ配線パターンからポリイミドフイルム上の全面部にフォトソルダーレジスト（以下ＰＳＲと記す）を塗布し、レジストを層形成する。次に、ＰＳＲのレジスト面にＰＳＲ用フォトマスクを介して、露光処理後、該レジストへ現像処理を実行して、ＰＳＲ層よりなる配線の保護パターン（ＰＳＲパターンと記す）を形成した後、１５０℃／８０分間の加熱するＰＳＲポストキュア処理して、１０〜１２５μｍ厚のＰＳＲパターン１３を形成する。次に、ＰＳＲパターンより露出したＣｕ配線パターンのＣｕ配線部分に０．０１〜０．５μｍ厚の錫めっき（以下Ｓｎめっきと記す）を形成したあと、１３０℃／９０分間の加熱するＳｎめっきアニール処理して、半導体実装用テープキャリアテープが製造される（特許文献１参照）。   Next, in the copper foil film 1 on which the Cu wiring pattern 12 is formed, a photo solder resist (hereinafter referred to as PSR) is applied to the entire surface of the polyimide film from the Cu wiring pattern, and a layer of the resist is formed. Next, after exposure processing is performed on the resist surface of the PSR through a PSR photomask, development processing is performed on the resist to form a wiring protection pattern (referred to as a PSR pattern) made of a PSR layer, and then 150 The PSR pattern 13 having a thickness of 10 to 125 μm is formed by performing a PSR post-cure process of heating at 80 ° C./80 minutes. Next, tin plating annealing of 0.01 to 0.5 μm thickness (hereinafter referred to as Sn plating) is formed on the Cu wiring portion of the Cu wiring pattern exposed from the PSR pattern, and then heated at 130 ° C. for 90 minutes. The tape carrier tape for semiconductor mounting is manufactured by processing (see Patent Document 1).

図３（ａ）は、前記の製造方法による半導体実装用テープキャリアテープである。ポリイミドフイルム１の基材の上面に、Ｃｕ配線層２形成されている。その上面にＰＳＲ層３が形成され、ＰＳＲ層の開口部４にはＳｎめっき層５が区画分離して形成されている。前記ＰＳＲ層３の区画では、その下面のＣｕ配線２を保護する役割である。また、前記Ｓｎめっき層５の形成区画では、接続端子部の役割となる。一方、ポリイミドフイルムの基材の下面は、前記パンチ孔の孔内に導通路を形成し、該導通路を介して上面配線層と導通回路を形成し、前記導通路は接続端子部となる（図表示せず）。   FIG. 3A shows a tape carrier tape for semiconductor mounting by the above manufacturing method. A Cu wiring layer 2 is formed on the upper surface of the base material of the polyimide film 1. A PSR layer 3 is formed on the upper surface, and an Sn plating layer 5 is formed in the opening 4 of the PSR layer in a partitioned manner. The section of the PSR layer 3 serves to protect the Cu wiring 2 on the lower surface thereof. Moreover, in the formation division of the said Sn plating layer 5, it becomes a role of a connection terminal part. On the other hand, the lower surface of the polyimide film substrate forms a conduction path in the hole of the punch hole, and forms a conduction circuit with the upper surface wiring layer through the conduction path, and the conduction path becomes a connection terminal portion ( (Not shown).

図３（ａ）の従来の半導体実装用テープキャリアテープが製造方法では、以下の問題がある。前記Ｓｎめっきの工程では、表面のＰＳＲパターンの側端部と、下面のＣｕ配線パターンの接点近傍にＳｎめっき液がもぐり込むことにより、該部に局部電池が形成される。   The manufacturing method of the conventional tape mounting tape for semiconductor mounting shown in FIG. 3A has the following problems. In the Sn plating step, a local battery is formed in the portion of the PSR pattern on the surface and the Sn plating solution that has penetrated in the vicinity of the contact point of the Cu wiring pattern on the lower surface.

この局部電池の作用により、Ｃｕ配線の表面に溝状にエグレ等の異常溶出された部分と、一方では、Ｓｎめっき層の異常析出する等の部分とが発生により、後工程での半導体実装時、Ｓｕ―Ｃｕ配線５，１２の折れ不良、断線不良の原因となる。   Due to the action of the local battery, a portion that is abnormally eluted such as an aglet in the shape of a groove on the surface of the Cu wiring and a portion that abnormally precipitates the Sn plating layer, on the other hand, are generated. As a result, the Su—Cu wirings 5 and 12 may be broken or disconnected.

この局部電池は、置換反応による無電解Ｓｎめっきにおいて、ＳｕとＣｕが置換される際、めっき面で均一な置換反応が出来ずに、局所的に偏りが生じることで形成される現象である。   This local battery is a phenomenon that is formed when local displacement occurs in the electroplated Sn plating by substitution reaction when Su and Cu are substituted and a uniform substitution reaction cannot be performed on the plating surface.

従来の半導体実装用テープキャリアテープが製造方法のＳｎめっきの工程では、通常、Ｃｕ配線の大部分の表面は均一な置換反応が実行されるが、ＰＳＲパターン側端部のＣｕ配線との接点近傍の界面にＳｎめっき液がもぐり込み、その接点を境界にＰＳＲ側では、Ｃｕの異常溶出と、その境界にＣｕ配線では、Ｓｎの異常析出となり、新たな電子の供給元があらわれることにより、前記接点近傍の界面に置換反応が偏り、局部電池が形成され、Ｃｕ表面の溝状にエグレ、又はＳｎめっき層の異常析出等が発生する。   In the process of Sn plating of a conventional tape mounting tape for semiconductor mounting, which is a manufacturing method, the surface of most of the Cu wiring is usually subjected to a uniform substitution reaction, but in the vicinity of the contact with the Cu wiring at the end of the PSR pattern side. The Sn plating solution squeezes into the interface, and Cu abnormally elutes on the PSR side with the contact as a boundary, and Sn abnormal precipitation occurs on the boundary with the Cu wiring, and a new electron supply source appears. The substitution reaction is biased at the interface in the vicinity of the contact, a local battery is formed, and the groove on the Cu surface is aggre-formed or abnormal deposition of the Sn plating layer occurs.

近年、このＣｕ表面の溝状にエグレ、又はＳｎめっき層の異常析出等が発生を抑制する製造方法が提案されている（特許文献２参照）。この方法では、ＰＳＲパターンの形成前に、予め、Ｃｕ配線パターン上に１段目のＳｎめっきを施し、Ｓｕ―Ｃｕ配線パターンを形成した後、ＰＳＲパターンを形成した後、２段目のＳｎめっきの工程を実行するため、Ｃｕ表面の溝状にエグレ、又はＳｎめっき層の異常析出等が発生を抑制することが出来るとしている（図３（ｂ）参照）。   In recent years, there has been proposed a manufacturing method that suppresses the occurrence of abnormal precipitation or the like of the agglomeration or Sn plating layer in a groove shape on the Cu surface (see Patent Document 2). In this method, before the PSR pattern is formed, the first stage of Sn plating is performed on the Cu wiring pattern in advance, the Su—Cu wiring pattern is formed, the PSR pattern is formed, and then the second stage of Sn plating is performed. In order to execute this process, it is said that the occurrence of egre in the groove shape on the Cu surface or abnormal deposition of the Sn plating layer can be suppressed (see FIG. 3B).

図３（ｂ）は、前記の２段めっきの製造方法による半導体実装用テープキャリアテープである。しかし、図３（ｂ）の前記２段めっきの製造方法では、最初に、長尺のポリイミドフイルムを用いて、金形を用いたパンチ孔を形成後、長尺の銅箔と接着剤を介して貼り合せ、銅箔フイルムの銅面に感光性のレジスト形成、露光処理後、該レジストをフォトプロセス法により、Ｃｕ配線パターン１２を形成する。次に、Ｃｕ配線パターン上に１段目のＳｎめっきを形成し、１３０℃／９０分の加熱処理のＳｎめっきアニールの処理して１段目のＳｎめっき層１６を形成した後、該１段目のＳｎ／Ｃｕ配線（拡散層８が付加）パターンからポリイミドフイルム上の全面部にフォトソルダーレジスト（以下ＰＳＲと記す）を塗布後、フォトプロセス法により、ＰＳＲパターンを形成し、１５０℃／８０分の高温加熱処理のＰＳＲポストキュアの処理をしてＰＳＲパターン１３を形成する。次に、ＰＳＲパターン１３より露出した１段目のＳｎ―Ｃｕ配線パターンの上面に２段目のＳｎめっきを形成し、１３０℃／９０分の加熱処理のＳｎめっきアニールの処理を行い２段目のＳｎめっき層１７を形成して、半導体実装用テープキャリアテープが製造される。   FIG. 3B shows a semiconductor carrier tape carrier tape produced by the two-step plating method. However, in the two-step plating manufacturing method of FIG. 3B, first, a punch hole using a mold is formed using a long polyimide film, and then a long copper foil and an adhesive are used. Then, after a photosensitive resist is formed on the copper surface of the copper foil film and exposed, a Cu wiring pattern 12 is formed on the resist by a photo process method. Next, the first-stage Sn plating is formed on the Cu wiring pattern, and the first-stage Sn-plating layer 16 is formed by heat-treatment Sn-plating annealing at 130 ° C./90 minutes. A photo solder resist (hereinafter referred to as PSR) is applied to the entire surface of the polyimide film from the Sn / Cu wiring (added diffusion layer 8) pattern of the eye, and then a PSR pattern is formed by a photo process method. A PSR pattern 13 is formed by performing a PSR post-cure process of high temperature heat treatment for a minute. Next, the second-stage Sn plating is formed on the upper surface of the first-stage Sn—Cu wiring pattern exposed from the PSR pattern 13, and the second-stage Sn plating annealing is performed at 130 ° C./90 minutes. The Sn plating layer 17 is formed, and a tape carrier tape for semiconductor mounting is manufactured.

前記の半導体実装用テープキャリアテープでは、ポリイミドフイルム１の基材の上面に、Ｃｕ配線層２形成されている。そのＣｕ配線層２の上面に、１段目のＳｎめっき層６が形成されている。その上面にＰＳＲ層３が形成され、ＰＳＲ層の開口部４には２段目のＳｎめっき層７が区画分離して形成されている。この製造方法では、ＰＳＲ層３の形成後に１５０℃／８０分の高温加熱処理のＰＳＲポストキュアがあり、その高温加熱処理により１段目のＳｎ―Ｃｕ配線層（拡散層８が付加され）が形成され、その上面にＰＳＲ層３、又は２段目のＳｎめっき層７が区画分離して形成されている。前記ＰＳＲ層３の形成区画では、Ｓｎ―Ｃｕ配線の保護を役割とし、前記２段目のＳｎめっき層７の形成区画では、拡散層が形成しない、２段目のＳｎめっき（純Ｓｎめっき）／１段目のＳｎ―Ｃｕの配線層は接続端子部となる。   In the semiconductor carrier tape carrier tape, the Cu wiring layer 2 is formed on the upper surface of the base material of the polyimide film 1. A first-stage Sn plating layer 6 is formed on the upper surface of the Cu wiring layer 2. A PSR layer 3 is formed on the upper surface, and a second-stage Sn plating layer 7 is formed in the opening 4 of the PSR layer by separating and separating. In this manufacturing method, after the formation of the PSR layer 3, there is a PSR post cure of high temperature heat treatment at 150 ° C./80 minutes, and the first stage Sn—Cu wiring layer (with the diffusion layer 8 added) is formed by the high temperature heat treatment. The PSR layer 3 or the second-stage Sn plating layer 7 is partitioned and formed on the upper surface. The formation section of the PSR layer 3 serves to protect the Sn—Cu wiring, and the formation section of the second stage Sn plating layer 7 does not form a diffusion layer. Second stage Sn plating (pure Sn plating) / The first-level Sn—Cu wiring layer serves as a connection terminal portion.

１段目のＳｎ―Ｃｕ配線パターンは、ＳｎとＣｕとの界面近傍で拡散層を形成したものであり、Ｓｎめっき層が、１３０℃／９０分の加熱処理のＳｎめっきアニールと、その後
工程での１５０℃／８０分の高温加熱処理のＰＳＲポストキュアの加熱処理されたものである。一方、２段目のＳｎめっき／Ｓｎ―Ｃｕ配線パターンは、ＳｎとＳｎ―Ｃｕとの界面近傍で拡散層を形成せず、Ｓｎめっき層が、１３０℃／９０分の加熱処理のＳｎめっきアニールのみ加熱処理されたものであり、高温加熱処理のない純Ｓｎめっきである。なお、Ｓｎ／Ｓｎ―Ｃｕは２層構造を示し、上層のＳｎと、その下にＳｎ―Ｃｕ、すなわち、ＳｎとＣｕの界面に拡散層を形成した層を示している。 The first-stage Sn—Cu wiring pattern is formed by forming a diffusion layer near the interface between Sn and Cu. The Sn plating layer is formed by Sn plating annealing at 130 ° C./90 minutes, followed by subsequent steps. PSR post-cure heat-treated at 150 ° C./80 minutes. On the other hand, the second-stage Sn plating / Sn—Cu wiring pattern does not form a diffusion layer in the vicinity of the Sn-Sn—Cu interface, and the Sn plating layer is Sn-plated annealed at 130 ° C./90 minutes. It is pure Sn plating which is only heat-treated and has no high-temperature heat treatment. Sn / Sn—Cu indicates a two-layer structure, and Sn is an upper layer and Sn—Cu below it, that is, a layer in which a diffusion layer is formed at the interface between Sn and Cu.

Ｃｕ面に無電解のＳｎめっき層（図３（ｂ）の１段目のＳｎめっき層６）の形成について簡単に説明する。Ｓｎイオンを含むＳｎめっき液層中に銅基材を浸漬させ、反応を実行させる。反応は、まずＣｕとめっき溶液の薬品（チオ尿素）と化学反応し、Ｃｕ化合物が溶出し、同時に電子が生成されるＣｕの溶出が起きる。一方、前記液中に生成された電子は、液中のＳｎイオンと合体し、Ｓｎの析出するもので、すなわち、ＣｕからＳｎへ置換する置換めっきである。通常、Ｃｕが１．０７ｇ溶出すると、同時進行で、Ｓｎが１ｇ析出する無電解のＳｎめっき法である。その置換速度は、Ｓｎめっきが進むと、Ｃｕ露出面からＣｕが溶出しながら、それと同量のＳｎが該Ｃｕ露出面に析出する。さらに進行する（めっき液中への浸漬時間が長くなる）と、Ｃｕ露出面のＳｎめっき層厚が厚くなる程、該Ｃｕ露出面からのＣｕが溶出が減少するため、置換速度（めっき層生成速度）は低下する。同時に、浸漬時間が長くなる程、レジスト界面剥離、例えば配線面上のＰＳＲ側端部にＳｎめっき液がＰＳＲ下面まで侵入し、ＰＳＲ下面の剥離、Ｓｎめっき液侵入が発生し、ＰＳＲ下面の剥離面が発生する。ＰＳＲ側端部の剥離面近傍では、めっき液が侵入し、且つＣｕが露出する環境となり、該露出するＣｕから、電子が供給され、液中のチオ尿素の高い濃度部、例えばＳｎめっき層でＳｎを析出する。前記ＰＳＲ側端部の剥離面近傍では、局部電池とした。   The formation of the electroless Sn plating layer (the first stage Sn plating layer 6 in FIG. 3B) on the Cu surface will be briefly described. A copper base material is immersed in the Sn plating solution layer containing Sn ions, and the reaction is performed. The reaction first chemically reacts with Cu and the chemical of the plating solution (thiourea) to elute the Cu compound, and at the same time, elution of Cu that generates electrons occurs. On the other hand, the electrons generated in the liquid are combined with Sn ions in the liquid to precipitate Sn, that is, displacement plating that substitutes from Cu to Sn. Usually, when 1.07 g of Cu elutes, it is an electroless Sn plating method in which 1 g of Sn precipitates simultaneously. As for the substitution rate, when Sn plating proceeds, Cu is eluted from the Cu exposed surface, and the same amount of Sn is deposited on the Cu exposed surface. As it progresses further (dipping time in the plating solution becomes longer), the elution of Cu from the exposed Cu surface decreases as the Sn plating layer thickness on the exposed Cu surface increases. Speed) decreases. At the same time, the longer the immersion time, the resist interface peeling, for example, the Sn plating solution penetrates into the PSR side end on the wiring surface, the PSR bottom surface peeling, the Sn plating solution penetration occurs, and the PSR bottom surface peeling. A surface is generated. In the vicinity of the peeled surface at the end of the PSR side, the plating solution penetrates and Cu is exposed, electrons are supplied from the exposed Cu, and a high concentration portion of thiourea in the solution, for example, Sn plating layer Sn is deposited. A local battery was used in the vicinity of the peeled surface at the PSR side end.

Ｓｎ―Ｃｕ面に無電解のＳｎめっき層（図３（ｂ）の２段目のＳｎめっき層７）の形成について簡単に説明する。前記テープキャリアテープの製造において、２段目のＳｎめっきでは、Ｓｎ―Ｃｕ配線の表面に隙間腐食の原因となる物質残渣、例えば、ＰＳＲ用現像液等が残存し、該物質残渣がめっき途中時に剥がれ、その剥がれた部分とそれ以外の部分との間にＣｕの析出量が異なるため、すなわち剥がれた部分からＣｕの異常析出され、局部電池が発生する問題が生じる。   The formation of the electroless Sn plating layer (second stage Sn plating layer 7 in FIG. 3B) on the Sn—Cu surface will be briefly described. In the production of the tape carrier tape, in the second stage of Sn plating, a substance residue causing crevice corrosion, such as a developer for PSR, remains on the surface of the Sn—Cu wiring, and the substance residue is in the middle of plating. Since the amount of Cu deposition is different between the peeled portion and the other portions, that is, Cu is abnormally precipitated from the peeled portion, and a local battery is generated.

前記局部電池では、物質残渣跡にＣｕクワレ（Ｃｕ腐食）が発生、例えばＳｎ―Ｃｕ配線が腐食される場合がある。品質不良となる問題がある。従来のＳｎめっき／Ｓｎ―Ｃｕ配線部分の形成時の純Ｓｎめっきの工程では、前述したＳｎ―Ｃｕ配線の表面に腐食部分が形成され、表面の溝状にＣｕ腐食、又はＳｎの異常析出等が発生する場合がある。   In the local battery, Cu residue (Cu corrosion) may be generated in the residue residue, for example, Sn—Cu wiring may be corroded. There is a problem that results in poor quality. In the process of pure Sn plating at the time of forming a conventional Sn plating / Sn—Cu wiring portion, a corroded portion is formed on the surface of the Sn—Cu wiring described above, Cu corrosion in the surface groove shape, abnormal precipitation of Sn, etc. May occur.

前記Ｓｎ―Ｃｕ配線を形成した表面は、Ｓｎめっきの影響から粗化され、フォトソルダーレジスト物質残渣が発生し易い問題もある。   The surface on which the Sn—Cu wiring is formed is roughened due to the influence of Sn plating, and there is a problem that a photo solder resist material residue is likely to be generated.

以下に公知文献を記す。
特許第３０６１６１３号公報 特許第３０７６３４２号公報 The known literature is described below.
Japanese Patent No. 3061613 Japanese Patent No. 3076342

本発明の課題は、無電解Ｓｎめっき処理において、Ｃｕ表面の溝状にエグレ、又はＳｎめっき層の異常析出等の製品不良の要因である局部電池の形成を抑制するため、隙間腐食の原因物質残査をＣｕ表面上から除去することをである。   The object of the present invention is to prevent crevice corrosion in order to suppress the formation of local batteries which are the cause of product defects such as agglomeration in the shape of grooves on the Cu surface or abnormal deposition of the Sn plating layer in the electroless Sn plating treatment. The residue is removed from the Cu surface.

本発明の請求項１に係る発明は、絶縁性のフイルム基材に銅箔を貼り合わせ、該銅箔をエッチング処理により、配線パターンが形成された、半導体装置を実装するための半導体実装用テープキャリアテープの製造方法において、Ｃｕ層よりなる配線パターンを形成したフイルム基材にソルダーレジスト樹脂を塗布する前に、Ｃｕ層よりなる配線パターン表面の全面にＳｎめっき層を形成した後、フイルム基材表面の全面に、熱硬化性で、光感光性のソルダーレジスト樹脂を塗布し、現像処理し、ソルダーレジストパターンを形成後、前記ソルダーレジストパターンをマスクにして、所定の腐食用薬品を用いて、露出したＳｎめっき層区画のみを除去し、併せて、露出したＳｎめっき層の表面に残存する隙間腐食の原因物質も除去処理した後、前記露出した区画の上全面に、再度、Ｓｎめっき層を区画形成することを特徴とする半導体実装用テープキャリアテープの製造方法である。   The invention according to claim 1 of the present invention is a semiconductor mounting tape for mounting a semiconductor device, wherein a copper foil is bonded to an insulating film substrate, and a wiring pattern is formed by etching the copper foil. In the manufacturing method of the carrier tape, before applying the solder resist resin to the film base material on which the wiring pattern made of the Cu layer is formed, after forming the Sn plating layer on the entire surface of the wiring pattern made of the Cu layer, the film base material The entire surface is coated with a thermosetting and photosensitive solder resist resin, developed, and after forming a solder resist pattern, using the solder resist pattern as a mask, using a predetermined corrosive chemical, After removing only the exposed Sn plating layer section, and also removing the causative substances remaining on the surface of the exposed Sn plating layer, Serial over the entire surface of the exposed sections, again, a semiconductor mounting tape carrier tape manufacturing method, characterized by defining a Sn plating layer.

本発明の請求項２に係る発明は、絶縁性のフイルム基材の片側上に銅層よりなる配線パターンと、該銅層よりなる配線パターン上の一部分面に形成した１段目のＳｎめっき層と、フイルム基材の全面及びＳｎめっき層の上面に、区画形成したソルダーレジストパターンと、該ソルダーレジストパターンから露出した区画のみに２段目のＳｎめっき層とを、その順に層形成した半導体実装用テープキャリアテープにおいて、ソルダーレジストパターンから露出した区画は、前記１段目のＳｎめっき層を除去した後に、２段目のＳｎめっき層を形成した半導体実装用テープキャリアテープであって、その層形成は、フイルム基材の片側上に銅層よりなる配線パターンと、該銅層よりなる配線パターン上の全面に形成した１段目のＳｎめっき層、又は２段目のＳｎめっき層と、フイルム基材及び１段目のＳｎめっき層の上全面に区画形成したソルダーレジストパターンと、該ソルダーレジストパターンから露出した面の上全面に区画形成した２段目のＳｎめっき層とを、その順に層形成したことを特徴とする半導体実装用テープキャリアテープである。   According to a second aspect of the present invention, there is provided a wiring pattern made of a copper layer on one side of an insulating film substrate, and a first-stage Sn plating layer formed on a partial surface of the wiring pattern made of the copper layer. And a solder mounting pattern in which a solder resist pattern formed on the entire surface of the film substrate and the upper surface of the Sn plating layer, and a second-stage Sn plating layer formed only in the sections exposed from the solder resist pattern, in that order. In the tape carrier tape for semiconductor use, the section exposed from the solder resist pattern is a tape mounting tape for semiconductor mounting in which a second-stage Sn plating layer is formed after removing the first-stage Sn plating layer, and the layer The formation includes a wiring pattern made of a copper layer on one side of the film substrate and a first-stage Sn plating layer formed on the entire surface of the wiring pattern made of the copper layer, A second-stage Sn plating layer, a solder resist pattern formed on the entire surface of the film substrate and the first-stage Sn plating layer, and a second-stage formed on the entire surface exposed from the solder resist pattern. In this case, the Sn plating layer is formed in that order, and is a tape carrier tape for semiconductor mounting.

本発明の半導体実装用テープキャリアテープ及びその製造方法では、無電解Ｓｎめっき処理において、予め無電解Ｓｎめっきにより形成したＳｎ―Ｃｕ配線のＳｎめっき層及びそのＳｎめっき層上に残存する隙間腐食の原因物質残査を併せて除去することににより、局部電池の形成を抑制することができ、Ｃｕ表面の溝状にエグレ、又はＳｎめっき層の異常析出等の無い半導体実装用テープキャリアテープを製造することができる。   In the tape carrier tape for semiconductor mounting and the manufacturing method thereof according to the present invention, in the electroless Sn plating process, the Sn plating layer of Sn—Cu wiring previously formed by electroless Sn plating and the crevice corrosion remaining on the Sn plating layer By removing the causative substance residue together, the formation of local batteries can be suppressed, and a tape carrier tape for semiconductor mounting that does not have an aggregating groove on the Cu surface or an abnormal precipitation of the Sn plating layer is manufactured. can do.

本発明の半導体実装用テープキャリアテープ及びその製造方法を一実施形態に基づいて以下説明する。   The tape carrier tape for semiconductor mounting and its manufacturing method of the present invention will be described below based on one embodiment.

図１は、本発明の半導体実装用テープキャリアテープの製造方法を説明する側断面図である。   FIG. 1 is a side sectional view for explaining a method for manufacturing a tape carrier tape for semiconductor mounting according to the present invention.

本発明の半導体実装用テープキャリアテープの製造方法を説明する。図１（ａ）は、絶縁性のフイルム基材１１に銅箔を貼り合わせる。フォトプロセス法を用いて、前記銅箔をエッチング処理して、配線パターン１２が形成された、半導体実装用テープキャリアテープ用フイルム基材を形成する。   The manufacturing method of the tape carrier tape for semiconductor mounting of this invention is demonstrated. In FIG. 1A, a copper foil is bonded to an insulating film substrate 11. The copper foil is etched using a photo process method to form a film substrate for a tape carrier tape for semiconductor mounting on which the wiring pattern 12 is formed.

図１（ｂ）は、Ｃｕ層よりなる配線パターン１２を形成したフイルム基材１１のソルダーレジスト樹脂を塗布する前に、Ｃｕ層よりなる配線パターン１２表面の全面に１段目のＳｎめっき層１６を形成する。次に、１段目のＳｎめっき層１６へ１３０℃／９０分の加熱処理のＳｎめっきアニールを行う。   FIG. 1B shows the first Sn plating layer 16 on the entire surface of the wiring pattern 12 made of the Cu layer before applying the solder resist resin of the film substrate 11 on which the wiring pattern 12 made of the Cu layer is formed. Form. Next, Sn plating annealing of heat treatment at 130 ° C./90 minutes is performed on the first-stage Sn plating layer 16.

図１（ｃ）は、絶縁性のフイルム基材表面１１の全面に、熱硬化性で、光感光性のソルダーレジスト樹脂を塗布し、現像処理し、ソルダーレジストパターン１３を形成する。次に、ソルダーレジストパターン１３へ１５０℃／８０分の高温加熱処理のＰＳＲポストキュアを行う。配線パターンでは、Ｓｎ−Ｃｕ層に拡散層８が形成される。   In FIG. 1C, a thermosetting and photosensitive solder resist resin is applied to the entire surface of the insulating film substrate surface 11 and developed to form a solder resist pattern 13. Next, the solder resist pattern 13 is subjected to a high-temperature heat treatment PSR post cure at 150 ° C./80 minutes. In the wiring pattern, the diffusion layer 8 is formed in the Sn—Cu layer.

図１（ｄ）は、前記ソルダーレジストパターン１３をマスクにして、所定の腐食用薬品を用いて、露出した１段目のＳｎめっき層区画４から１段目のＳｎめっき層１６のみを除去し、露出したＳｎめっき層４の表面に残存する隙間腐食の原因物質も併せて除去処理する。   FIG. 1 (d) uses the solder resist pattern 13 as a mask to remove only the first-stage Sn plating layer 16 from the exposed first-stage Sn plating layer section 4 using a predetermined corrosive chemical. In addition, the causative substance of crevice corrosion remaining on the exposed surface of the Sn plating layer 4 is also removed.

図１（ｅ）は、前記露出したＳｎめっき層区画４のみに、再度、２段目のＳｎめっき層１７を形成する。次に、２段目のＳｎめっき層１７へ１３０℃／９０分の加熱処理のＳｎめっきアニールを行うにより、露出した区画４の２段目のＳｎ／Ｃｕ層では拡散層のない純な２段目のＳｎめっき層１７が形成する。以上により、半導体実装用テープキャリアテープが製造できる。   In FIG. 1 (e), the second-stage Sn plating layer 17 is formed again only on the exposed Sn plating layer section 4. Next, by performing Sn plating annealing at 130 ° C./90 minutes for the second stage Sn plating layer 17, the second stage Sn / Cu layer in the exposed section 4 is a pure two stage without a diffusion layer. An Sn plating layer 17 of the eyes is formed. By the above, the tape carrier tape for semiconductor mounting can be manufactured.

本発明の製造方法によれば、１段目のＳｎめっき工程では、Ｃｕ層の配線パターン１２表全面にめっき層を形成することにより、パターン表面の全面にＳｎめっき反応が進行され、局部電池の形成を抑制することができる。１段目のＳｎめっき工程は、パターン表面からＣｕの異常溶出が発生しない製造方法である。   According to the manufacturing method of the present invention, in the first stage of the Sn plating step, by forming a plating layer on the entire surface of the wiring pattern 12 of the Cu layer, the Sn plating reaction proceeds on the entire surface of the pattern, and the local battery Formation can be suppressed. The first-stage Sn plating step is a manufacturing method in which abnormal elution of Cu does not occur from the pattern surface.

本発明の製造方法によれば、２段目のＳｎめっき工程では、Ｓｎ―Ｃｕ層の配線パターン１２面から、Ｓｎめっきのみを剥離することにより、Ｓｎ―Ｃｕパターン表面の隙間腐食の原因となるＰＳＲ用現像液等物質残渣及びＳｎが完全に剥離除去されることにより、Ｃｕの異常溶出が発生しない製造方法である。また、２段目のＳｎめっき工程では、ＰＳＲ層１３とＳｎ―Ｃｕ層１６，１２との密着強度が強くなり、界面剥離が生じず、Ｓｎめっき液がその界面の潜り込むことを抑制できる。２段目のＳｎめっき工程は、パターン表面からＣｕの異常溶出が発生しない製造方法である。   According to the manufacturing method of the present invention, only the Sn plating is peeled off from the surface of the wiring pattern 12 of the Sn—Cu layer in the second stage Sn plating step, which causes crevice corrosion on the surface of the Sn—Cu pattern. This is a manufacturing method in which abnormal elution of Cu does not occur when substance residue such as a developer for PSR and Sn are completely peeled and removed. Further, in the second-stage Sn plating step, the adhesion strength between the PSR layer 13 and the Sn—Cu layers 16 and 12 is increased, and interface peeling does not occur, and the Sn plating solution can be suppressed from entering the interface. The second stage Sn plating step is a manufacturing method in which abnormal elution of Cu does not occur from the pattern surface.

上述したように本発明の製造方法では、１段目及び２段目のＳｎめっき時にＣｕの異常溶出が発生しないため、Ｓｎめっきの析出が均一となり、Ｓｎめっきの厚さ、品質が均一化されている。   As described above, in the manufacturing method of the present invention, since abnormal elution of Cu does not occur during the first and second stages of Sn plating, the deposition of Sn plating becomes uniform, and the thickness and quality of the Sn plating are made uniform. ing.

図２は、本発明の半導体実装用テープキャリアテープの側断面図である。   FIG. 2 is a sectional side view of the tape mounting tape for semiconductor mounting according to the present invention.

図２のその層形成は、絶縁性のフイルム基材の片側上に銅層配線パターン１２と、該銅層よりなる配線パターン１２上に形成した１段目のＳｎめっき層１６と、フイルム基材１１及び１段目のＳｎめっき層１６の全面に区画形成したソルダーレジストパターン１３と、該ソルダーレジストパターンから露出した面に区画形成した２段目のＳｎめっき層１７とを、その順に層形成した半導体実装用テープキャリアテープである。図２に示すように銅層配線パターン１２と、その上に形成した１段目のＳｎめっき層１６とは、界面部の拡散層８が形成されている。   The layer formation in FIG. 2 includes a copper layer wiring pattern 12 on one side of an insulating film substrate, a first-stage Sn plating layer 16 formed on the wiring pattern 12 made of the copper layer, and a film substrate. A solder resist pattern 13 partitioned on the entire surface of the 11th and 1st stage Sn plating layers 16 and a second stage Sn plating layer 17 partitioned on the surface exposed from the solder resist pattern were formed in that order. It is a tape carrier tape for semiconductor mounting. As shown in FIG. 2, a diffusion layer 8 at the interface is formed between the copper layer wiring pattern 12 and the first-stage Sn plating layer 16 formed thereon.

次に、本発明の半導体実装用テープキャリアテープの製造方法の実施例を説明する。   Next, the Example of the manufacturing method of the tape carrier tape for semiconductor mounting of this invention is described.

所定の幅の長尺状で、７５μｍ厚のポリイミドフイルムに、所定の金型によりパンチ孔を打ち抜き、形成した。次に、前記ポリイミドフイルムに、接着剤（公知の接着剤で、巴川製（株）製造）を介して１８μｍ厚の銅箔とラミネートし、半導体実装用テープキャリアテープ用のフイルム基材を製造した。フォトリソグラフィー法を用いて、フォトマスク
を介して、銅箔からなる配線パターン（以下Ｃｕ配線層と記す）を形成した。次に、前記Ｃｕ配線層の全面に無電解Ｓｎめっき法により、０．１μｍ厚の１段目のＳｎめっき層を形成した。次に、前記フイルム基材の表面に、フォトソルダーレジスト（以下ＰＳＲと記す）を塗布した後プレキュア、露光後、アルカリ溶液による現像処理したあと、１５０℃で８０分間加熱しポストキュアし、接続端子部のみ露出したＰＳＲパターンを形成した。 A punch hole was punched and formed in a 75 μm thick polyimide film having a predetermined width and a predetermined mold. Next, the polyimide film was laminated with an 18 μm-thick copper foil through an adhesive (manufactured by Yodogawa Co., Ltd., using a known adhesive) to produce a film substrate for a tape carrier tape for semiconductor mounting. . A wiring pattern made of copper foil (hereinafter referred to as a Cu wiring layer) was formed through a photomask using a photolithography method. Next, a first stage Sn plating layer having a thickness of 0.1 μm was formed on the entire surface of the Cu wiring layer by electroless Sn plating. Next, a photo solder resist (hereinafter referred to as PSR) is applied to the surface of the film substrate, followed by pre-cure, exposure, development with an alkaline solution, heating at 150 ° C. for 80 minutes, post-cure, and connection terminals. A PSR pattern in which only a portion was exposed was formed.

次に、（株）荏原電産製のエバケム−テインエッチ／ＴＥ−０６０の薬品を２５℃に加温した後、前記半導体実装用テープキャリアテープを２０秒間浸漬し、前記半導体実装用テープキャリアテープのＰＳＲパターンから露出した、すなわち接続端子部の１段目のＳｎ―Ｃｕ配線層のＳｎめっき層のみ除去した。なお、当該薬品の取扱では、化学物質等安全データシート参照した。次に、蛍光Ｘ線分析装置を用いて、前記露出した接続端子部からＳｎめっき層が除去されたことを確認後、露出した接続端子部に２段目のＳｎめっき層を形成した後、１３０℃で９０分間の加熱処理をした。以上により、半導体実装用テープキャリアテープが製造された。   Next, the chemical of Evacem-Tein Etch / TE-060 manufactured by Ebara Densan Co., Ltd. was heated to 25 ° C., and then the semiconductor carrier tape carrier tape was immersed for 20 seconds, and the semiconductor carrier tape carrier tape Only the Sn plating layer exposed from the PSR pattern, that is, the first-stage Sn—Cu wiring layer of the connection terminal portion was removed. In handling the chemicals, we referred to the safety data sheet for chemical substances. Next, using a fluorescent X-ray analyzer, after confirming that the Sn plating layer was removed from the exposed connection terminal portion, a second stage Sn plating layer was formed on the exposed connection terminal portion, and then 130 Heat treatment was carried out at 90 ° C. for 90 minutes. The tape mounting tape for semiconductor mounting was manufactured by the above.

実施例１の半導体実装用テープキャリアテープの層形成では、フイルム基材の片側上に銅層の配線パターンと、該銅層配線パターン上に１段目のＳｎめっき層、又は２段目のＳｎめっき層と、フイルム基材上にソルダーレジストパターンと、該ソルダーレジストパターンから露出した面に接続端子部、すなわち前記２段目のＳｎめっき層が形成された層形成である。   In the layer formation of the tape carrier tape for semiconductor mounting in Example 1, the wiring pattern of the copper layer on one side of the film substrate and the first-level Sn plating layer or the second-level Sn on the copper layer wiring pattern This is a layer formation in which a plating layer, a solder resist pattern on a film substrate, and a connection terminal portion, that is, the second-stage Sn plating layer is formed on a surface exposed from the solder resist pattern.

実施例１では、試料から１０シートを抜き取り、破壊検査を実施した。その結果は、Ｃｕ表面の溝状にエグレ、又はＳｎめっき層の異常析出等の不良カ所は検出されずに、高品質の半導体実装用テープキャリアテープと、半導体実装用テープキャリアテープの製造方法が確認された。   In Example 1, 10 sheets were extracted from the sample and subjected to a destructive inspection. As a result, a high quality semiconductor mounting tape carrier tape and a manufacturing method of the semiconductor mounting tape carrier tape can be obtained without detecting defects such as an egre in a groove shape on the Cu surface or abnormal deposition of the Sn plating layer. confirmed.

本発明の半導体実装用テープキャリアテープの製造方法を説明する工程図であり、部分拡大の側断面図である。It is process drawing explaining the manufacturing method of the tape carrier tape for semiconductor mounting of this invention, and is a sectional side view of a partial expansion. 本発明の半導体実装用テープキャリアテープの部分拡大の側断面図である。It is side sectional drawing of the partial expansion of the tape carrier tape for semiconductor mounting of this invention. 従来の半導体実装用テープキャリアテープの部分拡大の側断面図で、（ａ）通常品であり、（ｂ）は、２段めっき品である。It is a sectional side view of the expansion of the conventional tape carrier tape for semiconductor mounting, (a) is a normal product, (b) is a two-stage plating product.

符号の説明Explanation of symbols

１…ポリイミドフイルム
２…Ｃｕ配線層
３…ＰＳＲ層
４…ＰＳＲ層開口部
５…Ｓｎめっき層
６…１段目のＳｎめっき層
７…２段目のＳｎめっき層
８…拡散層
１１…絶縁性のフイルム基材
１２…銅層配線パターン
１３…ソルダーレジストパターン（ＰＳＲパターン）
１６…１段目のＳｎめっきパターン
１７…２段目のＳｎめっきパターン DESCRIPTION OF SYMBOLS 1 ... Polyimide film 2 ... Cu wiring layer 3 ... PSR layer 4 ... PSR layer opening part 5 ... Sn plating layer 6 ... First stage Sn plating layer 7 ... Second stage Sn plating layer 8 ... Diffusion layer 11 ... Insulating property Film substrate 12 ... copper layer wiring pattern 13 ... solder resist pattern (PSR pattern)
16 ... First-stage Sn plating pattern 17 ... Second-stage Sn plating pattern

Claims (2)

絶縁性のフイルム基材に銅箔を貼り合わせ、該銅箔をエッチング処理により、配線パターンが形成された、半導体装置を実装するための半導体実装用テープキャリアテープの製造方法において、
Ｃｕ層よりなる配線パターンを形成したフイルム基材にソルダーレジスト樹脂を塗布する前に、Ｃｕ層よりなる配線パターン表面の全面にＳｎめっき層を形成した後、
フイルム基材表面の全面に、熱硬化性で、光感光性のソルダーレジスト樹脂を塗布し、現像処理し、ソルダーレジストパターンを形成後、
前記ソルダーレジストパターンをマスクにして、所定の腐食用薬品を用いて、露出したＳｎめっき層区画のみを除去し、併せて、露出したＳｎめっき層の表面に残存する隙間腐食の原因物質も除去処理した後、
前記露出した区画の上全面に、再度、Ｓｎめっき層を区画形成することを特徴とする半導体実装用テープキャリアテープの製造方法。 In the method for manufacturing a semiconductor carrier tape carrier tape for mounting a semiconductor device in which a wiring pattern is formed by laminating a copper foil on an insulating film substrate and etching the copper foil.
Before the solder resist resin is applied to the film base material on which the wiring pattern made of the Cu layer is formed, the Sn plating layer is formed on the entire surface of the wiring pattern surface made of the Cu layer.
After applying a thermosetting and photosensitive solder resist resin to the entire surface of the film substrate surface, developing it, and forming a solder resist pattern,
Using the solder resist pattern as a mask, only the exposed Sn plating layer section is removed using a predetermined corrosive chemical, and at the same time, the causative substances remaining on the surface of the exposed Sn plating layer are also removed. After
A method of manufacturing a tape carrier tape for semiconductor mounting, wherein an Sn plating layer is formed again on the entire upper surface of the exposed section. 絶縁性のフイルム基材の片側上に銅層よりなる配線パターンと、該銅層よりなる配線パターン上の一部分面に形成した１段目のＳｎめっき層と、フイルム基材の全面及びＳｎめっき層の上面に、区画形成したソルダーレジストパターンと、該ソルダーレジストパターンから露出した区画のみに２段目のＳｎめっき層とを、その順に層形成した半導体実装用テープキャリアテープにおいて、
ソルダーレジストパターンから露出した区画は、前記１段目のＳｎめっき層を除去した後に、２段目のＳｎめっき層を形成した半導体実装用テープキャリアテープであって、
その層形成は、
フイルム基材の片側上に銅層よりなる配線パターンと、
該銅層よりなる配線パターン上の全面に形成した１段目のＳｎめっき層、又は２段目のＳｎめっき層と、
フイルム基材及び１段目のＳｎめっき層の上全面に区画形成したソルダーレジストパターンと、
該ソルダーレジストパターンから露出した面の上全面に区画形成した２段目のＳｎめっき層とを、その順に層形成したことを特徴とする半導体実装用テープキャリアテープ。 A wiring pattern made of a copper layer on one side of an insulating film substrate, a first-stage Sn plating layer formed on a partial surface on the wiring pattern made of the copper layer, the entire surface of the film substrate and the Sn plating layer In the tape carrier tape for semiconductor mounting in which the solder resist pattern formed on the upper surface of the substrate and the second-stage Sn plating layer only on the section exposed from the solder resist pattern are formed in that order.
The section exposed from the solder resist pattern is a tape mounting tape for semiconductor mounting in which a second-stage Sn plating layer is formed after removing the first-stage Sn plating layer,
The layer formation is
A wiring pattern consisting of a copper layer on one side of the film substrate;
A first-stage Sn plating layer formed on the entire surface of the wiring pattern made of the copper layer, or a second-stage Sn plating layer;
A solder resist pattern formed on the entire upper surface of the film base and the first-stage Sn plating layer;
A tape carrier tape for semiconductor mounting, wherein a second-stage Sn plating layer partitioned on the entire surface exposed from the solder resist pattern is formed in that order.
JP2005158957A 2005-05-31 2005-05-31 Manufacturing method of tape carrier tape for semiconductor mounting Expired - Fee Related JP4618006B2 (en)

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CN104990962A (en) * 2015-06-08 2015-10-21 广东电网有限责任公司电力科学研究院 Crevice-corrosion-avoiding sample packaging method and structure in stainless steel pitting study
CN105050311A (en) * 2014-04-30 2015-11-11 发那科株式会社 Printed circuit board and method of manufacturing the same

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JP2000332064A (en) * 1999-05-24 2000-11-30 Shindo Denshi Kogyo Kk Manufacture of fine wiring tape carrier
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Publication number Priority date Publication date Assignee Title
CN105050311A (en) * 2014-04-30 2015-11-11 发那科株式会社 Printed circuit board and method of manufacturing the same
CN105050311B (en) * 2014-04-30 2019-03-08 发那科株式会社 Printed circuit board and its manufacturing method
CN104990962A (en) * 2015-06-08 2015-10-21 广东电网有限责任公司电力科学研究院 Crevice-corrosion-avoiding sample packaging method and structure in stainless steel pitting study
CN104990962B (en) * 2015-06-08 2018-03-02 广东电网有限责任公司电力科学研究院 The specimen enclosure method and structure of crevice corrosion are avoided in stainless steel spot corrosion research

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