JP2006286820A - Photovoltaic device - Google Patents
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- JP2006286820A JP2006286820A JP2005103097A JP2005103097A JP2006286820A JP 2006286820 A JP2006286820 A JP 2006286820A JP 2005103097 A JP2005103097 A JP 2005103097A JP 2005103097 A JP2005103097 A JP 2005103097A JP 2006286820 A JP2006286820 A JP 2006286820A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 32
- 230000002093 peripheral effect Effects 0.000 claims description 20
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 26
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Classifications
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
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Abstract
Description
本発明は、主面に光閉じ込めのためのテクスチャー構造の凹凸が形成された半導体基板を用いた光起電力装置に関するものである。 The present invention relates to a photovoltaic device using a semiconductor substrate in which irregularities of a texture structure for light confinement are formed on a main surface.
単結晶シリコン基板などの結晶系半導体基板を用いた光起電力装置は、光電変換効率が高く、既に太陽光発電システムとして広く一般に実用化されている。 A photovoltaic device using a crystalline semiconductor substrate such as a single crystal silicon substrate has high photoelectric conversion efficiency and has already been widely put into practical use as a photovoltaic power generation system.
これらの結晶系半導体基板を用いた光起電力装置においては、結晶系半導体基板の光入射側主面に、光閉じ込め構造により反射損失を低減するため、テクスチャー構造の凹凸が形成されている。表面にテクスチャー構造の凹凸を形成する方法としては、アルカリ性溶液を用いて結晶系半導体基板の表面をエッチングする方法が知られている（特許文献１など）。 In the photovoltaic device using these crystalline semiconductor substrates, texture structure irregularities are formed on the light incident side main surface of the crystalline semiconductor substrate in order to reduce reflection loss by the light confinement structure. As a method for forming irregularities of a texture structure on the surface, a method of etching the surface of a crystalline semiconductor substrate using an alkaline solution is known (Patent Document 1, etc.).
このような結晶系半導体基板においては、光入射側主面のみにテクスチャー構造の凹凸を形成しており、高い光電変換効率を有する光起電力装置では、基板の主面と反対側の裏面は、従来から平坦な面となるように形成されている（特許文献２など）。
しかしながら、本発明者は、半導体基板の周辺からの入射光を考慮した場合、基板の側面及び裏面周辺部にもテクスチャー構造の凹凸を形成することにより、基板周辺からの光を効率的に吸収することができ、光電変換効率が向上することを見出した。 However, when considering the incident light from the periphery of the semiconductor substrate, the inventor efficiently absorbs the light from the periphery of the substrate by forming irregularities of the texture structure on the side surface and the back surface periphery of the substrate. It has been found that photoelectric conversion efficiency is improved.
本発明の目的は、半導体基板を用いた光起電力装置において、光電変換効率に優れた光起電力装置を提供することにある。 An object of the present invention is to provide a photovoltaic device having excellent photoelectric conversion efficiency in a photovoltaic device using a semiconductor substrate.
本発明は、主面にテクスチャー構造の凹凸が形成された半導体基板を用いた光起電力セルを備える光起電力装置であり、半導体基板の側面及び裏面周辺部にもテクスチャー構造の凹凸が形成されていることを特徴としている。 The present invention is a photovoltaic device provided with a photovoltaic cell using a semiconductor substrate having a textured surface asperity formed on the main surface, and the textured surface asperity is also formed on the side surface and back surface peripheral portion of the semiconductor substrate. It is characterized by having.
本発明に従い、半導体基板の側面及び裏面周辺部にもテクスチャー構造の凹凸を形成することにより、基板の側面及び裏面周辺部において光を効果的に吸収することができ、光電変換効率を高め、高い出力が得られる。 According to the present invention, by forming irregularities of the texture structure also on the side surface and back surface periphery of the semiconductor substrate, light can be effectively absorbed in the side surface and back surface periphery of the substrate, increasing the photoelectric conversion efficiency, and high Output is obtained.
本発明において、凹凸が形成される裏面周辺部は、基板周辺の側面端部から内側に２ｍｍ以下までの領域であることが好ましい。凹凸を形成する裏面周辺部が、基板周辺の側面端部から内側に２ｍｍ以下までの領域を超えると、短絡電流が小さくなり、光電変換効率の向上が得られない場合がある。 In this invention, it is preferable that the back surface peripheral part in which an unevenness | corrugation is formed is an area | region from the side edge part of a board | substrate periphery to 2 mm or less inside. If the back surface peripheral part forming the irregularities exceeds the region of 2 mm or less inward from the side edge part around the substrate, the short circuit current may be reduced, and the photoelectric conversion efficiency may not be improved.
本発明の光起電力装置は、上記半導体基板を用いた光起電力セルが複数並べて設けられており、これらが電気的に直列に接続されている太陽電池モジュールであることが好ましい。このような太陽電池モジュールにおいては、光起電力セルが所定間隔をあけて配置されている。本発明によれば、光起電力セル間の隙間を通り入射した光が、基板の側面及び裏面周辺部において吸収されるので、光電変換効率を高めることができる。従来の基板の側面及び裏面周辺部がフラットである光起電力装置においては、セル間の隙間から入射し散乱した光が十分に吸収されず反射されていた。本発明では、このような散乱光を効果的に吸収することができるため、高い光電変換効率が得られる。 The photovoltaic device of the present invention is preferably a solar cell module in which a plurality of photovoltaic cells using the semiconductor substrate are provided side by side and these are electrically connected in series. In such a solar cell module, photovoltaic cells are arranged at a predetermined interval. According to the present invention, the light incident through the gap between the photovoltaic cells is absorbed at the side surface and the back surface peripheral portion of the substrate, so that the photoelectric conversion efficiency can be increased. In the conventional photovoltaic device in which the side surface and the back surface peripheral portion of the substrate are flat, the light incident and scattered from the gaps between the cells is not sufficiently absorbed and reflected. In this invention, since such scattered light can be absorbed effectively, high photoelectric conversion efficiency is obtained.
本発明において、半導体基板は、結晶系半導体基板であることが好ましく、単結晶半導体基板であってもよいし、多結晶半導体基板であってもよい。また、結晶系半導体基板は、例えば、結晶系シリコン基板であり、最も一般的には、単結晶シリコン基板である。 In the present invention, the semiconductor substrate is preferably a crystalline semiconductor substrate, and may be a single crystal semiconductor substrate or a polycrystalline semiconductor substrate. The crystalline semiconductor substrate is, for example, a crystalline silicon substrate, and most commonly a single crystal silicon substrate.
本発明における光起電力セルとしては、単結晶系光起電力セル、多結晶系光起電力セル、単結晶と非晶質のハイブリッド型の光起電力セルなどが挙げられる。ハイブリッド型光起電力セルとしては、例えば、ｎ型結晶系シリコン基板の主面上にｉ型非晶質シリコン層を形成し、この上にｐ型非晶質シリコン層を形成したものが挙げられる。ｉ型非晶質シリコン層の厚みは、例えば、２〜１０ｎｍであり、ｐ型非晶質シリコン層の厚みは、例えば、２〜１０ｎｍである。 Examples of the photovoltaic cell in the present invention include a single crystal photovoltaic cell, a polycrystalline photovoltaic cell, and a single crystal and amorphous hybrid photovoltaic cell. An example of a hybrid photovoltaic cell is one in which an i-type amorphous silicon layer is formed on the main surface of an n-type crystalline silicon substrate and a p-type amorphous silicon layer is formed thereon. . The i-type amorphous silicon layer has a thickness of 2 to 10 nm, for example, and the p-type amorphous silicon layer has a thickness of 2 to 10 nm, for example.
また、半導体基板の裏面には、裏面電極との間にＢＳＦ（back surface field）構造が形成されていてもよい。例えば、半導体基板がｎ型結晶系半導体基板である場合には、ｉ型非晶質シリコン層を介してｎ型非晶質シリコン層を設けてもよい。 Further, a back surface field (BSF) structure may be formed between the back surface of the semiconductor substrate and the back electrode. For example, when the semiconductor substrate is an n-type crystalline semiconductor substrate, an n-type amorphous silicon layer may be provided via an i-type amorphous silicon layer.
本発明における半導体基板は、例えば、結晶系半導体基板の裏面において、裏面周辺部以外の領域をレジスト膜やマスク等で覆い、この状態で基板をウェットエッチングすることにより得ることができる。従って、基板の主面、側面及び裏面周辺部に同時にテクスチャー構造の凹凸を形成した基板を用いることができる。 The semiconductor substrate in the present invention can be obtained, for example, by covering a region other than the periphery of the back surface with a resist film, a mask or the like on the back surface of the crystalline semiconductor substrate, and wet etching the substrate in this state. Therefore, the board | substrate which formed the unevenness | corrugation of the texture structure simultaneously in the main surface, side surface, and back surface peripheral part of a board | substrate can be used.
本発明における光起電力セルとしては、上記のような光起電力セルが挙げられるが、例えば、ｎ型もしくはｐ型の結晶系シリコン基板の上に直接ｐ型もしくはｎ型の非晶質シリコン層を形成した光起電力セルであってもよい。また、ｎ型もしくはｐ型の結晶系シリコン基板の表面にｐ型もしくはｎ型のドーパントをドープすることによりｐｎ接合を形成した光起電力セルであってもよい。 Examples of the photovoltaic cell in the present invention include the photovoltaic cells as described above. For example, a p-type or n-type amorphous silicon layer directly on an n-type or p-type crystalline silicon substrate. It may be a photovoltaic cell formed. Alternatively, a photovoltaic cell in which a pn junction is formed by doping a p-type or n-type dopant on the surface of an n-type or p-type crystalline silicon substrate may be used.
本発明によれば、基板の側面及び裏面周辺部における散乱光を効果的に吸収することができ、高い光電変換効率を得ることができる。 According to the present invention, it is possible to effectively absorb scattered light on the side surface and back surface peripheral portion of the substrate, and to obtain high photoelectric conversion efficiency.
以下、本発明を実施例により具体的に説明するが、本発明は以下の実施例に限定されるものではない。 EXAMPLES Hereinafter, although an Example demonstrates this invention concretely, this invention is not limited to a following example.
図１は、本発明に従う一実施例の光起電力装置を示す模式的断面図である。本実施例の光起電力装置は太陽電池モジュールであり、複数の光起電力セル１０が並べて設けられている。これらの光起電力セル１０は、図示省略されているが、互いに電気的に直列に接続されている。 FIG. 1 is a schematic cross-sectional view showing a photovoltaic device of one embodiment according to the present invention. The photovoltaic device of the present embodiment is a solar cell module, and a plurality of photovoltaic cells 10 are provided side by side. Although not shown, these photovoltaic cells 10 are electrically connected to each other in series.
光起電力セル１０は、単結晶シリコン基板１を用いて作製されており、単結晶シリコン基板１の光入射側の主面１ａにはテクスチャー構造の凹凸が形成されている。また、側面１ｂにも同様にテクスチャー構造の凹凸が形成されている。また、単結晶基板１の裏面１ｄの周辺部１ｃにも、テクスチャー構造の凹凸が形成されている。 The photovoltaic cell 10 is fabricated using a single crystal silicon substrate 1, and textured irregularities are formed on the main surface 1 a on the light incident side of the single crystal silicon substrate 1. Similarly, the side surface 1b is provided with textured irregularities. In addition, unevenness having a texture structure is also formed on the peripheral portion 1 c of the back surface 1 d of the single crystal substrate 1.
図１には、光起電力セル１０における単結晶シリコン基板１のみが図示されているが、光起電力セル１０は、図２に示すような構造を有している。すなわち、単結晶シリコン基板１はｎ型単結晶シリコン基板であり、その主面１ａの上には、ｉ型非晶質シリコン層２が形成されており、ｉ型非晶質シリコン層２の上には、ｐ型非晶質シリコン層３が形成されている。 Although only the single crystal silicon substrate 1 in the photovoltaic cell 10 is shown in FIG. 1, the photovoltaic cell 10 has a structure as shown in FIG. That is, the single crystal silicon substrate 1 is an n-type single crystal silicon substrate, and an i-type amorphous silicon layer 2 is formed on the main surface 1a. A p-type amorphous silicon layer 3 is formed.
ｐ型非晶質シリコン層３の上には、ＩＴＯ（インジュウム錫酸化物）などからなる透明電極４が形成されている。透明電極４の上には、集電極８が形成されている。 A transparent electrode 4 made of ITO (Indium Tin Oxide) or the like is formed on the p-type amorphous silicon layer 3. A collecting electrode 8 is formed on the transparent electrode 4.
なお、ｉ型非晶質シリコン層２、ｐ型非晶質シリコン層３、及び透明電極４は、単結晶シリコン基板１の側面１ｂ及び側面周辺部１ｃには形成されていない。側面１ｂの部分は、単結晶シリコン基板の面がそのまま露出した状態である。 The i-type amorphous silicon layer 2, the p-type amorphous silicon layer 3, and the transparent electrode 4 are not formed on the side surface 1b and the side surface peripheral portion 1c of the single crystal silicon substrate 1. The portion of the side surface 1b is in a state where the surface of the single crystal silicon substrate is exposed as it is.
また、単結晶シリコン基板１の裏面１ｄの上には、図２に示すように、ｉ型非晶質シリコン層５を介してｎ型非晶質シリコン層６が形成されている。従って、ＢＳＦ構造が形成されている。ｎ型非晶質シリコン層６の上には透明電極７が形成されており、透明電極７の上には集電極９が形成されている。 Further, as shown in FIG. 2, an n-type amorphous silicon layer 6 is formed on the back surface 1 d of the single crystal silicon substrate 1 via an i-type amorphous silicon layer 5. Therefore, a BSF structure is formed. A transparent electrode 7 is formed on the n-type amorphous silicon layer 6, and a collector electrode 9 is formed on the transparent electrode 7.
図１に示すように、電気的に直列に接続された光起電力セル１０は、ＥＶＡ樹脂（エチレン酢酸ビニル共重合体）などからなる充填材１３に埋め込まれた状態で、裏面保護フィルム１２及び表面のガラス板１１に挟まれた状態で、太陽電池モジュールが構成されている。図１に示すように、主面１ａ側から光１４が入射し、単結晶シリコン基板１内で光が吸収され光電変換されて発電される。図１に示すように、光起電力セル１０間には隙間が設けられており、この隙間に光１４が入射する。隙間から入射した光１４は、裏面保護フィルム１２の表面で反射し散乱する。本発明においては、単結晶シリコン基板１の側面１ｂ及び裏面周辺部１ｃに凹凸が形成されているので、このようにして裏面保護フィルム１２で反射し散乱した光を効果的に吸収することができる。このため、従来から光電変換に利用することができなかった光を利用することができ、高い光電変換効率を得ることができる。裏面保護フィルム１２として、光反射率が高いフィルム、例えば白色などのフィルムを用いることにより、裏面保護フィルム１２の表面で反射する光が増えるため、より高い光電変換効率を得ることができる。 As shown in FIG. 1, the photovoltaic cells 10 electrically connected in series are embedded in a filler 13 made of EVA resin (ethylene vinyl acetate copolymer) or the like, and the back surface protective film 12 and The solar cell module is configured with being sandwiched between the glass plates 11 on the surface. As shown in FIG. 1, light 14 enters from the main surface 1a side, and the light is absorbed and photoelectrically converted in the single crystal silicon substrate 1 to generate electric power. As shown in FIG. 1, a gap is provided between the photovoltaic cells 10, and light 14 enters the gap. The light 14 incident from the gap is reflected and scattered by the surface of the back surface protective film 12. In this invention, since the unevenness | corrugation is formed in the side surface 1b and the back surface peripheral part 1c of the single crystal silicon substrate 1, the light reflected and scattered by the back surface protective film 12 in this way can be absorbed effectively. . For this reason, the light which could not be utilized for photoelectric conversion conventionally can be utilized, and high photoelectric conversion efficiency can be obtained. By using a film having a high light reflectance, such as a white film, as the back surface protective film 12, the amount of light reflected on the surface of the back surface protective film 12 increases, so that higher photoelectric conversion efficiency can be obtained.
図５は、従来の比較例の光起電力装置を示す模式的断面図である。図５に示すように、従来の光起電力装置においては、単結晶シリコン基板１の側面１ｃ及び裏面周辺部１ｄに凹凸が形成されていない。従って、光起電力セル１０間の隙間に入射した光１４は、裏面保護フィルム１２で反射して散乱するが、基板１の側面及び裏面周辺部１ｃがフラットな面であるので、この散乱光を反射してしまい、効果的に吸収することができない。従って、従来は、このような散乱光を利用することができず、本発明のように高い光電変換効率を得ることができなかった。 FIG. 5 is a schematic cross-sectional view showing a photovoltaic device of a conventional comparative example. As shown in FIG. 5, in the conventional photovoltaic device, the unevenness | corrugation is not formed in the side surface 1c of the single crystal silicon substrate 1, and the back surface peripheral part 1d. Therefore, although the light 14 incident on the gap between the photovoltaic cells 10 is reflected and scattered by the back surface protective film 12, the side surface of the substrate 1 and the back surface peripheral portion 1c are flat surfaces. It is reflected and cannot be absorbed effectively. Therefore, conventionally, such scattered light cannot be used, and high photoelectric conversion efficiency cannot be obtained as in the present invention.
図１に示す光起電力装置を以下のようにして製造し、光電変換特性を評価した。 The photovoltaic device shown in FIG. 1 was manufactured as follows, and the photoelectric conversion characteristics were evaluated.
主面の面方位が（１００）であるｎ型単結晶シリコンウェハを、７０℃の５重量％ＮａＯＨ水溶液に５分間浸漬し、その表面をエッチングした。 An n-type single crystal silicon wafer having a (100) main surface orientation was immersed in a 5 wt% NaOH aqueous solution at 70 ° C. for 5 minutes, and the surface was etched.
なお、エッチングの際には、図３に示すように、単結晶シリコンウェハ１の裏面１ｄの部分にレジスト膜２０を形成した。図３に示すように、ウェハ１の側面１ｂの端部から内側に幅Ｗまでの領域にはレジスト膜２０が設けられないように形成した。ここでは、幅Ｗを１ｍｍとした。従って、基板の側面１ｂの端部から内側に１ｍｍまでの領域１ｃにレジスト膜が設けられないようにレジスト膜２０を形成した。レジスト膜２０としては、アルカリエッチング耐性の樹脂膜を用いることができる。また、酸化シリコン膜等からなるマスクを用いてもよい。 In the etching, a resist film 20 was formed on the back surface 1d of the single crystal silicon wafer 1 as shown in FIG. As shown in FIG. 3, the resist film 20 was not formed in the region from the end of the side surface 1 b of the wafer 1 to the width W inside. Here, the width W was 1 mm. Therefore, the resist film 20 was formed so that the resist film was not provided in the region 1c from the end of the side surface 1b of the substrate to 1 mm inside. As the resist film 20, a resin film resistant to alkali etching can be used. Further, a mask made of a silicon oxide film or the like may be used.
以上のようにしてレジスト膜を形成したシリコンウェハを、３重量％のカプリル酸を含有した２重量％ＮａＯＨからなる水溶液に浸漬し、レジスト膜が設けられていないシリコンウェハの表面に（１１１）面からなるテクスチャー構造の凹凸を形成した。 The silicon wafer on which the resist film is formed as described above is immersed in an aqueous solution of 2 wt% NaOH containing 3 wt% caprylic acid, and the (111) plane is formed on the surface of the silicon wafer on which no resist film is provided. The textured irregularities made of
次に、硫酸過水（硫酸：純水＝１：１、１２０℃）や、酸素プラズマによるアッシングにより、レジスト膜２０を除去した。レジスト膜が酸化シリコン膜である場合には、２重量％ＨＦ水溶液を用いて除去することができる。 Next, the resist film 20 was removed by ashing with sulfuric acid / hydrogen peroxide (sulfuric acid: pure water = 1: 1, 120 ° C.) or oxygen plasma. When the resist film is a silicon oxide film, it can be removed using a 2 wt% HF aqueous solution.
水洗した後、２重量％ＨＦ水溶液を用いて、シリコンウェハの表面の酸化膜を除去し、次に超純水で水洗した。 After washing with water, the oxide film on the surface of the silicon wafer was removed using a 2 wt% HF aqueous solution, and then washed with ultrapure water.
以上のようにして主面、側面及び裏面周辺部にテクスチャー構造の凹凸を形成した単結晶シリコンウェハの上に、プラズマＣＶＤ装置を用いて非晶質シリコン薄膜を形成した。まず、シリコンウェハの裏面（フラット面）に水素プラズマ処理（圧力８０Ｐａ、ＲＦ出力２０Ｗ）を行い、続けてｉ型非晶質シリコン薄膜（厚み５ｎｍ）を圧力８０Ｐａ、ＲＦ出力３０Ｗで形成した。次に、ｎ型非晶質シリコン薄膜（厚み３０ｎｍ）を圧力８０Ｐａ、ＲＦ出力３０Ｗで連続して形成した。 As described above, an amorphous silicon thin film was formed on the single crystal silicon wafer having the textured surface irregularities formed on the main surface, the side surface, and the periphery of the back surface using a plasma CVD apparatus. First, a hydrogen plasma treatment (pressure 80 Pa, RF output 20 W) was performed on the back surface (flat surface) of the silicon wafer, and then an i-type amorphous silicon thin film (thickness 5 nm) was formed at a pressure 80 Pa and an RF output 30 W. Next, an n-type amorphous silicon thin film (thickness 30 nm) was continuously formed at a pressure of 80 Pa and an RF output of 30 W.
次に、シリコンウェハの主面に対し、水素プラズマ処理（圧力８０Ｐａ、ＲＦ出力２０Ｗ）を行い、この上にｉ型非晶質シリコン薄膜（厚み５ｎｍ）を圧力８０Ｐａ、ＲＦ出力３０Ｗで形成した。さらに、この上にｐ型非晶質シリコン薄膜（厚み５ｎｍ）を圧力８０Ｐａ、ＲＦ出力３０Ｗで連続して形成した。 Next, the main surface of the silicon wafer was subjected to hydrogen plasma treatment (pressure 80 Pa, RF output 20 W), and an i-type amorphous silicon thin film (thickness 5 nm) was formed thereon with a pressure 80 Pa and RF output 30 W. Further, a p-type amorphous silicon thin film (thickness 5 nm) was continuously formed thereon at a pressure of 80 Pa and an RF output of 30 W.
なお、裏面に形成したｎ型非晶質シリコン薄膜及びｎ型非晶質シリコン薄膜は、凹凸が形成されている裏面周辺部の領域にも形成した。 Note that the n-type amorphous silicon thin film and the n-type amorphous silicon thin film formed on the back surface were also formed in the region around the back surface where the irregularities were formed.
以上のようにして形成した主面上のｐ型非晶質シリコン薄膜及び裏面上のｎ型非晶質シリコン薄膜の上に、スパッタリング法により透明電極としてＩＴＯをそれぞれ１００ｎｍの厚みとなるように形成した。次に、透明電極の上に、銀ペーストをスクリーン印刷し、櫛形電極を形成し、集電極とした。 On the p-type amorphous silicon thin film on the main surface and the n-type amorphous silicon thin film on the back surface formed as described above, ITO is formed to have a thickness of 100 nm as a transparent electrode by sputtering. did. Next, a silver paste was screen-printed on the transparent electrode to form a comb-shaped electrode, thereby forming a collector electrode.
以上のようにして作製した光起電力セルを複数個接続した後、充填材としてのＥＶＡ樹脂、保護基板としてのガラス板、裏面保護フィルムとしてのＰＥＴ（ポリエチレンテレフタレート）フィルムをラミネートし、太陽電池モジュールとした。 After connecting a plurality of photovoltaic cells produced as described above, an EVA resin as a filler, a glass plate as a protective substrate, and a PET (polyethylene terephthalate) film as a back protective film are laminated, and a solar cell module It was.
比較として、図４に示すように、単結晶シリコンウェハ１の側面１ｃ及び裏面１ｄの全面にレジスト膜２０を形成してエッチングする以外は、上記実施例と同様にして太陽電池モジュールを作製し、比較例の太陽電池モジュールとした。 For comparison, as shown in FIG. 4, a solar cell module was produced in the same manner as in the above example except that the resist film 20 was formed and etched on the entire side surface 1c and back surface 1d of the single crystal silicon wafer 1. It was set as the solar cell module of the comparative example.
上記の実施例及び比較例の太陽電池モジュールについて、ソーラーシミュレータにより出力を測定したところ、本実施例の太陽電池モジュールは、比較例の太陽電池モジュールに比べ、短絡電流が１．８％増加した。この結果、本実施例の太陽電池モジュールは、比較例の太陽電池モジュールに比べ、出力Ｐｍａｘが１．８％向上した。 About the solar cell module of said Example and comparative example, when the output was measured with the solar simulator, the short circuit current of the solar cell module of a present Example increased 1.8% compared with the solar cell module of the comparative example. As a result, the output Pmax of the solar cell module of this example was improved by 1.8% compared to the solar cell module of the comparative example.
＜凹凸を形成する裏面周辺部の領域についての検討＞
図３に示す裏面周辺部１ｃの領域の幅Ｗを、表１に示すように変化させて上記実施例と同様にして太陽電池モジュールを作製し、光電変換特性を評価した。なお、上記と同様に、Ｗ＝０の比較例の太陽電池モジュールを基準にして評価した。すなわち、比較例の太陽電池モジュールの短絡電流（Ｉｓｃ）、開放電圧（Ｖｏｃ）、フィルファクタ（Ｆ．Ｆ．）、出力（Ｐｍａｘ）を１として、それぞれを評価した。評価結果を表１に示す。
<Examination of the area around the back surface where irregularities are formed>
A solar cell module was produced in the same manner as in the above example by changing the width W of the region of the back surface peripheral portion 1c shown in FIG. 3 as shown in Table 1, and the photoelectric conversion characteristics were evaluated. In addition, it evaluated on the basis of the solar cell module of the comparative example of W = 0 similarly to the above. That is, the short-circuit current (Isc), the open-circuit voltage (Voc), the fill factor (FF), and the output (Pmax) of the solar cell module of the comparative example were evaluated as 1, respectively. The evaluation results are shown in Table 1.
また、裏面周辺部の幅Ｗと短絡電流の相対値との関係を図６に示す。表１及び図６に示す結果から明らかなように、裏面周辺部の幅Ｗが２ｍｍ以下であれば、短絡電流が比較例のものより高くなり、高い出力が得られている。従って、基板の裏面周辺部の幅Ｗとしては２ｍｍ以下が好ましいことがわかる。 FIG. 6 shows the relationship between the width W of the peripheral portion of the back surface and the relative value of the short circuit current. As is apparent from the results shown in Table 1 and FIG. 6, when the width W of the peripheral portion on the back surface is 2 mm or less, the short circuit current is higher than that of the comparative example, and a high output is obtained. Therefore, it can be seen that the width W of the peripheral portion of the back surface of the substrate is preferably 2 mm or less.
本発明は上記実施例のセルに限定されるものではなく、半導体基板を用いた光起電力セルであれば適用することができるものである。 The present invention is not limited to the cell of the above embodiment, but can be applied to any photovoltaic cell using a semiconductor substrate.
１…単結晶シリコン基板
１ａ…単結晶シリコン基板の主面
１ｂ…単結晶シリコン基板の側面
１ｃ…単結晶シリコン基板の裏面周辺部
１ｄ…単結晶シリコン基板の裏面
２…ｉ型非晶質シリコン層
３…ｐ型非晶質シリコン層
４…透明電極
５…ｉ型非晶質シリコン層
６…ｎ型非晶質シリコン層
７…透明電極
８，９…集電極
１０…光起電力セル
１１…ガラス板
１２…裏面保護フィルム
１３…充填材
１４…入射光
２０…レジスト膜
DESCRIPTION OF SYMBOLS 1 ... Single crystal silicon substrate 1a ... Main surface of single crystal silicon substrate 1b ... Side surface of single crystal silicon substrate 1c ... Back surface peripheral part of single crystal silicon substrate 1d ... Back surface of single crystal silicon substrate 2 ... i-type amorphous silicon layer 3 ... p-type amorphous silicon layer 4 ... transparent electrode 5 ... i-type amorphous silicon layer 6 ... n-type amorphous silicon layer 7 ... transparent electrode 8,9 ... collecting electrode 10 ... photovoltaic cell 11 ... glass Plate 12 ... Back surface protective film 13 ... Filler 14 ... Incident light 20 ... Resist film
Claims (8)
前記半導体基板の側面及び裏面周辺部にもテクスチャー構造の凹凸が形成されていることを特徴とする光起電力装置。 In a photovoltaic device comprising a photovoltaic cell using a semiconductor substrate with textured irregularities formed on the main surface,
The photovoltaic device according to claim 1, wherein unevenness having a texture structure is also formed on a side surface and a back surface peripheral portion of the semiconductor substrate.
The said unevenness | corrugation is formed by wet-etching the said board | substrate in the state which covered areas other than a peripheral part in the back surface of the said semiconductor substrate, The any one of Claims 1-7 characterized by the above-mentioned. Photovoltaic device.
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| US8872021B2 (en) | 2008-09-24 | 2014-10-28 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device and manufacturing method thereof |
| US9450132B2 (en) | 2008-09-24 | 2016-09-20 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device and manufacturing method thereof |
| JP2012044024A (en) * | 2010-08-20 | 2012-03-01 | Mitsubishi Chemicals Corp | Solar battery module |
| JP2018113462A (en) * | 2013-02-26 | 2018-07-19 | パナソニックＩｐマネジメント株式会社 | Solar cell module |
| WO2015068341A1 (en) * | 2013-11-08 | 2015-05-14 | パナソニックＩｐマネジメント株式会社 | Solar cell |
| JPWO2015068341A1 (en) * | 2013-11-08 | 2017-03-09 | パナソニックＩｐマネジメント株式会社 | Solar cell |
| JP2016072522A (en) * | 2014-09-30 | 2016-05-09 | 株式会社カネカ | Manufacturing method of silicon substrate for solar cell, manufacturing method of solar cell, and manufacturing method of solar cell module |
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