JP2006278641A - 半導体装置の製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 61
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 52
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 95
- 239000010703 silicon Substances 0.000 claims abstract description 95
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 94
- 238000010438 heat treatment Methods 0.000 claims abstract description 32
- 238000002513 implantation Methods 0.000 claims description 80
- 238000009792 diffusion process Methods 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 40
- 230000003647 oxidation Effects 0.000 claims description 18
- 238000007254 oxidation reaction Methods 0.000 claims description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 15
- 239000000126 substance Substances 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 9
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 description 77
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 45
- 229910052796 boron Inorganic materials 0.000 description 44
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 38
- 229910052698 phosphorus Inorganic materials 0.000 description 38
- 239000011574 phosphorus Substances 0.000 description 38
- 230000007547 defect Effects 0.000 description 34
- 230000015572 biosynthetic process Effects 0.000 description 32
- 108091006146 Channels Proteins 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
- 229910052814 silicon oxide Inorganic materials 0.000 description 17
- 230000014759 maintenance of location Effects 0.000 description 14
- 230000000694 effects Effects 0.000 description 12
- 239000012535 impurity Substances 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 11
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000012299 nitrogen atmosphere Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000001186 cumulative effect Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
【解決手段】半導体装置の製造方法は、(A)シリコン基板中に第1導電型のチャネルドープ層を形成する工程と、(B)そのチャネルドープ層中の領域であって、MOSトランジスタのソース・ドレインが形成される領域内に、シリコンを注入する工程と、(C)上記(B)工程の後に、熱処理を行う工程と、(D)上記(C)工程の後に、シリコン基板中にソース・ドレインを形成する工程とを備える。
【選択図】 図3
Description
本実施の形態において製造される半導体装置は、例えばDRAMである。図6は、製造されるDRAM1の断面構造を示している。このDRAM1において、ビット線30を共有する2つのセルトランジスタが1つの活性領域に形成されている。その活性領域は、半導体基板(シリコン基板)に埋め込まれた素子分離構造(STI: Shallow Trench Isolation)10によって囲まれている。また、シリコン基板中にp型ウエル層2が形成され、そのp型ウエル層2中にp型チャネルドープ層3が形成されている。p型ウエル層2には、少なくとも基板電位が与えられ、また、p型チャネルドープ層3は、トランジスタのしきい値電圧を決定する。また、基板表面付近には、ソース・ドレインとなるn型(低濃度)拡散層4が形成されている。また、n型拡散層4の下には、電界緩和のための埋め込み層9が形成されている。尚、p型ウエル層2の下部には、図示されていないn型埋め込みウエル層が形成されている。
図12は、本発明の第2の実施の形態に係る半導体装置の製造方法を示すフローチャートである。本実施の形態において、第1の実施の形態と同様の工程の説明は、適宜省略される。
2 p型ウエル層
3 p型チャネルドープ層
4 n型拡散層
5 ソース・ドレイン形成領域
9 埋め込み層
10 STI
11 ゲート絶縁膜
20 ゲート電極
22 酸化膜
23 サイドスペーサ
30 ビット線
31 プラグ
32 絶縁膜
33 層間絶縁膜
41 層間絶縁膜
42 層間絶縁膜
43 プラグ
50 キャパシタ
61 シリコン酸化膜
62 n型埋め込みウエル層
63 多結晶シリコン膜
64 タングステンシリサイド膜
65 シリコン酸化膜
Claims (10)
- MOSトランジスタを有する半導体装置の製造方法であって、
(A)シリコン基板中に第1導電型のチャネルドープ層を形成する工程と、
(B)前記チャネルドープ層中の領域であって、前記MOSトランジスタのソース・ドレインである第2導電型の拡散層が形成される領域内に、第1物質を注入する工程と、
(C)前記(B)工程の後に、熱処理を行う工程と、
(D)前記(C)工程の後に、前記シリコン基板中に前記拡散層を形成する工程と
を具備する
半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法であって、
前記第1物質は、シリコンである
半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法であって、
前記第1物質は、第IVB族元素である
半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法であって、
前記第1物質は、窒素である
半導体装置の製造方法。 - 請求項1乃至4のいずれかに記載の半導体装置の製造方法であって、
前記(B)工程において、前記第1物質の飛程が前記シリコン基板の表面からの前記拡散層の深さより小さくなるように、前記第1物質の注入エネルギーが決定される
半導体装置の製造方法。 - 請求項1乃至5のいずれかに記載の半導体装置の製造方法であって、
前記(B)工程における前記第1物質の注入量は、1×1013/cm2以上且つ1×1014/cm2以下である
半導体装置の製造方法。 - 請求項1乃至6のいずれかに記載の半導体装置の製造方法であって、
前記(C)工程において、前記熱処理は800℃〜1100℃の温度で実施される
半導体装置の製造方法。 - 請求項1乃至7のいずれかに記載の半導体装置の製造方法であって、
更に、
(E)前記シリコン基板上に、ゲート絶縁膜を介して前記MOSトランジスタのゲート電極を形成する工程と、
(F)前記(E)工程の後に、熱酸化処理を行う工程と
を具備し、
前記(E)工程及び前記(F)工程は、前記(A)工程と前記(B)工程の間に実行される
半導体装置の製造方法。 - 請求項1乃至7のいずれかに記載の半導体装置の製造方法であって、
更に、
(E)前記シリコン基板上に、ゲート絶縁膜を介して前記MOSトランジスタのゲート電極を形成する工程を具備し、
前記(E)工程は、前記(A)工程と前記(B)工程の間に実行され、
前記(C)工程において、熱酸化処理が行われる
半導体装置の製造方法。 - 請求項1乃至9のいずれかに記載の半導体装置の製造方法であって、
更に、
(G)前記拡散層に接続されるキャパシタを形成する工程を具備する
半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005094446A JP2006278641A (ja) | 2005-03-29 | 2005-03-29 | 半導体装置の製造方法 |
US11/390,138 US20060223292A1 (en) | 2005-03-29 | 2006-03-28 | Method of manufacturing semiconductor device |
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JP2005094446A JP2006278641A (ja) | 2005-03-29 | 2005-03-29 | 半導体装置の製造方法 |
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Publication Number | Publication Date |
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JP2006278641A true JP2006278641A (ja) | 2006-10-12 |
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JP2005094446A Pending JP2006278641A (ja) | 2005-03-29 | 2005-03-29 | 半導体装置の製造方法 |
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US (1) | US20060223292A1 (ja) |
JP (1) | JP2006278641A (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015023039A (ja) * | 2013-07-16 | 2015-02-02 | 住友重機械工業株式会社 | 半導体装置の製造方法及び製造装置 |
JP2015095534A (ja) * | 2013-11-12 | 2015-05-18 | 住友重機械工業株式会社 | 半導体装置の製造方法及び半導体製造装置 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7936017B2 (en) * | 2008-05-15 | 2011-05-03 | International Business Machines Corporation | Reduced floating body effect without impact on performance-enhancing stress |
KR101552921B1 (ko) * | 2014-09-29 | 2015-09-15 | 매그나칩 반도체 유한회사 | 비휘발성 메모리 소자 및 그 제조 방법 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3957945B2 (ja) * | 2000-03-31 | 2007-08-15 | 富士通株式会社 | 半導体装置及びその製造方法 |
JP2004221246A (ja) * | 2003-01-14 | 2004-08-05 | Seiko Epson Corp | 半導体装置及びその製造方法 |
US7101743B2 (en) * | 2004-01-06 | 2006-09-05 | Chartered Semiconductor Manufacturing L.T.D. | Low cost source drain elevation through poly amorphizing implant technology |
JP4870908B2 (ja) * | 2004-01-23 | 2012-02-08 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
-
2005
- 2005-03-29 JP JP2005094446A patent/JP2006278641A/ja active Pending
-
2006
- 2006-03-28 US US11/390,138 patent/US20060223292A1/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015023039A (ja) * | 2013-07-16 | 2015-02-02 | 住友重機械工業株式会社 | 半導体装置の製造方法及び製造装置 |
JP2015095534A (ja) * | 2013-11-12 | 2015-05-18 | 住友重機械工業株式会社 | 半導体装置の製造方法及び半導体製造装置 |
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