TWI497690B - 3d stacking semiconductor device and manufacturing method thereof - Google Patents
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Description
本發明是有關於一種半導體裝置及其製造方法，且特別是有關於一種三維堆疊半導體裝置及其製造方法。 The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a three-dimensional stacked semiconductor device and a method of fabricating the same.
隨著半導體技術的發展，各式半導體元件不斷推陳出新。半導體元件可以經過適當地安排後可以實現各種電性功能。現今各種電子產品皆已大量應用各種半導體元件。 With the development of semiconductor technology, various semiconductor components continue to evolve. The semiconductor elements can be appropriately arranged to realize various electrical functions. Various semiconductor components have been widely used in various electronic products today.
其中隨著電子產品追求「輕、薄、短、小」的趨勢下，如何將半導體元件的體積縮小，或者在固定體積下增加線路密集度，已成為半導體產業一項重要研究發展方向。 Among them, with the trend of "light, thin, short, and small" in electronic products, how to reduce the size of semiconductor components or increase the line density in a fixed volume has become an important research and development direction of the semiconductor industry.
本發明係有關於一種三維堆疊半導體裝置及其之製造方法。 The present invention relates to a three-dimensional stacked semiconductor device and a method of fabricating the same.
根據本發明之一方面，提出一種三維堆疊半導體裝置之製造方法。三維堆疊半導體裝置之製造方法包括以下步驟。提供N層堆疊結構。各個堆疊結構包括一導電層及一絕緣層。此些導電層及該些絕緣層交錯堆疊。N≦P×Q，N、P、Q為正整數。提供一第一光阻層。第一光阻層覆蓋此些堆疊結構之部分表面。以第一光阻層為遮罩，蝕刻(etch)P-1次此些堆疊結構。在此步驟之每次蝕刻中，此些堆疊結構被蝕刻一層的厚度，且在第1次~第P-2次蝕刻此些 堆疊結構後，皆削減(trim)第一光阻層之寬度一次。移除第一光阻層。提供一第二光阻層。第二光阻層覆蓋此些堆疊結構之部分表面。以第二光阻層為遮罩，蝕刻Q-1次此些堆疊結構。在此步驟之每次蝕刻中，此些堆疊結構被蝕刻P層的厚度，且在第1次~第Q-2次蝕刻此些堆疊結構後，皆削減第二光阻層之寬度一次。移除第二光阻層。設置N條導線，各該導線電性連接於各該導電層之一接點。第一光阻層係朝一第一方向削減寬度，第二光阻層係朝一第二方向削減寬度。第一方向不同於第二方向。數個接點沿著第一方向及第二方向陣列式排列。第一方向及第二方向之夾角係為銳角。 According to an aspect of the invention, a method of fabricating a three-dimensional stacked semiconductor device is presented. A method of manufacturing a three-dimensional stacked semiconductor device includes the following steps. An N-layer stack structure is provided. Each of the stacked structures includes a conductive layer and an insulating layer. The conductive layers and the insulating layers are alternately stacked. N≦P×Q, N, P, and Q are positive integers. A first photoresist layer is provided. The first photoresist layer covers a portion of the surface of the stacked structures. The stacked structure is etched P-1 times with the first photoresist layer as a mask. In each etching of this step, the stacked structures are etched to a thickness of one layer, and the first to the P-2th etching are performed. After stacking the structures, the width of the first photoresist layer is trimmed once. The first photoresist layer is removed. A second photoresist layer is provided. The second photoresist layer covers a portion of the surface of the stacked structures. The stack structure is etched Q-1 times with the second photoresist layer as a mask. In each etching of this step, the stacked structures are etched to the thickness of the P layer, and after the first to the Qth-2 etching of the stacked structures, the width of the second photoresist layer is reduced once. The second photoresist layer is removed. N wires are disposed, and each of the wires is electrically connected to one of the conductive layers. The first photoresist layer reduces the width toward a first direction, and the second photoresist layer decreases the width toward a second direction. The first direction is different from the second direction. A plurality of contacts are arranged in an array along the first direction and the second direction. The angle between the first direction and the second direction is an acute angle.
根據本發明之另一方面，提出一種三維堆疊半導體裝置。三維堆疊半導體裝置包括N層堆疊結構及N條導線。各個堆疊結構包括一導電層及一絕緣層。N為正整數。此些導電層及此些絕緣層交錯堆疊。各個導線電性連接各個導電層之一接點。其中此些接點沿著一第一方向以單層之差距排列成一P階層階梯狀結構，此些接點沿著一第二方向以P層之差距排列成一Q階層階梯狀結構。N≦P×Q。此些接點沿著第一方向及第二方向陣列式排列。第一方向及第二方向之夾角係為銳角。 According to another aspect of the present invention, a three-dimensional stacked semiconductor device is proposed. The three-dimensional stacked semiconductor device includes an N-layer stacked structure and N wires. Each of the stacked structures includes a conductive layer and an insulating layer. N is a positive integer. The conductive layers and the insulating layers are alternately stacked. Each of the wires is electrically connected to one of the contacts of each of the conductive layers. The contacts are arranged in a first layer along a first layer to form a P-level stepped structure. The contacts are arranged in a second direction along a gap of the P layer to form a Q-level stepped structure. N≦P×Q. The contacts are arranged in an array along the first direction and the second direction. The angle between the first direction and the second direction is an acute angle.
為讓本發明之上述內容能更明顯易懂，下文特舉各種佳實施例，並配合所附圖式，作詳細說明如下： In order to make the above-mentioned contents of the present invention more comprehensible, various preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:
以下係提出各種實施例進行詳細說明，實施例僅用以 作為範例說明，並不會限縮本發明欲保護之範圍。此外，實施例中之圖式係省略部份元件，以清楚顯示本發明之技術特點。 The following is a detailed description of various embodiments, and the embodiment is only used to The illustrations are not intended to limit the scope of the invention as claimed. Further, the drawings in the embodiments are omitted to partially illustrate the technical features of the present invention.
請參照第1圖，其繪示三維堆疊半導體裝置100之示意圖。三維堆疊半導體裝置100包括N層堆疊結構110及N條導線140。各個堆疊結構110包括一導電層111及一絕緣層112。N為正整數，例如是18。各個導電層111具有一停止層120。此些導線140穿過這些停止層120，以各自傳遞N層導電層111之訊號。透過三維堆疊半導體裝置100的設計，可以使N層導電層111密集地堆疊，並且使導線140密集地排列。 Please refer to FIG. 1 , which illustrates a schematic diagram of a three-dimensional stacked semiconductor device 100 . The three-dimensional stacked semiconductor device 100 includes an N-layer stacked structure 110 and N wires 140. Each of the stacked structures 110 includes a conductive layer 111 and an insulating layer 112. N is a positive integer, for example 18 . Each of the conductive layers 111 has a stop layer 120. The wires 140 pass through the stop layers 120 to respectively transmit signals of the N conductive layers 111. Through the design of the three-dimensional stacked semiconductor device 100, the N-layer conductive layers 111 can be densely stacked, and the wires 140 are densely arranged.
請參照第2A~2R圖，其繪示三維堆疊半導體裝置100之製造方法的流程圖。在一實施例中，可以透過多層光阻層搭配多方向之削減(trim)技術來形成三維堆疊半導體裝置100。第2A~2R圖係透過兩層光阻層及兩個方向之削減技術來完成N層堆疊結構110之三維堆疊半導體裝置100。 Please refer to FIGS. 2A-2R for a flowchart of a method of manufacturing the three-dimensional stacked semiconductor device 100. In one embodiment, the three-dimensional stacked semiconductor device 100 can be formed by a multi-layer photoresist layer in combination with a multi-directional trim technique. The 2A~2R pattern completes the three-dimensional stacked semiconductor device 100 of the N-layer stacked structure 110 through two layers of photoresist layers and two directions of reduction techniques.
如第2A~2E圖所示，其透過第一光阻層810來進行製程，以形成P階層階梯狀結構。P係為正整數，例如是3。如第2F~2P圖所示，其透過第二光阻層820來進行製程，以形成Q階層階梯狀結構。Q係為正整數，例如是6。N≦P×Q。例如是18≦3×6。以下之N、P、Q係直接以18、3、6為例做說明。 As shown in FIGS. 2A-2E, the process is performed through the first photoresist layer 810 to form a P-level stepped structure. P is a positive integer, for example, 3. As shown in FIGS. 2F-2P, the process is performed through the second photoresist layer 820 to form a Q-level stepped structure. Q is a positive integer, for example, 6. N≦P×Q. For example, it is 18≦3×6. The following N, P, and Q series are directly illustrated by 18, 3, and 6 as examples.
在第2A圖中，提供堆疊結構110。此時，18層堆疊結構110皆未被蝕刻。18層導電層111與18層絕緣層112 密集地交錯堆疊。 In Figure 2A, a stacked structure 110 is provided. At this time, the 18-layer stacked structure 110 is not etched. 18 conductive layers 111 and 18 insulating layers 112 Densely staggered stacks.
在第2A圖中，更提供第一光阻層810。第一光阻層810覆蓋18層堆疊結構110之部分表面。 In FIG. 2A, a first photoresist layer 810 is further provided. The first photoresist layer 810 covers a portion of the surface of the 18-layer stacked structure 110.
在第2B圖中，以第一光阻層810為遮罩，蝕刻(etch)堆疊結構110。在此次蝕刻中，此些堆疊結構110之暴露的部份被蝕刻一層的厚度。 In FIG. 2B, the stacked structure 110 is etched with the first photoresist layer 810 as a mask. In this etch, the exposed portions of such stacked structures 110 are etched to a thickness of one layer.
在第2C圖中，朝一第一方向C11削減(trim)第一光阻層810之寬度，以暴露此些堆疊結構110之其中2層。 In FIG. 2C, the width of the first photoresist layer 810 is trimmed toward a first direction C11 to expose two of the stacked structures 110.
在第2D圖中，以已削減之第一光阻層810為遮罩，蝕刻此些堆疊結構110。在此次蝕刻中，此些堆疊結構110之暴露的部份被蝕刻1層的厚度。也就是說，第一層及第二層之堆疊結構110的一部份被同時蝕刻1層之厚度。 In FIG. 2D, the stacked structures 110 are etched using the reduced first photoresist layer 810 as a mask. In this etch, the exposed portions of such stacked structures 110 are etched to a thickness of one layer. That is, a portion of the stacked structure 110 of the first layer and the second layer is simultaneously etched by a thickness of one layer.
在第2E圖中，移除第一光阻層810，以形成3個階層。 In FIG. 2E, the first photoresist layer 810 is removed to form three levels.
在第2A~2E圖之步驟中，共蝕刻2(即P-1)次堆疊結構110。在每次蝕刻中，此些堆疊結構110之暴露的部份被蝕刻一層的厚度，且在第1(即P-2)次蝕刻此些堆疊結構110後，朝第一方向C11削減第一光阻層810之寬度一次。在第2A~2E之實施例中，係以3階層為例做說明。若推廣至P階層，則是以第一光阻層810為遮罩，蝕刻P-1次此些堆疊結構110。在每次蝕刻中，此些堆疊結構110被蝕刻一層的厚度，且在第1次~第P-2次蝕刻此些堆疊結構110後，皆朝第一方向C11削減第一光阻層810之寬度一次。 In the steps of FIGS. 2A-2E, a total of 2 (ie, P-1) stacked structures 110 are etched. In each etching, the exposed portions of the stacked structures 110 are etched to a thickness, and after the first (ie, P-2) etching of the stacked structures 110, the first light is cut toward the first direction C11. The width of the resist layer 810 is once. In the embodiments of the second embodiment 2A to 2E, the three levels are taken as an example for explanation. If it is extended to the P-level, the first photoresist layer 810 is used as a mask, and the stacked structures 110 are etched P-1 times. In each etching, the stacked structures 110 are etched to a thickness of one layer, and after the first to the P-2th etching of the stacked structures 110, the first photoresist layer 810 is cut toward the first direction C11. Width once.
接著，在第2F圖中，提供第二光阻層820。第二光 阻層820覆蓋此些堆疊結構110之部份表面。 Next, in the 2Fth diagram, the second photoresist layer 820 is provided. Second light The resist layer 820 covers a portion of the surface of the stacked structures 110.
在第2G圖中，以第二光阻層820為遮罩，蝕刻此些堆疊結構110。在此次蝕刻中，此些堆疊結構110之暴露的部份被蝕刻3層的厚度。也就是說，第1~3層之堆疊結構110的一部份被同時蝕刻3層之厚度。 In FIG. 2G, the stacked structures 110 are etched with the second photoresist layer 820 as a mask. In this etch, the exposed portions of such stacked structures 110 are etched to a thickness of three layers. That is, a portion of the stacked structures 110 of the first to third layers is simultaneously etched to a thickness of three layers.
在第2H圖中，朝第二方向C12削減第二光阻層820之寬度，以暴露此些堆疊結構110之其中6層。 In FIG. 2H, the width of the second photoresist layer 820 is reduced toward the second direction C12 to expose six of the stacked structures 110.
在第2I圖中，以已削減之第二光阻層820為遮罩，蝕刻此些堆疊結構110。在此次蝕刻中，此些堆疊結構110之暴露的部份被蝕刻3層的厚度。也就是說，第1~6層之堆疊結構110的一部份被同時蝕刻3層之厚度。 In FIG. 2I, the stacked structures 110 are etched by using the reduced second photoresist layer 820 as a mask. In this etch, the exposed portions of such stacked structures 110 are etched to a thickness of three layers. That is, a portion of the stacked structures 110 of the first to sixth layers are simultaneously etched to a thickness of three layers.
在第2J圖中，朝第二方向C12削減第二光阻層820之寬度，以暴露此些堆疊結構110之其中9層。 In FIG. 2J, the width of the second photoresist layer 820 is reduced toward the second direction C12 to expose nine of the stacked structures 110.
在第2K圖中，以已削減之第二光阻層820為遮罩，蝕刻此些堆疊結構110。在此次蝕刻中，此些堆疊結構110之暴露的部份被蝕刻3層的厚度。也就是說，第1~9層之堆疊結構110的一部份被同時蝕刻3層之厚度。 In FIG. 2K, the stacked structures 110 are etched by masking the second photoresist layer 820 that has been cut. In this etch, the exposed portions of such stacked structures 110 are etched to a thickness of three layers. That is, a portion of the stacked structures 110 of the first to ninth layers are simultaneously etched to a thickness of three layers.
在第2L圖中，朝第二方向C12削減第二光阻層820之寬度，以暴露此些堆疊結構110之其中12層。 In the 2nd L, the width of the second photoresist layer 820 is reduced toward the second direction C12 to expose 12 of the stacked structures 110.
在第2M圖中，以已削減之第二光阻層820為遮罩，蝕刻此些堆疊結構110。在此次蝕刻中，此些堆疊結構110之暴露的部份被蝕刻3層的厚度。也就是說，第1~12層之堆疊結構110的一部份被同時蝕刻3層之厚度。 In FIG. 2M, the stacked structures 110 are etched by using the reduced second photoresist layer 820 as a mask. In this etch, the exposed portions of such stacked structures 110 are etched to a thickness of three layers. That is, a portion of the stacked structures 110 of the 1st to 12th layers are simultaneously etched to a thickness of 3 layers.
在第2N圖中，朝第二方向C12削減第二光阻層820之寬度，以暴露此些堆疊結構110之其中15層。 In the 2Nth figure, the width of the second photoresist layer 820 is reduced toward the second direction C12 to expose 15 of the stacked structures 110.
在第20圖中，以已削減之第二光阻層820為遮罩，蝕刻此些堆疊結構110。在此次蝕刻中，此些堆疊結構110之暴露的部份被蝕刻3層的厚度。也就是說，第1~15層之堆疊結構110的一部份被同時蝕刻3層之厚度。 In FIG. 20, the stacked structures 110 are etched using the reduced second photoresist layer 820 as a mask. In this etch, the exposed portions of such stacked structures 110 are etched to a thickness of three layers. That is, a portion of the stacked structure 110 of the first to fifteenth layers is simultaneously etched to a thickness of three layers.
在第2P圖中，移除第二光阻層820，以形成18個階層。 In the 2P figure, the second photoresist layer 820 is removed to form 18 levels.
在第2F~2P圖之步驟中，共蝕刻5(即Q-1)次堆疊結構110。在每次蝕刻中，此些堆疊結構110之暴露的部份被蝕刻3(即P)層的厚度，且在第1~4(即1~Q-2)次蝕刻此些堆疊結構110後，朝第二方向C12削減第二光阻層820之寬度一次。在第2E~2P之實施例中，係以6階層為例做說明。若推廣至Q階層，則是以第二光阻層820為遮罩，蝕刻Q-1次此些堆疊結構110。在此步驟之每次蝕刻中，此些堆疊結構110被蝕刻P層的厚度，且在第1次~第Q-2次蝕刻此些堆疊結構110後，皆朝第二方向C12削減第二光阻層820之寬度一次。 In the step of the 2F~2P diagram, 5 (i.e., Q-1) times of the stacked structure 110 are etched. In each etching, the exposed portions of the stacked structures 110 are etched to a thickness of 3 (ie, P) layers, and after the first to fourth (ie, 1 to Q-2) etching of the stacked structures 110, The width of the second photoresist layer 820 is reduced once in the second direction C12. In the second embodiment of the second embodiment, the six levels are taken as an example for explanation. If it is extended to the Q level, the second photoresist layer 820 is used as a mask, and the stacked structures 110 are etched Q-1 times. In each etching of this step, the stacked structures 110 are etched to a thickness of the P layer, and after the first to the Qth-2 etchings of the stacked structures 110, the second light is cut toward the second direction C12. The width of the resist layer 820 is once.
在第2Q圖中，形成停止層120於此些堆疊結構110之暴露之部分。 In the 2Q figure, the portion of the stop layer 120 exposed by the stacked structures 110 is formed.
在第2R圖中，於各個堆疊結構110所暴露出之導電層111上形成停止層120，並以導線140穿過此些停止層120，以連接到導電層111。 In FIG. 2R, a stop layer 120 is formed on the conductive layer 111 exposed by each of the stacked structures 110, and the wires 140 are passed through the stop layers 120 to be connected to the conductive layer 111.
如此一來，即可在相當狹小的體積內形成密集的18階層三維堆疊半導體裝置100。其中，在第2A~2E圖中，第一光阻層810係朝第一方向C11削減寬度；在第2F~2P圖中，第二光阻層820係朝第二方向C12削減寬度。第一 方向C11不同於第二方向C12，而使蝕刻過程中能夠在第一方向C11及第二方向C12皆形成數層階梯，而交織成矩陣式階梯結構。 As a result, a dense 18-layer three-dimensional stacked semiconductor device 100 can be formed in a relatively small volume. In the second to second E-pictures, the first photoresist layer 810 has a width reduced in the first direction C11, and in the second and second P-pictures, the second photoresist layer 820 has a width reduced in the second direction C12. the first The direction C11 is different from the second direction C12, so that a plurality of steps can be formed in the first direction C11 and the second direction C12 during the etching process, and interlaced into a matrix step structure.
在第2A~2R圖之實施例中，第一方向C11與第二方向C12之夾角係以實質上為直角為例做說明。在一實施例中，第一方向C11與第二方向C12之夾角也可以是銳角。 In the embodiment of the 2A-2R diagram, the angle between the first direction C11 and the second direction C12 is substantially a right angle as an example. In an embodiment, the angle between the first direction C11 and the second direction C12 may also be an acute angle.
在本實施例中，三維堆疊半導體裝置100具有N層堆疊結構110，在第一方向C11以單層之差距排列成P階層階梯狀結構，在第二方向C12以P層之差距排列成Q階層階梯狀結構。本實施例之N、P、Q係分別以18、3、6為例做說明。在一實施例中，N、P、Q也可以是18、6、3或18、9、2，只要P、Q為N之因數皆可。 In the present embodiment, the three-dimensional stacked semiconductor device 100 has an N-layer stacked structure 110, which is arranged in a P-level step structure in a first direction C11 by a single layer, and is arranged in a Q-level in a second direction C12 by a P-layer gap. Stepped structure. The N, P, and Q systems of the present embodiment are described by taking 18, 3, and 6 as examples, respectively. In an embodiment, N, P, and Q may also be 18, 6, 3, or 18, 9, and 2, as long as P and Q are N factors.
上述實施例係以兩個模組(P個階層與Q個階層)來形成三維堆疊半導體裝置100，在另一實施例中，也可以三個模組(例如是P個階層、Q個階層及R個階層)來形成三維堆疊半導體裝置200。請參照第3A~3B圖，其繪示三維堆疊半導體裝置200之製造方法的流程圖。在第3A圖中，可以透過類似第2A~2R之方式形成P階層階梯狀結構及Q階層階梯狀結構所組成之一P×Q階層階梯狀結構(例如是3×6階層階梯狀結構)。 In the above embodiment, the three-dimensional stacked semiconductor device 100 is formed by two modules (P levels and Q levels). In another embodiment, three modules (for example, P levels, Q levels, and The R layers are formed to form a three-dimensional stacked semiconductor device 200. Please refer to FIGS. 3A-3B for a flowchart of a method of manufacturing the three-dimensional stacked semiconductor device 200. In FIG. 3A, a P×Q hierarchical stepped structure (for example, a 3×6 hierarchical stepped structure) composed of a P-level stepped structure and a Q-level stepped structure can be formed by a method similar to the 2A to 2R.
在第3B圖中，提供一第三光阻層830。第三光阻層830覆蓋部份之堆疊結構210。各個堆疊結構210包括導電層211及絕緣層212。然後。以第三光阻層830為遮罩，蝕刻1次堆疊結構210。每次蝕刻堆疊結構21018層之厚度。在第3A~3B圖之實施例中，係以2階層為例做說 明。若推廣至R階層，則以第三光阻層830為遮罩，蝕刻R-1次堆疊結構210，每次蝕刻堆疊結構210 P×Q層之厚度，且在第1次~第R-2次蝕刻堆疊結構210後，皆削減第三光阻層830之寬度一次。 In FIG. 3B, a third photoresist layer 830 is provided. The third photoresist layer 830 covers a portion of the stacked structure 210. Each of the stacked structures 210 includes a conductive layer 211 and an insulating layer 212. then. The stacked structure 210 is etched once with the third photoresist layer 830 as a mask. The thickness of the layer of the stacked structure 21018 is etched each time. In the embodiment of Figures 3A-3B, the two classes are taken as an example. Bright. If it is extended to the R level, the third photoresist layer 830 is used as a mask, and the R-1 sub-stack structure 210 is etched, and the thickness of the P×Q layer of the stacked structure 210 is etched each time, and the first to the R-2 are performed. After the stack structure 210 is etched, the width of the third photoresist layer 830 is reduced once.
也就是說，若欲形成N階層之三維堆疊半導體裝置，可以透過P階層、Q階層、R階層等三階段來完成，P×Q階層階梯狀結構沿著第一方向以P×Q層之差距排列成一P×Q×R階層階梯狀結構。其中N、P、Q、R為正整數，N≦P×Q×R，且P、Q、R為N之因數。 That is to say, if a three-dimensional stacked semiconductor device of N-level is to be formed, it can be completed through three stages of P-level, Q-level, and R-level, and the P×Q-level step-like structure is separated by P×Q layer along the first direction. Arranged into a P × Q × R hierarchical step structure. Where N, P, Q, and R are positive integers, N≦P×Q×R, and P, Q, and R are factors of N.
同樣地，若依序推廣，N階層之三維堆疊半導體裝置可以透過P階層、Q階層、R階層、S階層等四階段來完成。P×Q×R階層階梯狀結構沿著第二方向以P×Q×R層之差距排列成一P×Q×R×S階層階梯狀結構。其中N、P、Q、R、S為正整數，N≦P×Q×R×S，且P、Q、R、S為N之因數。三維堆疊半導體裝置完成P階層、Q階層、R階層之後，可以提供一第四光阻層，第四光阻層覆蓋部份之堆疊結構。再以第四光阻層為遮罩，蝕刻S-1次堆疊結構，每次蝕刻堆疊結構P×Q×R層，且在第1次~第S-2次蝕刻該堆疊結構後，皆削減該第四光阻層之寬度一次。 Similarly, if sequentially promoted, the three-dimensional stacked semiconductor device of the N-layer can be completed by four stages of the P-level, the Q-level, the R-level, and the S-level. The P×Q×R hierarchical step structure is arranged along the second direction by a gap of P×Q×R layers into a P×Q×R×S hierarchical step structure. Where N, P, Q, R, S are positive integers, N≦P×Q×R×S, and P, Q, R, and S are factors of N. After the three-dimensional stacked semiconductor device completes the P-level, the Q-level, and the R-level, a fourth photoresist layer may be provided, and the fourth photoresist layer covers a stacked portion of the portion. Then, the fourth photoresist layer is used as a mask, and the S-1 times stacked structure is etched, and the stacked structure P×Q×R layer is etched each time, and after the first to the S-2th etching of the stacked structure, both are cut. The width of the fourth photoresist layer is once.
依照類似之方式，即可繼續推廣以五階段以上來完成三維堆疊半導體裝置。 In a similar manner, it is possible to continue to promote three-dimensional stacked semiconductor devices in five stages or more.
請參照第4A~4C圖，其繪示光阻層910在蝕刻及削減過程中的變化示意圖。如第4A~4B圖所示，在蝕刻堆疊結構310過程中，光阻層910將會被消耗厚度h1(約500)。如第4B~4C圖所示，在削減光阻層910之寬度tx 過程中，光阻層910將會被消耗厚度t1(約4000)。所以上述製造過程必須考量到光阻層910在蝕刻及削減過程的消耗量。 Please refer to FIGS. 4A-4C for a schematic diagram showing changes in the photoresist layer 910 during etching and cutting. As shown in FIGS. 4A-4B, during etching of the stacked structure 310, the photoresist layer 910 will be consumed by a thickness h1 (about 500). ). As shown in FIGS. 4B-4C, during the process of reducing the width tx of the photoresist layer 910, the photoresist layer 910 will be consumed by a thickness t1 (about 4000). ). Therefore, the above manufacturing process must take into account the consumption of the photoresist layer 910 during the etching and reduction process.
以表1為例，當N為36，採用一階段來形成具有36階層之三維堆疊半導體裝置時，削減次數為34次，蝕刻層數為35層，因此光阻層總消耗量為153500。 Taking Table 1 as an example, when N is 36, a three-stage stacked semiconductor device having 36 levels is formed in one stage, the number of reductions is 34, and the number of etching layers is 35, so the total consumption of the photoresist layer is 153,500. .
以表2A為例，當N為36，採用二階段來形成具有36階層之三維堆疊半導體裝置時，第一階段與第二階段之P與Q可以是採用各種組合，例如是編號2-1、2-2、2-3等三種組合。如表2B所示，第一階段採用6個階層且第二階段採用6個階層時，可以獲得較低的光阻層總消耗量。 Taking Table 2A as an example, when N is 36 and two stages are used to form a three-dimensional stacked semiconductor device having 36 levels, P and Q of the first stage and the second stage may be in various combinations, for example, number 2-1. Two combinations of 2-2 and 2-3. As shown in Table 2B, when the first stage uses 6 levels and the second stage uses 6 levels, a lower total photoresist layer consumption can be obtained.
因第二階段蝕刻層數較多，第二階段單次蝕刻所造成之光阻層消耗量會大於第一階段單次蝕刻的光阻層消耗量。考量每階段削減與蝕刻造成的光阻耗損總量，Q≦P是較佳選擇。例如；表2B的編號2-1，第一階段光阻需求9500；而第二階段光阻需求44000，非常高。此外，光阻太厚的缺點：1、光學解晰度降低；2、光阻厚度在製程上有一定極限。因此編號2-1不是最佳方案。編號2-2、編號2-3是較佳選擇方案。 Due to the large number of etching layers in the second stage, the consumption of the photoresist layer caused by the single etching in the second stage is greater than the consumption of the photoresist layer in the single etching in the first stage. Considering the total amount of photoresist loss caused by the reduction and etching at each stage, Q≦P is the better choice. For example; number 2-1 of Table 2B, first stage photoresist requirement 9500 And the second stage photoresist demand 44000 ,very high. In addition, the shortcomings of the photoresist are too thick: 1. The optical resolution is reduced; 2. The photoresist thickness has a certain limit on the process. Therefore number 2-1 is not the best solution. No. 2-2 and No. 2-3 are preferred options.
以表3A為例，當N為36，採用三階段來形成具有36階層之三維堆疊半導體裝置時，第一階段、第二階段與第三階段之P、Q與R可以是採用各種組合，例如是編號3-1、3-2、3-3、3-4等四種組合。如表3B所示，第一階段採用3個階層、第二階段採用3個階層且第三階段採用4個階層可以獲得較低的光阻層總消耗量。 Taking Table 3A as an example, when N is 36 and three-stage is used to form a three-dimensional stacked semiconductor device having 36 levels, P, Q, and R of the first stage, the second stage, and the third stage may be in various combinations, for example, It is a combination of numbers 3-1, 3-2, 3-3, 3-4, and so on. As shown in Table 3B, the first stage uses three levels, the second stage uses three levels, and the third stage uses four levels to obtain a lower total photoresist layer consumption.
通常導入新階段的原因是光阻厚度碰到極限、削減次數過多引發對準疑慮、或有設計規則(Design Rule)放 大的疑慮。以光阻厚度為例，如果每階段厚度極限是20000，那表2B沒有可選擇的方案；而表3B也只有編號3-2與編號3-4可以使用。 The reason for the new phase is usually that the photoresist thickness hits the limit, the number of cuts is too high, causing misalignment, or the design rule is enlarged. Take the photoresist thickness as an example, if the thickness limit per stage is 20000 , Table 2B has no alternative; and Table 3B is only available with numbers 3-2 and 3-4.
進一步來說，第三階段單次蝕刻所造成之光阻層消耗量會大於第二階段單次蝕刻的光阻層消耗量。考量每階段削減與蝕刻造成的光阻耗損總量，R≦Q≦P是較佳選擇。 Further, the photoresist layer consumption caused by the single etching in the third stage is greater than the photoresist layer consumption in the single etching in the second stage. Considering the total amount of photoresist loss caused by the reduction and etching at each stage, R≦Q≦P is a better choice.
依此類推，進一步採用第四階段之S階層時，S≦R≦Q≦P是較佳選擇。 And so on, when using the S-stage of the fourth stage, S≦R≦Q≦P is a better choice.
請參照第5圖，其繪示導線440與導線440連接於導電層411之接點411a之配置圖。上述三維堆疊半導體裝置可以密集地堆疊多層導電層411，導線440連接於導電層411之接點411a也密集地排列。在製造過程中，當光阻層朝第一方向C41與第二方向C42削減時，接點411a也將沿著第一方向C41及第二方向C42陣列式排列。若第一方向C41及第二方向C42之夾角θ 1實質上為直角，在配置導線440時，導線440可以成L型，以錯開此些導線440。 Please refer to FIG. 5 , which shows a layout diagram of the wires 440 and the wires 440 connected to the contacts 411 a of the conductive layer 411 . The three-dimensional stacked semiconductor device can densely stack the plurality of conductive layers 411, and the contacts 411a of the wires 440 connected to the conductive layer 411 are also densely arranged. During the manufacturing process, when the photoresist layer is cut toward the first direction C41 and the second direction C42, the contacts 411a are also arranged in an array along the first direction C41 and the second direction C42. If the angle θ 1 between the first direction C41 and the second direction C42 is substantially a right angle, when the wire 440 is disposed, the wire 440 may be L-shaped to stagger the wires 440.
請參照第6圖，其繪示導線540與導線540連接於導電層511之接點511a之配置圖。上述三維堆疊半導體裝置可以密集地堆疊多層導電層511，導線540連接於導電層511之接點511a也密集地。在製造過程中，當光阻層朝第一方向C51與第二方向C52削減時，接點511a也將沿著第一方向C51及第二方向C52陣列式排列。若第一方向C51及第二方向C52之夾角θ 2為銳角，在配置導線540時，導線540無須成L型，可以自此些接點511a朝同一方向平行式直線延伸，即可錯開此些導線540。 Please refer to FIG. 6 , which shows a layout diagram of the wire 540 and the wire 540 connected to the contact point 511 a of the conductive layer 511 . The above three-dimensional stacked semiconductor device can densely stack a plurality of conductive layers 511, and the contacts 511a of the wires 540 connected to the conductive layer 511 are also dense. During the manufacturing process, when the photoresist layer is cut in the first direction C51 and the second direction C52, the contacts 511a are also arranged in an array along the first direction C51 and the second direction C52. If the angle θ 2 between the first direction C51 and the second direction C52 is an acute angle, when the wire 540 is disposed, the wire 540 does not need to be L-shaped, and the wire 540 can extend parallel to the same direction from the contacts 511a, so that the wires 540 can be staggered. Wire 540.
此外，當第一方向C51與第二方向C52之夾角θ 2為銳角時，光阻層原本需要削減之寬度tx也可變為寬度tx’。其中寬度tx’為寬度tx之sin(θ 2)倍。 Further, when the angle θ 2 between the first direction C51 and the second direction C52 is an acute angle, the width tx which the photoresist layer originally needs to be reduced may also become the width tx'. Wherein the width tx' is sin(θ 2) times the width tx.
此外，請參照第7~8圖，其繪示接點611a與邊界之距離D1、D2、D3隨削減之變化關係圖。相鄰兩個接點611a之間距p係為固定。如第7圖所示，在理想狀況下，每次次光阻削減之寬度tx皆保持固定。因此，第7圖之接點 611a與邊界之距離D1、D2、D3可以固定於p/2。 In addition, please refer to FIGS. 7-8, which show the relationship between the distance D1, D2, and D3 of the contact 611a and the boundary as a function of the reduction. The distance p between adjacent two contacts 611a is fixed. As shown in Fig. 7, under ideal conditions, the width tx of each photoresist cut is kept constant. Therefore, the joint of Figure 7 The distance D1, D2, D3 of 611a from the boundary may be fixed at p/2.
如第8圖所示，每次削減可能存在一誤差量dx。因此，第8圖之接點611a與邊界之距離D2將變為p/2-dx，接點611a與邊界之距離D3將變為p/2-2dx。依此類推，N層堆疊結構110做了N-1次削減光阻層之步驟之後，接點611a與邊界之距離將縮小為p/2-(N-1)*dx。為了讓接點611a與邊界之距離不會縮小至零，間距p必須大於2(N-1)*dx。 As shown in Fig. 8, there may be an error amount dx for each reduction. Therefore, the distance D2 between the contact 611a and the boundary in Fig. 8 will become p/2-dx, and the distance D3 between the contact 611a and the boundary will become p/2-2dx. Similarly, after the N-layer stack structure 110 performs the N-1 reduction of the photoresist layer, the distance between the contact 611a and the boundary is reduced to p/2-(N-1)*dx. In order for the distance between the contact 611a and the boundary to not decrease to zero, the pitch p must be greater than 2(N-1)*dx.
綜上所述，雖然本發明已以各種實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In view of the above, the present invention has been disclosed in various embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
100、200‧‧‧三維堆疊半導體裝置 100,200‧‧‧Three-dimensional stacked semiconductor device
110、210、310‧‧‧堆疊結構 110, 210, 310‧‧‧ stacked structure
111、211、411、511‧‧‧導電層 111, 211, 411, 511‧‧‧ conductive layer
111a、411a、511a、611a‧‧‧接點 111a, 411a, 511a, 611a‧‧‧ joints
112、212‧‧‧絕緣層 112, 212‧‧‧ insulation
120‧‧‧停止層 120‧‧‧stop layer
140、440、540‧‧‧導線 140, 440, 540‧‧‧ wires
810‧‧‧第一光阻層 810‧‧‧First photoresist layer
820‧‧‧第二光阻層 820‧‧‧second photoresist layer
610、910‧‧‧光阻層 610, 910‧‧ ‧ photoresist layer
830‧‧‧第三光阻層 830‧‧‧ Third photoresist layer
C11、C41、C51‧‧‧第一方向 C11, C41, C51‧‧‧ first direction
C12、C42、C52‧‧‧第二方向 C12, C42, C52‧‧‧ second direction
D1、D2、D3‧‧‧距離 D1, D2, D3‧‧‧ distance
dx‧‧‧誤差量 Dx‧‧‧ error amount
h1、t1‧‧‧厚度 H1, t1‧‧‧ thickness
p‧‧‧間距 P‧‧‧ spacing
tx、tx’‧‧‧寬度 Width of tx, tx’‧‧‧
θ 1、θ 2‧‧‧夾角 θ 1, θ 2‧‧‧ angle
第1圖繪示三維堆疊半導體裝置之示意圖。 FIG. 1 is a schematic diagram of a three-dimensional stacked semiconductor device.
第2A~2R圖繪示三維堆疊半導體裝置之製造方法的流程圖。 2A-2R are flowcharts showing a method of manufacturing a three-dimensional stacked semiconductor device.
第3A~3B圖繪示三維堆疊半導體裝置之製造方法的流程圖。 3A-3B are flow charts showing a method of manufacturing a three-dimensional stacked semiconductor device.
第4A~4C圖繪示光阻層在蝕刻及削減過程中的變化示意圖。 4A-4C are schematic diagrams showing changes in the photoresist layer during etching and cutting.
第5圖繪示導線與導線連接於導電層之接點之配置圖。 Figure 5 is a diagram showing the arrangement of the wires and the wires connected to the contacts of the conductive layer.
第6圖繪示導線與導線連接於導電層之接點之配置圖。 Figure 6 is a diagram showing the arrangement of the wires and the wires connected to the contacts of the conductive layer.
第7~8圖繪示接點與邊界之距離隨削減之變化關係圖。 Figures 7-8 show the relationship between the distance between the joint and the boundary as a function of the reduction.
100‧‧‧三維堆疊半導體裝置 100‧‧‧Three-dimensional stacked semiconductor device
110‧‧‧堆疊結構 110‧‧‧Stack structure
111‧‧‧導電層 111‧‧‧ Conductive layer
112‧‧‧絕緣層 112‧‧‧Insulation
120‧‧‧停止層 120‧‧‧stop layer
140‧‧‧導線 140‧‧‧Wire
C11‧‧‧第一方向 C11‧‧‧ first direction
C12‧‧‧第二方向 C12‧‧‧second direction
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100207186A1 (en) * | 2009-02-17 | 2010-08-19 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of manufacturing the same |
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