JP2006186320A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2006186320A5 JP2006186320A5 JP2005326358A JP2005326358A JP2006186320A5 JP 2006186320 A5 JP2006186320 A5 JP 2006186320A5 JP 2005326358 A JP2005326358 A JP 2005326358A JP 2005326358 A JP2005326358 A JP 2005326358A JP 2006186320 A5 JP2006186320 A5 JP 2006186320A5
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- forming
- electrodes
- layer
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 11
- 238000004519 manufacturing process Methods 0.000 claims 5
- 239000003990 capacitor Substances 0.000 claims 1
Claims (8)
前記絶縁表面上及び前記第1の電極上に設けられた第1の誘電層と、A first dielectric layer provided on the insulating surface and on the first electrode;
前記第1の誘電層上に設けられた第2の電極と、を有する容量素子を有し、A capacitive element having a second electrode provided on the first dielectric layer,
前記第1の電極は、互いに間隔をあけて配置された複数の電極よりなり、The first electrode is composed of a plurality of electrodes arranged at intervals from each other,
前記第2の電極は、凹凸形状を有し、The second electrode has an uneven shape,
前記第2の電極の凸部は、前記複数の電極の間に配置され、The convex portion of the second electrode is disposed between the plurality of electrodes,
前記第2の電極の凹部は、前記複数の電極と重なる位置に配置され、The concave portion of the second electrode is disposed at a position overlapping the plurality of electrodes,
前記第2の電極の上面は、平坦であることを特徴とする半導体装置。The semiconductor device is characterized in that an upper surface of the second electrode is flat.
前記容量素子は、前記第2の電極上に設けられた第2の誘電層と、前記第2の誘電層上に設けられた第3の電極と、を有することを特徴とする半導体装置。The capacitor element includes a second dielectric layer provided on the second electrode, and a third electrode provided on the second dielectric layer.
半導体層と、前記半導体層上に設けられたゲート絶縁層と、前記ゲート絶縁層上に設けられたゲート電極と、を有するTFTを有し、A TFT having a semiconductor layer, a gate insulating layer provided on the semiconductor layer, and a gate electrode provided on the gate insulating layer;
前記絶縁表面は、前記ゲート絶縁層の表面であることを特徴とする半導体装置。The semiconductor device, wherein the insulating surface is a surface of the gate insulating layer.
前記絶縁表面上及び前記第1の電極上に、第1の誘電層を形成し、Forming a first dielectric layer on the insulating surface and on the first electrode;
前記第1の誘電体層上に、凸部が前記複数の電極の間に配置され、且つ、凹部が前記複数の電極と重なる位置に配置された凹凸形状を有し、上面が平坦な第2の電極を形成することを特徴とする半導体装置の作製方法。On the first dielectric layer, a convex portion is disposed between the plurality of electrodes, and a concave portion is disposed at a position where the concave portion overlaps the plurality of electrodes, and the top surface is flat. A method for manufacturing a semiconductor device, characterized by forming an electrode.
前記半導体層上にゲート絶縁層を形成し、Forming a gate insulating layer on the semiconductor layer;
前記ゲート絶縁層上に、ゲート電極と、互いに間隔をあけて配置された複数の電極よりなる第1の電極と、を形成し、Forming a gate electrode and a first electrode composed of a plurality of electrodes spaced from each other on the gate insulating layer;
前記ゲート絶縁層上及び前記第1の電極上に、第1の誘電層を形成し、Forming a first dielectric layer on the gate insulating layer and on the first electrode;
前記第1の誘電体層上に、凸部が前記複数の電極の間に配置され、且つ、凹部が前記複数の電極と重なる位置に配置された凹凸形状を有し、上面が平坦な第2の電極を形成することを特徴とする半導体装置の作製方法。On the first dielectric layer, a convex portion is disposed between the plurality of electrodes, and a concave portion is disposed at a position where the concave portion overlaps the plurality of electrodes, and the top surface is flat. A method for manufacturing a semiconductor device, characterized by forming an electrode.
前記第2の電極上に第2の誘電層を形成し、Forming a second dielectric layer on the second electrode;
前記第2の誘電層上に第3の電極を形成することを特徴とする半導体装置の作製方法。A method for manufacturing a semiconductor device, wherein a third electrode is formed over the second dielectric layer.
前記第2の電極を、The second electrode;
前記第1の誘電体層上の前記複数の電極と重なる位置及び前記複数の電極の間に、導電層を形成し、Forming a conductive layer between the plurality of electrodes and a position overlapping the plurality of electrodes on the first dielectric layer;
前記導電層の上面を平坦化することによって形成することを特徴とする半導体装置の作製方法。A method for manufacturing a semiconductor device, comprising forming the top surface of the conductive layer by planarization.
前記第2の電極を、The second electrode;
前記第1の誘電体層上であって前記複数の電極の間に、第1の導電層を形成し、Forming a first conductive layer on the first dielectric layer and between the plurality of electrodes;
前記第1の導電層上及び前記第1の誘電体層上の前記複数の電極と重なる位置に、第2の導電層を形成することによって形成することを特徴とする半導体装置の作製方法。A method for manufacturing a semiconductor device, comprising: forming a second conductive layer on the first conductive layer and the first dielectric layer so as to overlap with the plurality of electrodes.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005326358A JP5004459B2 (en) | 2004-12-03 | 2005-11-10 | Method for manufacturing semiconductor device |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004351752 | 2004-12-03 | ||
JP2004351752 | 2004-12-03 | ||
JP2005326358A JP5004459B2 (en) | 2004-12-03 | 2005-11-10 | Method for manufacturing semiconductor device |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2006186320A JP2006186320A (en) | 2006-07-13 |
JP2006186320A5 true JP2006186320A5 (en) | 2008-10-16 |
JP5004459B2 JP5004459B2 (en) | 2012-08-22 |
Family
ID=36739163
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005326358A Expired - Fee Related JP5004459B2 (en) | 2004-12-03 | 2005-11-10 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5004459B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4872591B2 (en) * | 2006-10-18 | 2012-02-08 | 三菱電機株式会社 | TFT substrate, manufacturing method thereof, and display device including the TFT substrate |
TWI711165B (en) | 2014-11-21 | 2020-11-21 | 日商半導體能源研究所股份有限公司 | Semiconductor device and electronic device |
WO2020240329A1 (en) * | 2019-05-30 | 2020-12-03 | 株式会社半導体エネルギー研究所 | Display device and electronic apparatus |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2789293B2 (en) * | 1993-07-14 | 1998-08-20 | 株式会社半導体エネルギー研究所 | Semiconductor device manufacturing method |
JP2001060666A (en) * | 1999-08-23 | 2001-03-06 | Canon Inc | Semiconductor device, manufacture thereof and liquid crystal element formed of the same |
JP3744293B2 (en) * | 2000-01-11 | 2006-02-08 | セイコーエプソン株式会社 | Electro-optical device manufacturing method and electro-optical device |
-
2005
- 2005-11-10 JP JP2005326358A patent/JP5004459B2/en not_active Expired - Fee Related
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2022043102A5 (en) | ||
JP2012015500A5 (en) | ||
JP2016174180A5 (en) | Liquid crystal display device and method for manufacturing liquid crystal display device | |
JP2009033145A5 (en) | ||
JP2016195267A5 (en) | ||
JP2013211537A5 (en) | ||
JP2016006855A5 (en) | ||
JP2015165329A5 (en) | Display device manufacturing method and display device | |
JP2009157354A5 (en) | ||
JP2016139800A5 (en) | Semiconductor device | |
JP2013243372A5 (en) | Semiconductor device, electronic device, and portable information terminal | |
JP2012138574A5 (en) | ||
JP2013211573A5 (en) | ||
JP2012049514A5 (en) | ||
JP2012068627A5 (en) | Method for manufacturing semiconductor device | |
JP2011133876A5 (en) | ||
JP2007088418A5 (en) | ||
JP2009049393A5 (en) | ||
JP2016034040A5 (en) | Display device | |
JP2015156477A5 (en) | Semiconductor device | |
JP2009278072A5 (en) | ||
JP2012182446A5 (en) | ||
JP2012234140A5 (en) | ||
JP2012015498A5 (en) | ||
JP2011151380A5 (en) | Transistor |