JP2006173494A - 配線基板の製造方法 - Google Patents
配線基板の製造方法 Download PDFInfo
- Publication number
- JP2006173494A JP2006173494A JP2004366622A JP2004366622A JP2006173494A JP 2006173494 A JP2006173494 A JP 2006173494A JP 2004366622 A JP2004366622 A JP 2004366622A JP 2004366622 A JP2004366622 A JP 2004366622A JP 2006173494 A JP2006173494 A JP 2006173494A
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- wiring
- electrode layer
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- wiring board
- layer
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- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
【解決手段】第1の電極層上に形成された誘電体層と、当該誘電体層上に形成された第2の電極層とを有するキャパシタと、前記第1の電極層または前記第2の電極層と接続される、前記キャパシタを貫通するように形成された複数のビア配線と、を有し、前記ビア配線が貫通する複数の開口部がそれぞれ形成された、前記第1の電極層、前記誘電体層、および前記第2の電極層を形成する工程と、前記開口部を絶縁層で埋設する工程と、当該開口部に埋設された当該絶縁層を貫通するビアホールを形成する工程と、当該ビアホールに前記ビア配線を形成する工程と、を有し、前記第1の電極層に形成された第1の開口部の開口径は、前記ビアホールの加工径より小さく、前記第1の電極層に形成された第2の開口部の開口径は当該加工径より大きいことを特徴とする配線基板の製造方法。
【選択図】図1
Description
100,100A 配線基板
200 キャパシタ
201 下部電極層
202 誘電体層
203 上部電極層
204 コア基板
205 支持体
206,301,401,501,601 絶縁層
302,502,502A,502B,602 ビア配線
303,304,503,603 パターン配線
305,604 ソルダーレジスト層
306,605 メッキ層
606 ソルダーボール
H1,H2,H3,H4,H5,H6,h1,h2 開口部
d1,d2,d3,d4,d5,d6 開口径
Claims (12)
- 第1の電極層と、当該第1の電極層上に形成された誘電体層と、当該誘電体層上に形成された第2の電極層とを有するキャパシタと、
前記第1の電極層または前記第2の電極層と接続される、前記キャパシタを貫通するように形成された複数のビア配線と、を有する、半導体チップが接続される配線基板の製造方法であって、
前記ビア配線が貫通する複数の開口部がそれぞれ形成された、前記第1の電極層、前記誘電体層、および前記第2の電極層を形成する工程と、
前記開口部を絶縁層で埋設する工程と、
当該開口部に埋設された当該絶縁層を貫通するビアホールを形成する工程と、
当該ビアホールに前記ビア配線を形成する工程と、を有し、
前記第1の電極層に形成された第1の開口部の開口径は、前記ビアホールの加工径より小さく、前記第1の電極層に形成された第2の開口部の開口径は当該加工径より大きいことを特徴とする配線基板の製造方法。 - 前記第2の電極層に形成された前記開口部は、前記加工径より大きいことを特徴とする請求項1記載の配線基板の製造方法。
- 前記誘電体層に形成された前記開口部は、前記第1の開口部より大きいことを特徴とする請求項1または2記載の配線基板の製造方法。
- 前記第1の電極層の前記第2の開口部を貫通するビア配線は、前記第2の電極層に電気的に接続されるように形成されることを特徴とする請求項1乃至3のうち、いずれか1項記載の配線基板の製造方法。
- 前記キャパシタの第1の電極層側には、前記ビア配線に接続される下層ビア配線を含む下層配線構造が形成されていることを特徴とする請求項1乃至4のうち、いずれか1項記載の配線基板の製造方法。
- 前記キャパシタの前記第2の電極層側には、前記ビア配線に接続される上層ビア配線を含む上層配線構造が形成されることを特徴とする請求項1乃至5のうち、いずれか1項記載の配線基板の製造方法。
- 前記ビア配線は、前記半導体チップの電源ラインまたは接地ラインに接続されることを特徴とする、請求項1乃至6のうち、いずれか1項記載の配線基板の製造方法。
- 前記キャパシタは、当該キャパシタを支持する支持体上に形成され、当該キャパシタ形成後に当該支持体が除去されることを特徴とする請求項1乃至7のうち、いずれか1項記載の配線基板の形成方法。
- 前記キャパシタと前記支持体の間には前記キャパシタを支持するコア基板が形成されることを特徴とする請求項8記載の配線基板の製造方法。
- 前記絶縁層に形成される前記ビアホールは、前記コア基板を貫通するように形成されることを特徴とする請求項9記載の配線基板の形成方法。
- 前記第1の電極層が前記支持体に接するように前記支持体上に前記キャパシタが形成された後、前記支持体層が除去されることを特徴とする請求項8記載の配線基板の製造方法。
- 前記誘電体層は、Ta2O5,STO,BST,PZT,または、BTOよりなることを特徴とする請求項1乃至11のうち、いずれか1項記載の配線基板の製造方法。
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KR20150081155A (ko) * | 2014-01-03 | 2015-07-13 | 삼성전기주식회사 | 패키지 기판, 패키지 기판 제조 방법 및 이를 이용한 반도체 패키지 |
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