JP2005332973A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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Abstract
【解決手段】 本発明の半導体装置は、基板、基板上に実装された第1の半導体チップ、その上に積層された内蔵半導体パッケージ、およびこれらを覆う第1のモールド樹脂を備える。この内蔵半導体パッケージは、ダイパッドに実装された少なくとも1つの第2の半導体チップと、複数の端子と電気的に接続され、上面に配設された接続領域およびこれに対向する下面に配設された支持領域を含む複数のリードフレームと、接続領域が露出され、支持領域が覆われるように樹脂モールドする第2のモールド樹脂と、を有する。さらに接続領域は、第2のモールド樹脂のパッケージ表面より下方に位置する。
【選択図】図1
Description
以下、添付図面を参照しながら、本発明に係る半導体装置の実施の形態を説明する。各実施の形態の説明において、理解を容易にするために方向を表す用語(例えば、「上側」、「下側」、「上面」、および「下面」など)を適宜用いるが、これは説明のためのものであって、これらの用語は本発明を限定するものでない。
また、第2の半導体チップ36は、内蔵半導体パッケージ30内に樹脂モールドされた後に第1の半導体チップ18上に積層されるので、複数の半導体チップを直接的に積層する従来式の半導体装置と比較して、半導体チップのチップサイズに対する制約がなく、設計の自由度が増大する。
さらに、本発明の半導体装置1によれば、複数の半導体チップ18,36を積層することにより実装面に平行な水平方向のパッケージサイズを低減するとともに、接続領域42を第2のモールド樹脂46のパッケージ表面50より下方に配置することにより垂直方向の厚みを薄くすることができる。
後述するが、リードフレーム38の接続領域42に対向する支持領域44が第2のモールド樹脂46により支持されているため、接続領域42におけるワイヤボンディングが容易となる。
図5に示すフローチャートのステップST10において、図6に示すダイパッド34上に第2の半導体チップ(例えば、メモリIC)36を実装する(なお、図6に示す内蔵半導体パッケージ30は、図1および図2(a)に示す内蔵半導体パッケージ30に比して、上下反転していることに留意されたい。)。
ステップST12において、メモリIC36の各端子とこれに対応するリードフレーム38を、金線40を用いてワイヤボンディング方式により電気的に接続する。
そしてステップST14において、リードフレーム38の接続領域42が露出され、支持領域44が覆われるように、ダイパッド34、メモリIC36、およびリードフレーム38を樹脂封止する。
こうして完成された内蔵半導体パッケージ30は、ステップST16において、電気的動作テストが行われ、不具合品は確実に排除される。
ステップST20において、図2(b)および図3に示すように、配線基板14の上側主面16には、第1の半導体チップ18および内臓半導体パッケージ30のために、それぞれ複数のボンディングパッド20,32を設け、その下側主面26には外部基板(図示せず)に実装するための格子上に配置された複数の外部接続用ランド(図示せず)を設ける。また、必要に応じて、半田ボール28を外部接続用ランドに接合する。
ステップST22では、第1の半導体チップ(例えば、ロジックIC)18を配線基板14の上側主面16に実装する。
続けてステップST24において、ロジックIC18の端子22とボンディングパッド20を、金線24を用いてワイヤボンディングする。上述のように、ロジックIC18と配線基板14との電気的接続をフリップチップ方式により実現することもできる。
さらに、ステップST26において、こうしてアセンブリされた基板半導体パッケージ10の電気的動作テストが行われ、不具合品が除去される。
ステップST32では、図1および図3に示すように、各リードフレーム38の接続領域42と配線基板14のボンディングパッド32とが金線ワイヤ48を用いて電気的に接続される。このとき、各リードフレーム38の接続領域42の対向する支持領域44が第2のモールド樹脂46により確実に支持されているので、容易にワイヤボンディングすることができる。換言すると、支持領域44が支持されていなければ、各リードフレーム38は、ワイヤボンディング時にワイヤボンダから加わる力に耐えられず、折れ曲がり、信頼性の高いワイヤボンディング接合が得られない。
ステップST34においては、第1の半導体チップ18および内蔵半導体パッケージ30の全体が樹脂モールドされる(第1のモールド樹脂12)。
最後に、ステップST36で、完成された半導体装置1の最終的な電気的動作テストが行われる。
図7を参照しながら、本発明に係る半導体装置の実施の形態2について以下に説明する。実施の形態2の半導体装置1は、内蔵半導体パッケージのダイパッドの上面および下面の両方に少なくとも1つの半導体チップを実装する点を除いて、実施の形態1の半導体装置1と同様の構成を有するので、重複する部分に関する詳細な説明を省略する。
図8を参照しながら、本発明に係る半導体装置の実施の形態3について以下に説明する。実施の形態3の半導体装置1は、内蔵半導体パッケージのダイパッドに実装された第2の半導体チップの上に、さらに別の第3の半導体チップを積層した点を除いて、実施の形態1の半導体装置1と同様の構成を有するので、重複する部分に関する詳細な説明を省略する。
図9を参照しながら、本発明に係る半導体装置の実施の形態4について以下に説明する。実施の形態4の半導体装置1は、基板半導体パッケージの第1の半導体チップの上に別の第4の半導体チップを直接的に積層した点を除いて、実施の形態1の半導体装置1と同様の構成を有するので、重複する部分に関する詳細な説明を省略する。
図10を参照しながら、本発明に係る半導体装置の実施の形態5について以下に説明する。実施の形態5の半導体装置1は、複数のリードフレームが内蔵半導体パッケージの4つの辺から延び、配線基板が上側主面の4つの辺に沿って内蔵半導体パッケージのための複数のボンディングパッドを有する点を除き、実施の形態1の半導体装置1と同様の構成を有するので、重複する部分に関する詳細な説明を省略する。
Claims (8)
- 基板、該基板上に実装された第1の半導体チップ、該第1の半導体チップ上に積層された内蔵半導体パッケージ、および該第1の半導体チップと該内蔵半導体パッケージを覆う第1のモールド樹脂を備えた半導体装置において、
前記内蔵半導体パッケージは、
複数の端子を含み、ダイパッドに実装された少なくとも1つの第2の半導体チップと、
前記複数の端子と電気的に接続され、上面に配設された接続領域およびこれに対向する下面に配設された支持領域を含む複数のリードフレームと、
前記接続領域が露出され、前記支持領域が覆われるように、前記ダイパッド、前記第2の半導体チップ、および前記リードフレームを覆う第2のモールド樹脂と、を有し、
前記リードフレームの前記接続領域は、前記内蔵半導体パッケージの前記第2のモールド樹脂のパッケージ表面より下方に位置することを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記リードフレームの前記接続領域が、ワイヤボンディング方式により前記基板に電気的に接続されることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1の半導体チップは、ワイヤボンディング方式またはフリップチップ方式により前記基板に電気的に接続されることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記内蔵半導体パッケージは、前記ダイパッドの上面および下面のいずれか一方、または両方に実装される前記少なくとも1つの第2の半導体チップを含むことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記内蔵半導体パッケージは、前記第2の半導体チップの上に積層された少なくとも1つの第3の半導体チップをさらに含むことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記内蔵半導体パッケージは、互いに対向する2組の辺を含む平面形状を有し、
前記複数のリードフレームは、前記内蔵半導体パッケージのいずれか一方または両方の組の前記辺から延びることを特徴とする半導体装置。 - 半導体装置に内蔵される内蔵半導体パッケージであって、
複数の端子を含み、ダイパッドに実装された少なくとも1つの第2の半導体チップと、
前記複数の端子と電気的に接続され、上面に配設された接続領域およびこれに対向する下面に配設された支持領域を含む複数のリードフレームと、
前記接続領域が露出され、前記支持領域が覆われるように、前記ダイパッド、前記第2の半導体チップ、および前記リードフレームを覆う第2のモールド樹脂と、を有し、
前記リードフレームの前記接続領域は、前記内蔵半導体パッケージの前記第2のモールド樹脂のパッケージ表面より下方に位置することを特徴とする内蔵半導体パッケージ。 - 半導体装置の製造方法であって、
第1の半導体チップを基板上に実装するステップと、
請求項7に記載された内蔵半導体パッケージの電気的動作テストを行うステップと、
前記内蔵半導体パッケージを前記第1の半導体チップ上に積層するステップと、
前記リードフレームの前記接続領域を前記基板に電気的に接続するステップと、
前記第1の半導体チップと前記内蔵半導体パッケージを覆うように樹脂モールドするステップと、を有することを特徴とする半導体装置の製造方法。
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JP2004149912A JP4455158B2 (ja) | 2004-05-20 | 2004-05-20 | 半導体装置 |
US11/132,292 US7193331B2 (en) | 2004-05-20 | 2005-05-19 | Semiconductor device and manufacturing process thereof |
US11/685,801 US20070161129A1 (en) | 2004-05-20 | 2007-03-14 | Semiconductor device and manufacturing process thereof |
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US7852439B2 (en) | 2007-03-19 | 2010-12-14 | Fujitsu Limited | Multi-layer display element and manufacturing method for the same |
CN112614816A (zh) * | 2019-10-04 | 2021-04-06 | 爱思开海力士有限公司 | 使用引线的半导体装置和层叠半导体封装 |
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JP2007123454A (ja) * | 2005-10-27 | 2007-05-17 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US7420206B2 (en) | 2006-07-12 | 2008-09-02 | Genusion Inc. | Interposer, semiconductor chip mounted sub-board, and semiconductor package |
JP5252007B2 (ja) * | 2011-03-08 | 2013-07-31 | 株式会社村田製作所 | 電子部品の製造方法 |
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EP0595021A1 (en) | 1992-10-28 | 1994-05-04 | International Business Machines Corporation | Improved lead frame package for electronic devices |
JP4033968B2 (ja) | 1998-03-31 | 2008-01-16 | 新日鉄マテリアルズ株式会社 | 複数チップ混載型半導体装置 |
JP3955712B2 (ja) * | 2000-03-03 | 2007-08-08 | 株式会社ルネサステクノロジ | 半導体装置 |
KR100583494B1 (ko) * | 2000-03-25 | 2006-05-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
JP2002057253A (ja) * | 2000-08-10 | 2002-02-22 | Nec Corp | 半導体装置およびその製造方法 |
JP3683179B2 (ja) * | 2000-12-26 | 2005-08-17 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
JP2003017646A (ja) * | 2001-06-29 | 2003-01-17 | Matsushita Electric Ind Co Ltd | 樹脂封止型半導体装置およびその製造方法 |
JP2003273317A (ja) * | 2002-03-19 | 2003-09-26 | Nec Electronics Corp | 半導体装置及びその製造方法 |
US6825064B2 (en) * | 2002-09-30 | 2004-11-30 | Ultratera Corporation | Multi-chip semiconductor package and fabrication method thereof |
US6850020B1 (en) * | 2003-09-26 | 2005-02-01 | Red Devil Equipment Company | Multizone clamping system for paint mixer |
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Cited By (2)
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US7852439B2 (en) | 2007-03-19 | 2010-12-14 | Fujitsu Limited | Multi-layer display element and manufacturing method for the same |
CN112614816A (zh) * | 2019-10-04 | 2021-04-06 | 爱思开海力士有限公司 | 使用引线的半导体装置和层叠半导体封装 |
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US20070161129A1 (en) | 2007-07-12 |
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