JP2005317729A - Connection terminal, semiconductor package using the same, and method for manufacturing semiconductor package - Google Patents
Connection terminal, semiconductor package using the same, and method for manufacturing semiconductor package Download PDFInfo
- Publication number
- JP2005317729A JP2005317729A JP2004133304A JP2004133304A JP2005317729A JP 2005317729 A JP2005317729 A JP 2005317729A JP 2004133304 A JP2004133304 A JP 2004133304A JP 2004133304 A JP2004133304 A JP 2004133304A JP 2005317729 A JP2005317729 A JP 2005317729A
- Authority
- JP
- Japan
- Prior art keywords
- plating film
- semiconductor package
- connection terminal
- electroless
- wiring conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
本発明は、接続端子とその接続端子を用いた半導体パッケージ及び半導体パッケージの製造方法に関する。 The present invention relates to a connection terminal, a semiconductor package using the connection terminal, and a method for manufacturing the semiconductor package.
電子部品を搭載するプリント配線板や半導体を直接搭載する半導体搭載用基板は、近年高密度化が進んでおり、実装方法も高密度化に対応してきており、配線板のスルーホールに電子部品の端子ピンを挿入して、はんだで固定する実装方法から、配線板の表面層の端子にはんだで固定する表面実装方法に変わってきている。 Printed wiring boards on which electronic components are mounted and semiconductor mounting boards on which semiconductors are directly mounted have been increasing in density in recent years, and mounting methods have also been adapted to high density. There is a change from a mounting method in which terminal pins are inserted and fixed with solder to a surface mounting method in which the pins on the surface layer of the wiring board are fixed with solder.
また、表面実装用の電子部品でも、はんだ接続用のリード端子を平行した２列に形成したデュアルインラインパッケージ（以下、ＤＩＰという。）や、正方形のパッケージの４辺にリード端子を設けたクワッドフラットパッケージ（以下、ＱＦＰという。）から、パッケージの裏面に格子状に配列したはんだボールで接続するボールグリッドアレイ（以下、ＢＧＡという。）になってきている。 In addition, even for surface mount electronic components, a quad flat with lead terminals provided on four sides of a dual in-line package (hereinafter referred to as DIP) in which lead terminals for solder connection are formed in two parallel rows, or a square package. The package (hereinafter referred to as QFP) has become a ball grid array (hereinafter referred to as BGA) connected by solder balls arranged in a lattice pattern on the back surface of the package.
このＢＧＡのはんだボールが接続した端子構造は、導体端子上にニッケルめっき皮膜、金めっき皮膜が順次形成されており、その上にはんだボールが接続されている。ここで使用されているはんだボールは、錫と鉛の割合が６：４である共晶はんだボールである。また、下地のニッケルの上に無電解パラジウムめっき皮膜、置換金めっき被膜、無電解金めっき被膜を順に形成するめっき方法は既に公知となっている（例えば、特許文献１参照）。 In the terminal structure in which the BGA solder balls are connected, a nickel plating film and a gold plating film are sequentially formed on the conductor terminals, and the solder balls are connected thereon. The solder balls used here are eutectic solder balls in which the ratio of tin and lead is 6: 4. Further, a plating method for forming an electroless palladium plating film, a displacement gold plating film, and an electroless gold plating film in this order on the underlying nickel is already known (see, for example, Patent Document 1).
ところで、従来の共晶はんだボールが接続した端子構造では、はんだボールの接続後の熱処理によって、接続信頼性が著しく低下することがあるという課題がある。このはんだボールの接続不良には、はんだボールそのものが破壊する場合と、はんだボールとはんだボール接続用端子の界面が剥離する場合とがあり、はんだボールそのものが破壊する場合は、かなり大きい外力が加わらなければ起こらず、通常の使用状態での接続不良は、殆どが、はんだボールとはんだボール接続用端子の界面が剥離することによって起こっているという課題があった。また、特許文献１に記載されている様に、従来は下地ニッケルが一般的であり、上記課題の解決には至らなかった。
本発明は、下地ニッケルがなくても熱処理後の接続信頼性に優れた、接続端子とその接続端子を用いた半導体パッケージ及び半導体パッケージの製造方法を提供することを目的とする。
By the way, in the conventional terminal structure to which the eutectic solder balls are connected, there is a problem that the connection reliability may be significantly lowered by the heat treatment after the solder balls are connected. There are cases where the solder ball itself breaks down and the interface between the solder ball and the solder ball connecting terminal peels off, and when the solder ball itself breaks down, a considerable external force is applied. Otherwise, there is a problem that the connection failure in the normal use state is mostly caused by peeling of the interface between the solder ball and the solder ball connection terminal. Further, as described in Patent Document 1, conventionally, nickel as a base has been generally used, and the above problem has not been solved.
An object of the present invention is to provide a connection terminal, a semiconductor package using the connection terminal, and a method for manufacturing the semiconductor package, which are excellent in connection reliability after heat treatment even without a base nickel.
本発明は、以下のことを特徴とする。
（１）配線導体の表面に無電解パラジウムめっき皮膜及び無電解金めっき被膜が順に形成され、その上にはんだボールが溶着された接続端子。
（２）無電解パラジウムめっき皮膜が、９０重量％以上の純度のパラジウムから成る（１）に記載の接続端子。
（３）配線導体の表面に無電解パラジウムめっき皮膜及び無電解金めっき被膜が順に形成され、その上にはんだボールが溶着された接続端子と、該配線導体を支持する基板と、半導体チップと、該半導体チップと該配線導体を接続する接続導体とから成る半導体パッケージ。
（４）無電解パラジウムめっき皮膜が、９０重量％以上の純度のパラジウムから成る（３）に記載の半導体パッケージ。
（５）基板の表面に配線導体を形成する工程と、該配線導体の表面に無電解パラジウムめっき皮膜及び無電解金めっき被膜を順に形成し、その上にはんだボールを溶着し接続端子を形成する工程と、該接続端子のはんだボールの上に半導体チップを搭載する工程と、半導体チップと配線導体を接続する接続導体を形成する工程とを含んで成る半導体パッケージの製造方法。
The present invention is characterized by the following.
(1) A connection terminal in which an electroless palladium plating film and an electroless gold plating film are sequentially formed on the surface of a wiring conductor, and solder balls are welded thereon.
(2) The connection terminal according to (1), wherein the electroless palladium plating film is made of palladium having a purity of 90% by weight or more.
(3) A connection terminal in which an electroless palladium plating film and an electroless gold plating film are sequentially formed on the surface of the wiring conductor, and solder balls are deposited thereon, a substrate that supports the wiring conductor, a semiconductor chip, A semiconductor package comprising the semiconductor chip and a connection conductor for connecting the wiring conductor.
(4) The semiconductor package according to (3), wherein the electroless palladium plating film is made of palladium having a purity of 90% by weight or more.
(5) A step of forming a wiring conductor on the surface of the substrate, an electroless palladium plating film and an electroless gold plating film are sequentially formed on the surface of the wiring conductor, and solder balls are welded thereon to form connection terminals. A method for manufacturing a semiconductor package, comprising: a step; a step of mounting a semiconductor chip on a solder ball of the connection terminal; and a step of forming a connection conductor connecting the semiconductor chip and a wiring conductor.
以上説明したとおり、本発明によって、熱処理後の接続信頼性に優れた、接続端子とその接続端子を用いた半導体パッケージ並びに半導体パッケージの製造方法を提供することができる。 As described above, according to the present invention, it is possible to provide a connection terminal, a semiconductor package using the connection terminal, and a method for manufacturing the semiconductor package, which are excellent in connection reliability after heat treatment.
本発明のはんだボールが接続した端子構造は、配線導体の端子上に、無電解パラジウムめっき皮膜、無電解金めっき皮膜が順に形成されており、その上にはんだボールが接続している構造であることを特徴とする。 The terminal structure to which the solder ball of the present invention is connected is a structure in which an electroless palladium plating film and an electroless gold plating film are sequentially formed on the terminal of the wiring conductor, and the solder ball is connected thereto. It is characterized by that.
配線導体としては、銅、銀、金、タングステン、アルミニウム、これら各々の合金等から成る群から選ばれる少なくとも１種類以上のものを材料として用いることができる。それらの中でも、工業上、価格上の点で銅がより好ましい。 As the wiring conductor, at least one kind selected from the group consisting of copper, silver, gold, tungsten, aluminum, alloys of these, and the like can be used as a material. Among these, copper is more preferable in terms of industry and price.
無電解パラジウムめっきは、めっき液中のパラジウムイオンを還元剤の働きによってニッケル表面にパラジウムを析出させたものであり、還元剤に蟻酸化合物を使用すると無電解パラジウムめっき皮膜の純度が９９重量％以上になるので、接続の信頼性が高く好ましく、また、還元剤に燐含有化合物、ホウ素含有化合物を使用するとめっき皮膜がパラジウム−燐、パラジウム−ホウ素合金になり、パラジウムの純度が９０重量％以上になるが、はんだボール接続信頼性は問題ない。このパラジウムの純度は、９０重量％以上の純度のパラジウムであれば良い。この無電解パラジウムめっき皮膜の膜厚は、５μｍ以下であることが好ましく、０．０１〜０．３μｍであることがより好ましい。１μｍを越えると、効果がそれ以上に向上せず、経済的でないので好ましくない。下限値は特に存在しないが、広く一般に用いられる蛍光X線測定法の測定限界が０．０１μｍであることを考慮すると、実用上は０．０１μｍ以上であることが好ましい。 In electroless palladium plating, palladium ions in the plating solution are deposited on the nickel surface by the action of the reducing agent. When a formic acid compound is used as the reducing agent, the purity of the electroless palladium plating film is 99% by weight or more. Therefore, the connection reliability is preferably high, and when a phosphorus-containing compound or a boron-containing compound is used as the reducing agent, the plating film becomes palladium-phosphorus or palladium-boron alloy, and the purity of palladium is 90% by weight or more. However, the solder ball connection reliability is not a problem. The purity of this palladium may be palladium with a purity of 90% by weight or more. The film thickness of the electroless palladium plating film is preferably 5 μm or less, and more preferably 0.01 to 0.3 μm. If it exceeds 1 μm, the effect is not improved further and it is not economical, which is not preferable. Although there is no lower limit in particular, it is preferably 0.01 μm or more in practical use considering that the measurement limit of a widely used fluorescent X-ray measurement method is 0.01 μm.
無電解金めっきのうち、置換型無電解金めっきは、下地のニッケルと溶液中の金イオンとの置換反応によってニッケル表面に金皮膜を形成するものであり、めっき液には、シアン化合物を含むものと含まないものがあるが、いずれのめっき液でも使用できる。さらに必要に応じ還元型の無電解金めっき皮膜を形成してもよい。この無電解金めっき皮膜は、９９重量％以上の純度の金であることが好ましく、９９重量％未満であれば、接続の信頼性が低下する場合もある。さらに、この無電解金めっき皮膜の純度は、９９．５重量％以上であることがより好ましい。無電解めっき皮膜の膜厚は、０．００５〜３μｍであることが好ましく、０．００５μｍ未満では、めっきの効果がなく接続の信頼性が向上せず、３μｍを越えると、効果がそれ以上に向上せず、経済的でないので好ましくない。さらには、この無電解金めっき皮膜の厚さは、０．００５〜０．５μｍの範囲であることがより好ましい。 Among electroless gold plating, substitutional electroless gold plating forms a gold film on the nickel surface by a substitution reaction between the underlying nickel and gold ions in the solution, and the plating solution contains a cyanide compound. Some of them are not included, but any plating solution can be used. Further, if necessary, a reduced electroless gold plating film may be formed. The electroless gold plating film is preferably gold having a purity of 99% by weight or more. If the electroless gold plating film is less than 99% by weight, connection reliability may be lowered. Furthermore, the purity of the electroless gold plating film is more preferably 99.5% by weight or more. The film thickness of the electroless plating film is preferably 0.005 to 3 μm. If the thickness is less than 0.005 μm, the plating effect is not improved and the connection reliability is not improved. It is not preferable because it does not improve and is not economical. Furthermore, the thickness of the electroless gold plating film is more preferably in the range of 0.005 to 0.5 μm.
はんだボール接続用端子の素材には、銅、タングステン、モリブデン、これらの合金等から成る群から選ばれる少なくとも１種類以上のものを材料として用いることができる。鉛を含まないはんだボール接続用端子の下地である基材の種類は、セラミック、半導体、樹脂基板等で、この樹脂基板には、フェノール、エポキシ、ポリイミド等のものが使用でき、さらに、剛性の強い板状の基材、柔軟なフレキシブルな基材のいずれも用いることができる。この鉛を含まないはんだボールが接続した端子構造を有する半導体搭載用基板には、ＣＳＰ、ＢＧＡ、ＭＣＭ、配線板、および半導体チップの他、はんだバンプを有するＣＳＰ、ＢＧＡ、ＭＣＭ、配線板、および半導体チップがある。 As a material for the solder ball connection terminal, at least one or more selected from the group consisting of copper, tungsten, molybdenum, alloys thereof, and the like can be used. The type of base material that is the base of the solder ball connection terminal that does not contain lead is ceramic, semiconductor, resin substrate, etc. This resin substrate can be phenol, epoxy, polyimide, etc. Either a strong plate-like substrate or a flexible flexible substrate can be used. In addition to CSP, BGA, MCM, wiring board, and semiconductor chip, CSP, BGA, MCM, wiring board, and CSP, BGA, MCM, wiring board, and semiconductor chip are included in the semiconductor mounting substrate having a terminal structure to which solder balls not containing lead are connected There is a semiconductor chip.
以下、本発明の好適な実施例について説明する。
実施例１
Hereinafter, preferred embodiments of the present invention will be described.
Example 1
銅張り積層板であるＭＣＬ−Ｅ−６７（日立化成工業株式会社製、商品名）に孔をあけ、スルーホールめっきを行ない、エッチングレジストを形成し、不要な銅をエッチング除去し、不要な箇所にめっきを析出させないように、ソルダーレジストを兼ねためっきレジストを形成した後、以下の工程によりはんだボール接続用端子を形成した。
工程１：（前処理）
上記基板を、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／ｌの過硫酸アンモニウム溶液に１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗する。
工程２：（活性化）
続いて、めっき活性化処理液であるICPアクセラ（奥野製薬工業株式会社製、商品名）に、２５℃で３分間、浸漬処理し、２分間水洗する。
工程3：（無電解パラジウムめっき）
続いて、無電解パラジウムめっき液であるプレシアPDS（奥野製薬工業株式会社製、商品名）に、５０℃で２０分間、浸漬処理する。
工程4：（金めっき）
続いて、金めっき液であるIM-GOLD（日本高純度化学製、商品名）に、８５℃で１５分間、浸漬処理する。
上記方法で作製した半導体搭載用基板のはんだボール接続用端子に、６０重量％錫と４０重量％の共晶はんだボールをリフロー炉で接続させた。
比較例１
MCL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a copper-clad laminate, is perforated, through-hole plating is performed, an etching resist is formed, and unnecessary copper is removed by etching. After forming a plating resist that also serves as a solder resist so as not to cause plating to be deposited on, solder ball connection terminals were formed by the following steps.
Step 1: (Pretreatment)
The substrate was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then immersed in a 100 g / l ammonium persulfate solution for 1 minute. Wash with water for 1 minute, soak in 1% sulfuric acid for 1 minute, and rinse with water for 2 minutes.
Step 2: (Activation)
Subsequently, it is immersed in ICP Axela (trade name, manufactured by Okuno Pharmaceutical Co., Ltd.), which is a plating activation treatment solution, at 25 ° C. for 3 minutes and washed with water for 2 minutes.
Process 3: (Electroless palladium plating)
Subsequently, it is immersed in Precia PDS (trade name, manufactured by Okuno Pharmaceutical Co., Ltd.), which is an electroless palladium plating solution, at 50 ° C. for 20 minutes.
Process 4: (Gold plating)
Subsequently, immersion treatment is performed at 85 ° C. for 15 minutes in IM-GOLD (trade name, manufactured by Nippon Kosei Kagaku), which is a gold plating solution.
60% by weight tin and 40% by weight eutectic solder balls were connected in a reflow furnace to the solder ball connection terminals of the semiconductor mounting substrate produced by the above method.
Comparative Example 1
銅張り積層板であるＭＣＬ−Ｅ−６７（日立化成工業株式会社製、商品名）に孔をあけ、スルーホールめっきを行ない、エッチングレジストを形成し、不要な銅をエッチング除去し、不要な箇所にめっきを析出させないように、ソルダーレジストを兼ねためっきレジストを形成した後、以下の工程によりはんだボール接続用端子を形成した。
工程１：（前処理）
上記基板を、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／ｌの過硫酸アンモニウム溶液に１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗する。
工程２：（活性化）
続いて、めっき活性化処理液であるICPアクセラ（奥野製薬工業株式会社製、商品名）に、２５℃で３分間、浸漬処理し、２分間水洗する。
工程3：（無電解ニッケルめっき）
続いて、無電解ニッケルめっき液であるICPニコロンU（奥野製薬工業株式会社製、商品名）に、８５℃で２０分間、浸漬処理する。
工程4：（金めっき）
続いて、金めっき液であるIM−GOLD（日本高純度化学製、商品名）に、８５℃で１０分間、浸漬処理する。
上記方法で作製した半導体搭載用基板のはんだボール接続用端子に、６０重量％錫と４０重量％の共晶はんだボールをリフロー炉で接続させた。
比較例２
MCL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a copper-clad laminate, is perforated, through-hole plating is performed, an etching resist is formed, and unnecessary copper is removed by etching. After forming a plating resist that also serves as a solder resist so as not to cause plating to be deposited on, solder ball connection terminals were formed by the following steps.
Step 1: (Pretreatment)
The substrate was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then immersed in a 100 g / l ammonium persulfate solution for 1 minute. Wash with water for 1 minute, soak in 1% sulfuric acid for 1 minute, and rinse with water for 2 minutes.
Step 2: (Activation)
Subsequently, it is immersed in ICP Axela (trade name, manufactured by Okuno Pharmaceutical Co., Ltd.), which is a plating activation treatment solution, at 25 ° C. for 3 minutes, and washed with water for 2 minutes.
Process 3: (Electroless nickel plating)
Subsequently, immersion treatment is performed at 85 ° C. for 20 minutes in ICP Nicolon U (trade name, manufactured by Okuno Pharmaceutical Co., Ltd.) which is an electroless nickel plating solution.
Process 4: (Gold plating)
Subsequently, immersion treatment is performed at 85 ° C. for 10 minutes in IM-GOLD (manufactured by Nippon Kosei Chemical Co., Ltd.) which is a gold plating solution.
60% by weight of tin and 40% by weight of eutectic solder balls were connected to the solder ball connection terminals of the semiconductor mounting substrate manufactured by the above method in a reflow furnace.
Comparative Example 2
銅張り積層板であるＭＣＬ−Ｅ−６７（日立化成工業株式会社製、商品名）に孔をあけ、スルーホールめっきを行ない、エッチングレジストを形成し、不要な銅をエッチング除去し、不要な箇所にめっきを析出させないように、ソルダーレジストを兼ねためっきレジストを形成した後、以下の工程によりはんだボール接続用端子を形成した。
工程１：（前処理）
上記基板を、脱脂液Ｚ−２００（株式会社ワールドメタル製、商品名）に、５０℃で３分間浸漬し、２分間水洗し、その後、１００ｇ／ｌの過硫酸アンモニウム溶液に１分間浸漬し、２分間水洗し、１０％の硫酸で１分間浸漬し、２分間水洗する。
工程2：（金めっき）
続いて、金めっき液であるIM-GOLD（日本高純度化学株式会社製、商品名）に、８５℃で１０分間、浸漬処理する。
上記方法で作製した半導体搭載用基板のはんだボール接続用端子に、６０重量％錫と４０重量％の共晶はんだボールをリフロー炉で接続させた。
MCL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a copper-clad laminate, is perforated, through-hole plating is performed, an etching resist is formed, and unnecessary copper is removed by etching. After forming a plating resist that also serves as a solder resist so as not to cause plating to be deposited on, solder ball connection terminals were formed by the following steps.
Step 1: (Pretreatment)
The substrate was immersed in a degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) at 50 ° C. for 3 minutes, washed with water for 2 minutes, and then immersed in a 100 g / l ammonium persulfate solution for 1 minute. Wash with water for 1 minute, soak in 1% sulfuric acid for 1 minute, and rinse with water for 2 minutes.
Process 2: (Gold plating)
Subsequently, immersion treatment is performed at 85 ° C. for 10 minutes in IM-GOLD (trade name, manufactured by Nihon Kojun Kagaku Co., Ltd.) which is a gold plating solution.
60 wt% tin and 40 wt% eutectic solder balls were connected in a reflow furnace to the solder ball connecting terminals of the semiconductor mounting substrate manufactured by the above method.
実施例１と比較例１、２で作製した、はんだボールが接続したＢＧＡを１５０℃、１００時間の熱処理を行った後、はんだボールのシェア（引き剥がし）試験を行った。
（シェア試験）図１に示すように、製作した半導体パッケージ基板を固定し、はんだボールに水平にシェア試験機のシェアツールを当て、約３００μｍ／分の速度で、はんだボールが破壊するかあるいはボールパッドからはんだボールが剥がれるまで力を加える。この速度は、はんだボールのはんだが柔らかく変形を起こしやすいことから、変形をする前に剪断破壊するかあるいはボールパッドから剥がれる程度の速度としてこの速度を選定した。この速度よりも早ければ、はんだボールが剪断破壊するかあるいはボールパッドから剥がれるかの判断は十分に行えるものである。
The BGAs produced in Example 1 and Comparative Examples 1 and 2 were connected to solder balls and heat-treated at 150 ° C. for 100 hours, and then subjected to a shear (peeling) test of the solder balls.
(Share test) As shown in FIG. 1, the manufactured semiconductor package substrate is fixed, the shear tool of the shear tester is applied horizontally to the solder ball, and the solder ball breaks or the ball at a speed of about 300 μm / min. Apply force until the solder balls come off the pads. Since this solder ball is soft and easily deformed, this speed was selected as a speed at which the solder ball was sheared before being deformed or peeled off from the ball pad. If it is faster than this speed, it can be sufficiently judged whether the solder ball is sheared or peeled off from the ball pad.
この結果、実施例１のサンプルでは、全てのはんだボールが、ボール内での剪断による破壊まで耐えることができたが、比較例１のはんだボールは、約９０％の端子において、無電解ニッケルめっきとはんだボールの界面で破壊が発生し、熱処理後の接続信頼性が不良であった。また比較例２のサンプルはめっき後の乾燥にて端子が著しく変色していたためはんだボールシェア試験は行わなかった。 As a result, in the sample of Example 1, all the solder balls were able to withstand the fracture due to the shear in the ball. However, the solder ball of Comparative Example 1 was electroless nickel plated at about 90% of the terminals. Breakage occurred at the interface of the solder balls and the connection reliability after heat treatment was poor. In the sample of Comparative Example 2, the solder ball shear test was not performed because the terminals were remarkably discolored by drying after plating.
１ 基板
２ 配線導体
３ 無電解パラジウムめっき被膜
４ 無電解金めっき被膜
５ はんだボール
６ めっきレジスト
７ シェア試験機のシェアツール
８ 接続端子
９ 半導体チップ
１０ ダイアタッチ
１１ ワイヤボンディング
１２ 封止材
１３ 配線導体
１４ 接続導体
DESCRIPTION OF SYMBOLS 1 Board |
Claims (5)
A step of forming a wiring conductor on the surface of the substrate, a step of sequentially forming an electroless palladium plating film and an electroless gold plating film on the surface of the wiring conductor, and forming a connection terminal by welding solder balls thereon; A method for manufacturing a semiconductor package, comprising: mounting a semiconductor chip on a solder ball of the connection terminal; and forming a connection conductor for connecting the semiconductor chip and a wiring conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004133304A JP2005317729A (en) | 2004-04-28 | 2004-04-28 | Connection terminal, semiconductor package using the same, and method for manufacturing semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004133304A JP2005317729A (en) | 2004-04-28 | 2004-04-28 | Connection terminal, semiconductor package using the same, and method for manufacturing semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2005317729A true JP2005317729A (en) | 2005-11-10 |
Family
ID=35444839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004133304A Pending JP2005317729A (en) | 2004-04-28 | 2004-04-28 | Connection terminal, semiconductor package using the same, and method for manufacturing semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2005317729A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008291348A (en) * | 2007-04-27 | 2008-12-04 | Hitachi Chem Co Ltd | Connecting terminal, semiconductor package using connecting terminal, and method for manufacturing semiconductor package |
| WO2010004856A1 (en) * | 2008-07-08 | 2010-01-14 | 日本高純度化学株式会社 | Catalyst-imparting liquid for palladium plating |
| JP2018059154A (en) * | 2016-10-05 | 2018-04-12 | 小島化学薬品株式会社 | Electroless palladium/gold plating process |
| KR20190008284A (en) | 2016-06-13 | 2019-01-23 | 우에무라 고교 가부시키가이샤 | Film forming method |
| CN115087760A (en) * | 2020-02-18 | 2022-09-20 | 日本高纯度化学株式会社 | Plated laminate |
| KR20220142463A (en) | 2020-02-18 | 2022-10-21 | 니혼 고쥰도가가쿠 가부시키가이샤 | plated laminate |
-
2004
- 2004-04-28 JP JP2004133304A patent/JP2005317729A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008291348A (en) * | 2007-04-27 | 2008-12-04 | Hitachi Chem Co Ltd | Connecting terminal, semiconductor package using connecting terminal, and method for manufacturing semiconductor package |
| US8426742B2 (en) | 2007-04-27 | 2013-04-23 | Hitachi Chemical Company, Ltd. | Connecting terminal, semiconductor package using connecting terminal and method for manufacturing semiconductor package |
| WO2010004856A1 (en) * | 2008-07-08 | 2010-01-14 | 日本高純度化学株式会社 | Catalyst-imparting liquid for palladium plating |
| KR20110028312A (en) | 2008-07-08 | 2011-03-17 | 니혼 고쥰도가가쿠 가부시키가이샤 | Catalyst-imparting liquid for palladium plating |
| JP5567478B2 (en) * | 2008-07-08 | 2014-08-06 | 日本高純度化学株式会社 | Method for producing palladium plating film on copper-based metal and palladium plating film obtained by the production method |
| KR101639084B1 (en) | 2008-07-08 | 2016-07-12 | 니혼 고쥰도가가쿠 가부시키가이샤 | Catalyst-imparting liquid for palladium plating |
| KR20190008284A (en) | 2016-06-13 | 2019-01-23 | 우에무라 고교 가부시키가이샤 | Film forming method |
| US10941493B2 (en) | 2016-06-13 | 2021-03-09 | C. Uyemura & Co., Ltd. | Film formation method |
| WO2018066217A1 (en) * | 2016-10-05 | 2018-04-12 | 小島化学薬品株式会社 | Electroless palladium/gold plating process |
| TWI645071B (en) * | 2016-10-05 | 2018-12-21 | 日商小島化學藥品股份有限公司 | Electroless palladium / gold plating method |
| JP2018059154A (en) * | 2016-10-05 | 2018-04-12 | 小島化学薬品株式会社 | Electroless palladium/gold plating process |
| CN115087760A (en) * | 2020-02-18 | 2022-09-20 | 日本高纯度化学株式会社 | Plated laminate |
| KR20220142463A (en) | 2020-02-18 | 2022-10-21 | 니혼 고쥰도가가쿠 가부시키가이샤 | plated laminate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6669077B1 (en) | High-strength solder joint | |
| KR100688833B1 (en) | Method for plating on printed circuit board and printed circuit board produced therefrom | |
| JP2007031826A (en) | Connection terminal and substrate for mounting semiconductor having the same | |
| JP2009239278A (en) | Substrate for mounting electronic component, and method of manufacturing the same | |
| JP3345529B2 (en) | Wire bonding terminal, method of manufacturing the same, and method of manufacturing semiconductor mounting substrate using the wire bonding terminal | |
| KR20180089547A (en) | Method for obtaining a palladium surface finish for copper wire bonding on printed circuit boards and ic-substratess | |
| US8759986B2 (en) | Substrate structure and method of manufacturing the same | |
| US7982138B2 (en) | Method of nickel-gold plating and printed circuit board | |
| JP2006196648A (en) | Electronic component having external junction electrode and manufacturing method thereof | |
| US20030080092A1 (en) | Rework method for finishing metallurgy on chip carriers | |
| JP2005317729A (en) | Connection terminal, semiconductor package using the same, and method for manufacturing semiconductor package | |
| JP2013012739A (en) | Electric joining terminal structure and method for preparing the same | |
| JP4798451B2 (en) | Wiring board and manufacturing method thereof | |
| JP2000277897A (en) | Terminal for solder-ball connection and its formation method and as manufacture of board for semiconductor mounting | |
| KR100619345B1 (en) | Method for plating on printed circuit board for semi-conductor package and printed circuit board produced therefrom | |
| JP2005054267A (en) | Electroless gold plating method | |
| JP2000252380A (en) | Solder connecting pad and substrate for placing semiconductor using the solder connecting pad | |
| JPH11140659A (en) | Substrate for mounting semiconductor and its production | |
| JP3596335B2 (en) | Semiconductor mounting substrate using wire bonding terminals | |
| JP2008028069A (en) | Substrate with externally bonded electrode, and method for manufacturing the same | |
| JP2002118134A (en) | Connection terminal and semiconductor package using the same as well as manufacturing method thereof | |
| JP4449459B2 (en) | A wire mounting terminal, a manufacturing method thereof, and a semiconductor mounting substrate having the wire bonding terminal. | |
| JPH11140658A (en) | Substrate for mounting semiconductor and its production | |
| JP2001044315A (en) | Terminal for connection with solder ball, method of forming the terminal, substrate for semiconductor package having the same and manufacture of the substrate for semiconductor package | |
| JP2002118135A (en) | Connection terminal and semiconductor package using the same as well as manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070316 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090129 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090205 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20090702 |