JP2005286349A - Bumpless semiconductor device - Google Patents

Bumpless semiconductor device Download PDF

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Publication number
JP2005286349A
JP2005286349A JP2005149542A JP2005149542A JP2005286349A JP 2005286349 A JP2005286349 A JP 2005286349A JP 2005149542 A JP2005149542 A JP 2005149542A JP 2005149542 A JP2005149542 A JP 2005149542A JP 2005286349 A JP2005286349 A JP 2005286349A
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Prior art keywords
chip
conductive particles
bumpless
electrode pad
semiconductor device
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Japanese (ja)
Inventor
Yukio Yamada
幸男 山田
Masayuki Nakamura
雅之 中村
Hiroyuki Hishinuma
啓之 菱沼
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Dexerials Corp
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Sony Chemicals Corp
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Priority to JP2005149542A priority Critical patent/JP2005286349A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bumpless semiconductor device capable of high surely and inexpensively connecting an IC chip with a substrate using flip-chip method, without forming bumps on the IC chip, while suppressing short-circuiting, reducing the connection cost, suppressing concentration of stresses to the connection, and reducing damages given to the IC chip and the substrate, when connecting the IC chip to a circuit board by means of flip-chip method. <P>SOLUTION: A conductive particle 4 is connected by metallic bond with an electrode pad 2 of the bumpless IC chip, equipped with the electrode pad 2 on its surface and a passivation film 3 around the pad 2. A composite particle, having a metal-plated layer on the surface of a resin particle, is employed as the conductive particle 4. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、バンプレス半導体装置に関する。   The present invention relates to a bumpless semiconductor device.

ベアＩＣチップを回路基板にフリップチップ方式で接続する場合、パッシべーション膜で覆われていないスクライブラインでのショートの発生を防止するために、ＩＣチップと回路基板との間を離す必要がある。このため、ＩＣチップに高さ１０μｍ〜８０μｍ程度の接続用のバンプを形成することが広く行われている（図３〜図５）。   When connecting a bare IC chip to a circuit board by a flip chip method, it is necessary to separate the IC chip from the circuit board in order to prevent a short circuit from occurring on a scribe line not covered with a passivation film. . For this reason, a bump for connection having a height of about 10 μm to 80 μm is widely formed on the IC chip (FIGS. 3 to 5).

図３の態様の場合には、スタッドバンプ法により形成された金バンプ３１を有するＩＣチップ３２の当該金バンプ３１と、回路基板３３の接続端子３４とを、導電性粒子３５がバインダー３６中に分散してなる異方性導電接着剤３７（フィルム又はペースト）を介して熱圧着している。また、図４の態様の場合には、スタッドバンプ法により形成された金バンプ４１を有するＩＣチップ４２の当該金バンプ４１と、回路基板４３の接続端子４４とを、絶縁性接着材料４５（フィルム又はペースト）を介して熱圧着している。   In the case of the embodiment of FIG. 3, the conductive particles 35 are placed in the binder 36 between the gold bump 31 of the IC chip 32 having the gold bump 31 formed by the stud bump method and the connection terminal 34 of the circuit board 33. Thermocompression bonding is performed through a dispersed anisotropic conductive adhesive 37 (film or paste). 4, the gold bump 41 of the IC chip 42 having the gold bump 41 formed by the stud bump method and the connection terminal 44 of the circuit board 43 are connected to the insulating adhesive material 45 (film Or thermocompression bonding via a paste).

なお、図３及び図４の態様において、ＩＣチップと回路基板との間の密着力は、バンプ３１（４１）と接続端子３４（４４）とが互いに金属結合していないので、異方性導電接着剤中（絶縁性接着剤中）のバインダー（接着成分）の凝集力に依存している。   3 and 4, the adhesion force between the IC chip and the circuit board is such that the bump 31 (41) and the connection terminal 34 (44) are not metal-bonded to each other. It depends on the cohesive strength of the binder (adhesive component) in the adhesive (in the insulating adhesive).

また、図５の態様の場合には、半田ペースト印刷／リフロ−法等により半田バンプ５１が形成されたＩＣチップ５２の当該半田バンプ５１を、回路基板５３のフラックス処理済み接続端子５４に当接させ、半田の融点以上に加熱することにより半田バンプ５１と接続端子５４とを接続し、ＩＣチップ５２と回路基板５３との間隙をアンダーフィル剤５５で充填している。この場合、アンダーフィル剤５５の充填前に、通常、フラックスを除去する洗浄操作が行われる。   5, the solder bump 51 of the IC chip 52 on which the solder bump 51 is formed by the solder paste printing / reflow method or the like is brought into contact with the flux-treated connection terminal 54 of the circuit board 53. Then, the solder bump 51 and the connection terminal 54 are connected by heating to the melting point or higher of the solder, and the gap between the IC chip 52 and the circuit board 53 is filled with the underfill agent 55. In this case, before the underfill agent 55 is filled, a cleaning operation for removing the flux is usually performed.

しかしながら、図３〜図５の態様の場合、いずれもＩＣチップに加工コストの高いバンプを形成することが前提となっているので、ＩＣチップの形状的な自由度が低下し、しかもＩＣチップと回路基板との間の接続コストを低減することが困難であるという問題がある。   However, in the cases of FIGS. 3 to 5, it is assumed that bumps having high processing costs are formed on the IC chip, so that the degree of freedom of the shape of the IC chip is reduced, and the IC chip There is a problem that it is difficult to reduce the connection cost with the circuit board.

また、図３及び図４の態様において、バンプ３１（４１）と接続端子３４（４４）とは金属結合していないために、ＩＣチップと回路基板との間の密着力は、異方性導電接着剤中（絶縁性接着剤中）のバインダー（接着成分）の凝集力に依存せざるを得ず、異方性導電接着剤を使用する図３の態様の場合は接続信頼性が確保できるが、使用しない図４の態様の場合には接続信頼性が金属結合した場合に比べ低くなるという問題がある。   3 and 4, the bump 31 (41) and the connection terminal 34 (44) are not metal-bonded, so that the adhesion between the IC chip and the circuit board is anisotropically conductive. In the case of the embodiment of FIG. 3 using an anisotropic conductive adhesive, connection reliability can be ensured, depending on the cohesive strength of the binder (adhesive component) in the adhesive (in the insulating adhesive). In the case of the embodiment of FIG. 4 that is not used, there is a problem that the connection reliability is lower than that in the case of metal bonding.

更に、図３の態様の場合、バンプピッチの微細化とバンプサイズの微小化に伴い、バンプ３１と接続端子３４との間に導電性粒子３５を確実に存在せしめるために、異方性導電接着剤３７中の導電性粒子３５の含有割合を増大させると、ショートの発生の危険性が増大するという問題がある。また、導電性粒子３５の入手コストが比較的高価なため、ＩＣチップ３２と回路基板３３との間の接続コストも増大するという問題もある。図４の態様の場合、導電性粒子をバンプ４１と接続端子４４との間に介在させずに、バンプ４１と接続端子４４とをダイレクトに圧接するので、接続部にストレスが集中して接続信頼性が更に低下するという問題がある。また、圧着時の圧力を高くする必要があるので、ＩＣチップや回路基板が比較的大きなダメージを受ける可能性がある。   Further, in the case of the embodiment of FIG. 3, anisotropic conductive bonding is performed in order to ensure that the conductive particles 35 exist between the bumps 31 and the connection terminals 34 as the bump pitch and the bump size are reduced. When the content ratio of the conductive particles 35 in the agent 37 is increased, there is a problem that the risk of occurrence of a short circuit increases. In addition, since the cost of obtaining the conductive particles 35 is relatively high, there is a problem that the connection cost between the IC chip 32 and the circuit board 33 also increases. In the case of the embodiment of FIG. 4, the conductive particles are not interposed between the bumps 41 and the connection terminals 44, and the bumps 41 and the connection terminals 44 are directly pressed against each other. There is a problem that the property further decreases. Further, since it is necessary to increase the pressure at the time of pressure bonding, there is a possibility that the IC chip and the circuit board are relatively damaged.

一方、図５の態様の場合には、半田バンプ５１と接続端子５４とが金属結合しており接続信頼性は比較的十分であるが、金属結合を形成するのに十分なバンプの大きさを確保すると、半田バンプ５１のファインピッチ化が困難となるという問題がある。更に、フラックスＦの洗浄工程及びアンダーフィル剤５５の充填工程が増えるという問題がある。   On the other hand, in the case of the embodiment of FIG. 5, the solder bump 51 and the connection terminal 54 are metal-bonded and the connection reliability is relatively sufficient. However, the bump size sufficient to form the metal bond is sufficient. If secured, there is a problem that it becomes difficult to make the fine pitch of the solder bumps 51. Furthermore, there is a problem that the cleaning process of the flux F and the filling process of the underfill agent 55 are increased.

本発明は、以上の従来の技術の課題を解決しようとするものであり、ベアＩＣチップなどの半導体装置を回路基板にフリップチップ方式で接続する際に、半導体装置にバンプを形成することなく、ショートの抑制、接続コストの低減、接続部へのストレス集中の抑制、及びＩＣチップや回路基板に付加されるダメージの低減を図りつつ、高信頼性且つ低コストでＩＣチップと回路基板とを接続可能とすることを目的とする。   The present invention is intended to solve the above-described problems of the conventional technology, and when a semiconductor device such as a bare IC chip is connected to a circuit board by a flip chip method, without forming bumps on the semiconductor device, Connect IC chip and circuit board with high reliability and low cost while suppressing short circuit, reducing connection cost, reducing stress concentration on connection part, and reducing damage to IC chip and circuit board. The purpose is to make it possible.

本発明者は、ガラス板などの平板に導電性粒子を静電気的にいったん吸着させ、その平板の導電性粒子吸着面を、半導体装置の電極パッド側表面に重ねて超音波圧着することにより、電極パッドにだけ導電性粒子を金属結合させることができることを見出し、本発明を完成させるに至った。   The inventor once electrostatically adsorbs the conductive particles on a flat plate such as a glass plate, and superposes the conductive particle adsorption surface of the flat plate on the electrode pad side surface of the semiconductor device, thereby ultrasonically pressing the electrode. It has been found that the conductive particles can be metal-bonded only to the pad, and the present invention has been completed.

即ち、本発明は、表面に電極パッドが設けられ、電極パッドの周囲にはパッシベーション膜が設けられているバンプレス半導体装置であって、電極パッドに導電性粒子が金属結合により接続されていることを特徴とするバンプレス半導体装置を提供する。   That is, the present invention is a bumpless semiconductor device in which an electrode pad is provided on the surface and a passivation film is provided around the electrode pad, and conductive particles are connected to the electrode pad by a metal bond. A bumpless semiconductor device is provided.

また、本発明は、以下の工程（ａ）及び（ｂ）：
（ａ）平板の片面に導電性粒子を静電気的に吸着させる工程；及び
（ｂ）表面に電極パッドが設けられ、電極パッドの周囲にはパッシベーション膜が設けられているバンプレス半導体装置の電極パッド面に、該平板の導電性粒子吸着面を重ねて超音波圧着することにより、導電性粒子を電極パッドに金属結合させて該平板から電極パッドに転着させる工程
を有することを特徴とするバンプレス半導体装置の製造方法を提供する。 The present invention also includes the following steps (a) and (b):
(A) a step of electrostatically adsorbing conductive particles on one surface of a flat plate; and (b) an electrode pad of a bumpless semiconductor device in which an electrode pad is provided on the surface and a passivation film is provided around the electrode pad. And a conductive particle adsorbing surface of the flat plate is superposed on the surface, and ultrasonic bonding is performed, whereby the conductive particles are metal-bonded to the electrode pad and transferred from the flat plate to the electrode pad. A method for manufacturing a press semiconductor device is provided.

更に、本発明は、このバンプレス半導体装置の接続パッドに金属結合した導電性粒子が回路基板の接続端子に当接するように、該バンプレス半導体装置と回路基板とが絶縁性接着材料で接合されていることを特徴とする接続構造体を提供する。   Further, according to the present invention, the bumpless semiconductor device and the circuit board are bonded with an insulating adhesive material so that the conductive particles metal-bonded to the connection pads of the bumpless semiconductor device are in contact with the connection terminals of the circuit board. A connection structure is provided.

本発明によれば、ＩＣチップなどの半導体装置を回路基板にフリップチップ方式で接続する際に、半導体装置にバンプを形成することなく、ショートの抑制、接続コストの低減、接続部へのストレス集中の抑制、及びＩＣチップや回路基板に付加されるダメージの低減を図りつつ、高信頼性且つ低コストでＩＣチップと回路基板とを接続することができる。   According to the present invention, when a semiconductor device such as an IC chip is connected to a circuit board by a flip chip method, it is possible to suppress a short circuit, reduce connection cost, and concentrate stress on a connection portion without forming bumps on the semiconductor device. It is possible to connect the IC chip and the circuit board with high reliability and low cost while suppressing the damage and reducing the damage applied to the IC chip and the circuit board.

以下、本発明を図面を参照しながら詳細に説明する。   Hereinafter, the present invention will be described in detail with reference to the drawings.

図１は、本発明のバンプレス半導体装置をＩＣチップに適用した例である。このＩＣチップ１の構造は、表面にアルミニウムなどの電極パッド２が設けられ、電極パッド２の周囲には電極パッド２の表面位置レベルよりも高い表面位置レベルのパッシベーション膜３が設けられているバンプレス構造を有する。そして、電極パッド２には、導電性粒子４が金属結合により接続されている。従って、電極パッド２と導電性粒子４との間の接続信頼性は、図３〜図５に示した従来のＩＣチップに形成されたバンプに匹敵するものとなる。しかも、導電性粒子４を電極パッド２に金属結合させる場合、煩雑で高コストの従来のバンプ形成法ではなく、超音波圧着法等の比較的低コストの手法で金属結合させることができる。更に、導電性粒子４として存在しているので、導電性粒子４と回路基板の接続端子（被接続体）との間の接続信頼性も、従来の異方性導電接続法に匹敵するものとなる。   FIG. 1 shows an example in which the bumpless semiconductor device of the present invention is applied to an IC chip. This IC chip 1 has a structure in which an electrode pad 2 such as aluminum is provided on the surface, and a passivation film 3 having a surface position level higher than the surface position level of the electrode pad 2 is provided around the electrode pad 2. It has a press structure. Then, the conductive particles 4 are connected to the electrode pad 2 by metal bonding. Therefore, the connection reliability between the electrode pad 2 and the conductive particles 4 is comparable to the bump formed on the conventional IC chip shown in FIGS. Moreover, when the conductive particles 4 are metal-bonded to the electrode pad 2, they can be metal-bonded by a relatively low-cost method such as an ultrasonic pressure bonding method instead of the complicated and expensive conventional bump forming method. Further, since the conductive particles 4 exist, the connection reliability between the conductive particles 4 and the connection terminals (connected bodies) of the circuit board is comparable to the conventional anisotropic conductive connection method. Become.

本発明において、導電性粒子４としては、半田粒子、ニッケル粒子などの金属粒子や、ベンゾグアナミンなどの樹脂粒子（コア）の表面にニッケルや金等の金属メッキ層が形成された複合粒子を使用することができる。中でも、接続部分に加わる応力を緩和できる樹脂粒子をコアとする複合粒子を使用することが好ましい。   In the present invention, as the conductive particles 4, composite particles in which metal particles such as solder particles and nickel particles or resin particles (core) such as benzoguanamine are formed with a metal plating layer such as nickel or gold are used. be able to. Among these, it is preferable to use composite particles having resin particles as a core that can relieve stress applied to the connection portion.

導電性粒子４の粒径は、金属結合された導電性粒子４の少なくとも一部が、パッシべーション膜３の表面よりも外側に突出する大きさとすることが好ましい。即ち、パッシベーション膜３と電極パッド２との間の表面位置レベルの差よりも大きくすることが好ましい。これにより、スクライブラインにおけるショートの発生を抑制でき、しかも被接続体（回路基板）に対する接続信頼性を向上させることができる。この場合、導電性粒子４の粒径を、電極パッド２に金属結合可能な範囲で、電極パッド２の径よりも大きくしてもよいが、導電性粒子４同士の横方向のショートをより効率的に抑制するために、導電性粒子４の粒径を電極パッド２の径よりも小さくすることが好ましい。具体的には、導電性粒子４の粒径は、金属粒子である場合には好ましくは１〜５０μｍ、より好ましくは３〜４０μｍであり、複合粒子の場合には樹脂粒子の直径が好ましくは１〜５０μｍ、より好ましくは３〜４０μｍであり且つ金属メッキ層の厚みが好ましくは１０ｎｍ〜１μｍ、より好ましくは１５ｎｍ〜１μｍである。   The particle diameter of the conductive particles 4 is preferably set such that at least a part of the metal-bonded conductive particles 4 protrudes outside the surface of the passivation film 3. That is, it is preferable that the difference between the surface position level between the passivation film 3 and the electrode pad 2 is larger. Thereby, generation | occurrence | production of the short in a scribe line can be suppressed, and also the connection reliability with respect to a to-be-connected body (circuit board | substrate) can be improved. In this case, the particle diameter of the conductive particles 4 may be larger than the diameter of the electrode pad 2 within a range in which metal bonding to the electrode pad 2 is possible. Therefore, it is preferable to make the particle diameter of the conductive particles 4 smaller than the diameter of the electrode pad 2. Specifically, the particle size of the conductive particles 4 is preferably 1 to 50 μm, more preferably 3 to 40 μm when the particles are metal particles, and the diameter of the resin particles is preferably 1 when the particles are composite particles. -50 μm, more preferably 3-40 μm, and the thickness of the metal plating layer is preferably 10 nm-1 μm, more preferably 15 nm-1 μm.

また、導電性粒子４の最外層として、好ましくは５ｎｍ〜０．５μｍ厚程度の薄い金メッキ層を形成することが、接触抵抗を低減させる点から好ましい。   Further, it is preferable to form a thin gold plating layer having a thickness of about 5 nm to 0.5 μm as the outermost layer of the conductive particles 4 from the viewpoint of reducing the contact resistance.

なお、図１の態様におけるＩＣチップ１、電極パッド２、パッシベーション膜３の具体的構成としては、それぞれ従来公知のものを採用することができる。   In addition, as a specific configuration of the IC chip 1, the electrode pad 2, and the passivation film 3 in the embodiment of FIG.

次に、本発明のバンプレス半導体装置（ＩＣチップ）の製造方法を工程毎に説明する。   Next, a method for manufacturing a bumpless semiconductor device (IC chip) according to the present invention will be described step by step.

工程（ａ）
図２（ａ）に示すように、まず、ガラス平板などの平板２１の片面に前述した導電性粒子４を静電気的に吸着させる。この場合、工程（ｂ）における超音波圧着時の導電性粒子の転着を効率的に行うために、単層で吸着させることが好ましい。導電性粒子４を静電気的に平板２１に吸着させる手法としては、平板２１の表面をポリエステル布等で擦って静電気をチャージし、その面に導電性粒子４を散布すればよい。吸着しなかった導電性粒子については、平板２１を傾けあるいは裏返し、平板２１に軽く振動を与えることにより除去することができる。 Step (a)
As shown in FIG. 2A, first, the conductive particles 4 described above are electrostatically adsorbed on one side of a flat plate 21 such as a glass flat plate. In this case, in order to efficiently transfer the conductive particles during the ultrasonic pressure bonding in the step (b), it is preferable to adsorb in a single layer. As a method for electrostatically adsorbing the conductive particles 4 to the flat plate 21, the surface of the flat plate 21 may be rubbed with a polyester cloth or the like to charge static electricity, and the conductive particles 4 may be scattered on the surface. The conductive particles that have not been adsorbed can be removed by tilting or turning the flat plate 21 and applying light vibrations to the flat plate 21.

工程（ｂ）
次に、図２（ｂ）に示すように、表面に電極パッド２が設けられ、電極パッド２の周囲にはパッシベーション膜３が設けられているＩＣチップ１の電極パッド面２に、平板２１の導電性粒子吸着面を重ねて超音波圧着する（図２（ｃ））。これにより、導電性粒子４を電極パッド２に金属結合させて該平板２１から電極パッド２に転着させることができる。なお、絶縁膜であるパッシべーション膜３に対しては、導電性粒子４は金属結合しないので転着しない。 Step (b)
Next, as shown in FIG. 2 (b), the electrode pad 2 is provided on the surface, and the passivation film 3 is provided around the electrode pad 2. Ultrasonic pressure bonding is performed with the conductive particle adsorption surfaces overlapped (FIG. 2C). Thereby, the conductive particles 4 can be metal-bonded to the electrode pad 2 and transferred from the flat plate 21 to the electrode pad 2. The conductive particles 4 are not transferred to the passivation film 3 that is an insulating film because the conductive particles 4 are not metal-bonded.

超音波圧着条件としては、例えば１０〜１００ＫＨｚの周波数を１〜１００ＭＰａ（電極パッド当たり）の圧力で、０．１〜２０秒、印可する条件が挙げられる。使用できる具体的な装置としては、Ｕｌｔｒａｓｏｎｉｃ Ｍｉｃｒｏ Ｗｅｌｄｉｎｇ Ｓｙｓｔｅｍ（ＳＨ４０ＭＰ、ＵＬＴＡＸ社製）が挙げられる。   Examples of the ultrasonic pressure bonding condition include a condition in which a frequency of 10 to 100 KHz is applied at a pressure of 1 to 100 MPa (per electrode pad) for 0.1 to 20 seconds. Specific devices that can be used include Ultrasonic Micro Welding System (SH40MP, manufactured by ULTAX).

工程（ｃ）
必要に応じて、パッシべーション膜３に付着した導電性粒子４を、市販の粘着テープに転着させるか、あるいはエアブロー処理により吹き飛ばすことにより除去すると、図２（ｄ）に示すバンプレス半導体装置（ＩＣチップ）１が得られる。 Step (c)
If necessary, the conductive particles 4 adhering to the passivation film 3 are removed by transferring them onto a commercially available adhesive tape or by blowing them off by an air blowing process, so that the bumpless semiconductor device shown in FIG. (IC chip) 1 is obtained.

図２（ｄ）に示したバンプレス半導体装置（ＩＣチップ）１は高い接続信頼性を有する接続構造体を与えることができる。具体的には、接続パッド２に金属結合した導電性粒子４が回路基板５の接続端子６に当接するように、バンプレス半導体装置１と回路基板５とを公知のフィルム状又はペースト状の絶縁性接着材料７で接合された接続構造体（図２（ｅ））を挙げることができる。   The bumpless semiconductor device (IC chip) 1 shown in FIG. 2D can provide a connection structure having high connection reliability. Specifically, the bumpless semiconductor device 1 and the circuit board 5 are insulated in a known film or paste form so that the conductive particles 4 that are metal-bonded to the connection pads 2 come into contact with the connection terminals 6 of the circuit board 5. A connection structure (FIG. 2 (e)) bonded with the adhesive material 7 can be cited.

以下、本発明を実施例により具体的に説明する。   Hereinafter, the present invention will be specifically described by way of examples.

実施例１〜８及び比較例１〜４
ガラス平板の片面をポリエステル布で擦った後、その面に表１の導電性粒子を散布して吸着させ、余分の導電性粒子は、ガラス平板を傾けて軽く振動させることにより除去した。但し、実施例６は、導電性粒子としてＮｉコアの表面にＡｕメッキ層が設けられた金属粒子を使用したが、その他の実施例及び比較例では、ベンゾグアナミン（コア樹脂粒子）の表面にＮｉメッキ層及びＡｕメッキ層が形成された複合粒子を使用した。 Examples 1-8 and Comparative Examples 1-4
After rubbing one side of the glass flat plate with a polyester cloth, the conductive particles shown in Table 1 were sprayed and adsorbed on the surface, and excess conductive particles were removed by tilting the glass flat plate and gently vibrating. However, in Example 6, metal particles having an Au plating layer provided on the surface of the Ni core were used as the conductive particles. In other examples and comparative examples, the surface of benzoguanamine (core resin particles) was Ni plated. Composite particles on which a layer and an Au plating layer were formed were used.

このガラス平板の導電性粒子吸着面を、片面にアルミ電極パッドが８０μｍピッチで５００個設けられた１０ｍｍ角のＩＣチップの電極パッド形成面に重ね、ガラス平板側から超音波圧着装置（Ｕｌｔｒａｓｏｎｉｃ Ｍｉｃｒｏ Ｗｅｌｄｉｎｇ Ｓｙｓｔｅｍ（ＳＨ４０ＭＰ、ＵＬＴＡＸ社製））により超音波圧着処理（周波数１０、５０又は１００ｋＨｚ；圧力４９ＭＰａ；処理時間１０秒）した。これにより、導電性粒子をＩＣチップの電極パッドに金属結合により転着した。パッシべーション膜に付着した余分の導電性粒子をエアブロー処理により吹き飛ばし、図１に示すバンプレス半導体装置（ＩＣチップ）を得た。















The conductive particle adsorption surface of this glass flat plate is superimposed on the electrode pad forming surface of a 10 mm square IC chip having 500 aluminum electrode pads with a pitch of 80 μm on one side, and an ultrasonic pressure bonding device (Ultrasonic Micro Welding) is applied from the glass flat plate side. Ultrasonic pressure bonding (frequency 10, 50 or 100 kHz; pressure 49 MPa; treatment time 10 seconds) was performed using System (SH40MP, manufactured by ULTAX). As a result, the conductive particles were transferred to the electrode pads of the IC chip by metal bonding. Excess conductive particles adhering to the passivation film were blown off by an air blowing process to obtain a bumpless semiconductor device (IC chip) shown in FIG.















Figure 2005286349
Figure 2005286349

次に、得られたバンプレス半導体装置の電極パッドを、２５μｍ厚のポリイミド回路基板の接続端子（８μｍ高さの銅に金メッキを施した回路パターン（８０μｍピッチ））に対して位置合わせし、それらの間に熱硬化型エポキシ系絶縁性接着フィルム（異方性導電接着フィルム（ＦＰ１６６１３、ソニーケミカル社製）から導電性粒子を除去したもの）を挟み込み、１９０℃、圧力１９６０ｋＰａ、１０秒という条件で熱圧着し、接続構造体を得た。   Next, the electrode pads of the obtained bumpless semiconductor device are aligned with the connection terminals of a polyimide circuit board having a thickness of 25 μm (a circuit pattern (80 μm pitch) obtained by gold plating on copper having a height of 8 μm). A thermosetting epoxy-based insulating adhesive film (an anisotropic conductive adhesive film (FP16613, manufactured by Sony Chemical Co., Ltd.) is sandwiched between them, and the conditions are 190 ° C., pressure 1960 kPa, and 10 seconds. A connection structure was obtained by thermocompression bonding.

得られた続構造体について、−５５℃←→１２５℃の間のサーマルショック（１０００サイクル）試験を行ったところ、実施例１〜５、７〜８のバンプレス半導体装置を使用した接続構造体は、抵抗上昇がいずれも１０ｍΩ以内であり、優れた接続信頼性を示した。また、実施例６のバンプレス半導体装置を使用した接続構造体は、抵抗上昇が２００ｍΩ程度であったが、実用上問題のないレベルであった。   About the obtained continuation structure, when the thermal shock (1000 cycles) test between -55 degreeC ←-> 125 degreeC was done, the connection structure using the bumpless semiconductor device of Examples 1-5, 7-8 The resistance increase was within 10 mΩ in all cases, indicating excellent connection reliability. Further, the connection structure using the bumpless semiconductor device of Example 6 had a resistance increase of about 200 mΩ, but it was at a level causing no practical problem.

一方、比較例１のバンプレス半導体装置を使用した接続構造体は、コア樹脂粒子径が小さすぎるために、抵抗上昇が１Ωを超えてしまった。比較例２のバンプレス半導体装置を使用した接続構造体は、コア樹脂粒子径が大きすぎるために、パッドに載らない粒子が出現し、初期抵抗値が高くなり使用に適さないものであった。比較例３のバンプレス半導体装置を使用した接続構造体は、コア樹脂粒子表面の金属メッキ層の厚みが薄すぎるために、導電性粒子が転着していない電極パッドが出現し、初期抵抗値が高くなり使用に適さないものであった。また、比較例４のバンプレス半導体装置を使用した接続構造体は、コア粒子表面の金属メッキ層の厚みが厚すぎるために、導電性粒子同士が凝集し、ショートが発生した。   On the other hand, in the connection structure using the bumpless semiconductor device of Comparative Example 1, the increase in resistance exceeded 1Ω because the core resin particle diameter was too small. In the connection structure using the bumpless semiconductor device of Comparative Example 2, since the core resin particle diameter was too large, particles that could not be placed on the pad appeared and the initial resistance value was high, which was not suitable for use. In the connection structure using the bumpless semiconductor device of Comparative Example 3, since the thickness of the metal plating layer on the surface of the core resin particles is too thin, an electrode pad to which no conductive particles are transferred appears, and the initial resistance value Was high and unsuitable for use. Further, in the connection structure using the bumpless semiconductor device of Comparative Example 4, the thickness of the metal plating layer on the surface of the core particles was too thick, and the conductive particles aggregated to cause a short circuit.

本発明のバンプレス半導体装置によれば、ＩＣチップなどの半導体装置を回路基板にフリップチップ方式で接続する際に、半導体装置にバンプを形成することなく、ショートの抑制、接続コストの低減、接続部へのストレス集中の抑制、及びＩＣチップや回路基板に付加されるダメージの低減を図りつつ、高信頼性且つ低コストでＩＣチップと回路基板とを接続することができる。   According to the bumpless semiconductor device of the present invention, when a semiconductor device such as an IC chip is connected to a circuit board by a flip-chip method, short circuit is suppressed, connection cost is reduced, and connection is not required without forming bumps on the semiconductor device. The IC chip and the circuit board can be connected with high reliability and low cost while suppressing the stress concentration on the part and reducing the damage applied to the IC chip and the circuit board.

本発明のバンプレス半導体装置の概略断面図である。It is a schematic sectional drawing of the bumpless semiconductor device of this invention. 本発明のバンプレス半導体装置及び接続構造体の製造工程図である。It is a manufacturing process figure of the bumpless semiconductor device and connection structure of the present invention. ＩＣチップと回路基板との従来の接続形態の説明図である。It is explanatory drawing of the conventional connection form of an IC chip and a circuit board. ＩＣチップと回路基板との従来の接続形態の説明図である。It is explanatory drawing of the conventional connection form of an IC chip and a circuit board. ＩＣチップと回路基板との従来の接続形態の説明図である。It is explanatory drawing of the conventional connection form of an IC chip and a circuit board.

符号の説明Explanation of symbols

１ バンプレス半導体装置（ＩＣチップ）
２ 電極パッド
３ パッシベーション膜
４ 導電性粒子
５ 回路基板
６ 接続端子
1 Bumpless semiconductor device (IC chip)
2 Electrode Pad 3 Passivation Film 4 Conductive Particles 5 Circuit Board 6 Connection Terminal

Claims (5)

表面に電極パッドが設けられ、電極パッドの周囲にはパッシベーション膜が設けられているバンプレスＩＣチップであって、電極パッドに導電性粒子が金属結合により接続されていることを特徴とするバンプレスＩＣチップ。   A bumpless IC chip having an electrode pad on the surface and a passivation film around the electrode pad, wherein conductive particles are connected to the electrode pad by metal bonding. IC chip. 導電性粒子が、樹脂粒子の表面に金属メッキ層が形成された複合粒子である請求項１記載のバンプレスＩＣチップ。   The bumpless IC chip according to claim 1, wherein the conductive particles are composite particles in which a metal plating layer is formed on the surface of the resin particles. 樹脂粒子の直径が１〜５０μｍであり、金属メッキ層の厚みが１０ｎｍ〜１μｍである請求項２記載のバンプレスＩＣチップ。   The bumpless IC chip according to claim 2, wherein the resin particles have a diameter of 1 to 50 μm and a metal plating layer has a thickness of 10 nm to 1 μm. 金属結合された導電性粒子の少なくとも一部が、パッシべーション膜の表面よりも外側に突出している請求項１〜３のいずれかに記載のバンプレスＩＣチップ。   The bumpless IC chip according to any one of claims 1 to 3, wherein at least a part of the metal-bonded conductive particles protrudes outward from the surface of the passivation film. 請求項１〜４のいずれかに記載のバンプレスＩＣチップの接続パッドに金属結合した導電性粒子が回路基板の接続端子に当接するように、該バンプレスＩＣチップと回路基板とが絶縁性接着材料で接合されていることを特徴とする接続構造体。
The bumpless IC chip and the circuit board are insulatively bonded so that the conductive particles metal-bonded to the connection pad of the bumpless IC chip according to any one of claims 1 to 4 come into contact with the connection terminals of the circuit board. A connection structure characterized by being joined with a material.
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KR20170093170A (en) 2015-01-13 2017-08-14 데쿠세리아루즈 가부시키가이샤 Bump-forming film, semiconductor device, manufacturing method thereof, and connection structure

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170093170A (en) 2015-01-13 2017-08-14 데쿠세리아루즈 가부시키가이샤 Bump-forming film, semiconductor device, manufacturing method thereof, and connection structure
KR20190099103A (en) 2015-01-13 2019-08-23 데쿠세리아루즈 가부시키가이샤 Bump-forming film, semiconductor device, manufacturing method thereof, and connection structure
US10943879B2 (en) 2015-01-13 2021-03-09 Dexerials Corporation Bump-forming film, semiconductor device and manufacturing method thereof, and connection structure

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