JP2005244033A - Electrode package and semiconductor device - Google Patents

Electrode package and semiconductor device Download PDF

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Publication number
JP2005244033A
JP2005244033A JP2004053690A JP2004053690A JP2005244033A JP 2005244033 A JP2005244033 A JP 2005244033A JP 2004053690 A JP2004053690 A JP 2004053690A JP 2004053690 A JP2004053690 A JP 2004053690A JP 2005244033 A JP2005244033 A JP 2005244033A
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electrode
layer
conductive pattern
resin
pattern layer
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Hiroshi Kimura
浩 木村
Osamu Tokuda
修 徳田
Hiroshi Nakagawa
宏史 中川
Kohei Hoshii
康平 星井
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Kyushu Hitachi Maxell Ltd
Maxell Holdings Ltd
Torex Semiconductor Ltd
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Kyushu Hitachi Maxell Ltd
Torex Semiconductor Ltd
Hitachi Maxell Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrode package with which a surface mounted type semiconductor device can be manufactured at a low cost. <P>SOLUTION: A plurality of independent metal layers 22 are arranged in a matrix shape and sealed inside a planar resin 21. The metal layers 22 are exposed from the front surface and back surface of the planar resin 21. The cross-sectional area of the metal layers 22 is increased from the front surface to the back surface of the planar resin 21. On the back surface of the planar resin 21, a reinforcing frame formed by arranging the longitudinal direction of a plurality of bar-shaped bodies 23 along the peripheral edge of the planar resin 21 is provided. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、電極パッケージ及び半導体装置に関し、特にリードレス表面実装型の樹脂封止される半導体素子が搭載される電極パッケージ及びリードレス表面実装型の樹脂封止された半導体装置係るものである。   The present invention relates to an electrode package and a semiconductor device, and more particularly to an electrode package on which a leadless surface mount type resin-encapsulated semiconductor element is mounted and a leadless surface mount type resin-encapsulated semiconductor device.

上述した表面実装技術とは、半導体装置表面に設けた電極をプリント基板に直接半田付けする技術である。この技術を用いることにより、ピン挿入方式で必要だったスルーホールが必要なくなり、部品の小型化、実装密度の増大、基板の小型化などが可能となった。このような表面実装型の半導体装置に用いられる電極パッケージとして、例えば、図４に示されるような電着フレームが特許文献１に記載されている。同図に示すように、電着フレームは、可撓性平板状の金属基板９上に、電着によって、互いに独立した複数の電極材としての金属層８ａ、８ｂが成膜されたものである。   The surface mounting technique described above is a technique for directly soldering an electrode provided on the surface of a semiconductor device to a printed circuit board. By using this technology, the through-holes required for the pin insertion method are no longer necessary, and it is possible to reduce the size of components, increase the mounting density, and reduce the size of the substrate. As an electrode package used in such a surface mount type semiconductor device, for example, an electrodeposition frame as shown in FIG. As shown in the figure, the electrodeposition frame is formed by forming metal layers 8a and 8b as a plurality of independent electrode materials on a flexible flat metal substrate 9 by electrodeposition. .

上述した電着フレームを用いて、以下に示すような手順で、リードレス表面実装型の半導体装置が形成される。まず、図５（ａ）に示すように、電着フレームの金属層８ｂに半導体素子２を接着して搭載し、半導体素子２の電極パッド２ａと金属層８ａとをワイヤ４によって接続する。なお、金属層８ｂは、あらかじめ半導体素子２の底面の面積より広く、成膜されている。そして、ワイヤ４で配線がなされた半導体素子２を、エポキシ樹脂７で樹脂封止する。   Using the above-described electrodeposition frame, a leadless surface mounting type semiconductor device is formed by the following procedure. First, as shown in FIG. 5 (a), the semiconductor element 2 is bonded and mounted on the metal layer 8 b of the electrodeposition frame, and the electrode pad 2 a of the semiconductor element 2 and the metal layer 8 a are connected by the wire 4. The metal layer 8b is formed in advance so as to be wider than the area of the bottom surface of the semiconductor element 2. Then, the semiconductor element 2 wired with the wire 4 is resin-sealed with an epoxy resin 7.

次に、図５（ｂ）に示すように、樹脂封止によって形成された樹脂封止体１１から金属基板９を引き離す。これにより、樹脂封止体１１の底面から、金属層８ａ、８ｂが露出する。その後、図５（ｃ）に示すように、ボール状の導電端子が形成される部分の金属層８ａ、８ｂを選択的に露出して、他の部分をレジスト膜１０でマスクし、半田などの導電材を付着させて導電端子１２を形成する。その後、切断線Ｓに沿って、切断することによって、個々の半導体装置に切り出す。   Next, as shown in FIG. 5B, the metal substrate 9 is pulled away from the resin sealing body 11 formed by resin sealing. Thereby, the metal layers 8 a and 8 b are exposed from the bottom surface of the resin sealing body 11. After that, as shown in FIG. 5C, the metal layers 8a and 8b where the ball-shaped conductive terminals are formed are selectively exposed, and the other portions are masked with a resist film 10, and solder or the like is used. The conductive terminal 12 is formed by attaching a conductive material. Thereafter, the semiconductor device is cut into individual semiconductor devices by cutting along the cutting line S.

しかしながら、上述した電着フレームは、互いに独立した複数の金属層８ａ、８ｂが金属基板９によって支持されているため、金属基板９をつけた状態で、各半導体装置のメーカに納品する必要がある。このため、電着フレームを納品する際の重量が重くなり、納品コストがかかるという問題がある。   However, since the above-described electrodeposition frame has a plurality of metal layers 8a and 8b that are independent of each other and are supported by the metal substrate 9, it is necessary to deliver it to each semiconductor device manufacturer with the metal substrate 9 attached. . For this reason, the weight at the time of delivering an electrodeposition frame becomes heavy, and there exists a problem that delivery cost starts.

また、各メーカにおいて、上述した電着フレームを用いて、半導体装置を作る際には、金属基板９を剥がす必要があり、手間がかかると共に、金属基板９を剥がす装置を所有する必要があり、半導体装置の製造原価が高騰する要因となっていた。さらに、金属層８ｂの端部から切断線Ｓまでの距離Ｄの寸法は、金属層８ａの大きさの１／２と、半導体素子２と金属層８ａ間の絶縁距離Ｃを確保する必要があり、半導体装置を小型にすることができず半導体素子２に対して、大きな面積を必要としていた。これも半導体装置の製造原価が高騰する要因となっていた。
特開２００３−３７２１３公報 In addition, in each manufacturer, when making a semiconductor device using the above-described electrodeposition frame, it is necessary to peel off the metal substrate 9, which is troublesome and requires the possession of a device for peeling the metal substrate 9. The manufacturing cost of semiconductor devices increased. Furthermore, the dimension of the distance D from the end portion of the metal layer 8b to the cutting line S must be 1/2 of the size of the metal layer 8a and the insulation distance C between the semiconductor element 2 and the metal layer 8a. The semiconductor device cannot be reduced in size and requires a large area for the semiconductor element 2. This was also a factor that caused the manufacturing cost of semiconductor devices to rise.
JP 2003-37213 A

そこで、本発明は、上記のような問題点に着目し、安価に、表面実装型の半導体装置を製造することができる電極パッケージ及び当該電極パッケージを用いた半導体装置を提供することを課題とする。   Accordingly, the present invention focuses on the above-described problems, and an object thereof is to provide an electrode package capable of manufacturing a surface-mount type semiconductor device at a low cost and a semiconductor device using the electrode package. .

請求項１記載の発明は、半導体素子が搭載されると共に、前記半導体素子と電気的に接続される導電パターン層と、前記導電パターン層に積層して設けられ、同一形状の複数の独立した電極材から成る電極層と、前記導電パターン層と前記電極層とを封止する板状樹脂とを備え、前記板状樹脂の一方の板面から前記導電パターン層が露出し、他方の板面から前記電極層が露出していることを特徴とする電極パッケージに存する。   According to the first aspect of the present invention, a semiconductor element is mounted, and a conductive pattern layer electrically connected to the semiconductor element and a plurality of independent electrodes having the same shape are provided by being stacked on the conductive pattern layer. An electrode layer made of a material, and a plate-like resin that seals the conductive pattern layer and the electrode layer, the conductive pattern layer is exposed from one plate surface of the plate-like resin, and from the other plate surface In the electrode package, the electrode layer is exposed.

請求項１記載の発明によれば、同一形状の複数の独立した電極材からなる電極層が、導電パターン層に積層して設けられている。導電パターン層と電極層とは板状樹脂内に封止され、一方の板面から導電パターン層が露出し、他方の板面から電極層が露出している。従って、同一形状の複数の独立した電極材からなる電極層を、導電パターン層に積層して設けることにより、電極層に半田などの導電材を付着すれば、均等な大きさの複数の導電端子を設けることができる。しかも、導電パターン層と電極層とを樹脂によって支持することにより、基板を用いることなく電極パッケージを形成することができ、重量を軽くすることができると共に、この電極パッケージを用いて半導体装置を製造する際に、基板を剥がす必要も、均等な導電端子を設けるためのマスクを形成する必要もなくなる。   According to the first aspect of the present invention, the electrode layer made of a plurality of independent electrode materials having the same shape is provided by being laminated on the conductive pattern layer. The conductive pattern layer and the electrode layer are sealed in a plate-shaped resin, and the conductive pattern layer is exposed from one plate surface, and the electrode layer is exposed from the other plate surface. Therefore, by providing an electrode layer composed of a plurality of independent electrode materials having the same shape on the conductive pattern layer, if a conductive material such as solder adheres to the electrode layer, a plurality of conductive terminals of equal size Can be provided. Moreover, by supporting the conductive pattern layer and the electrode layer with resin, an electrode package can be formed without using a substrate, the weight can be reduced, and a semiconductor device can be manufactured using this electrode package. In this case, it is not necessary to peel off the substrate or to form a mask for providing uniform conductive terminals.

請求項２記載の発明は、請求項１記載の電極パッケージと、前記電極パッケージにおいて、前記板状樹脂の導電パターン層が露出している板面に搭載され、前記導電パターン層と電気的に接続された半導体素子と、前記半導体素子を封止する樹脂パッケージとを備えたことを特徴とする半導体装置に存する。   According to a second aspect of the present invention, the electrode package according to the first aspect is mounted on the plate surface where the conductive pattern layer of the plate-like resin is exposed in the electrode package, and is electrically connected to the conductive pattern layer. And a resin package for sealing the semiconductor element.

請求項２記載の発明によれば、半導体素子が、請求項１記載の電極パッケージにおいて、板状樹脂の導電パターン層が露出している板面に搭載され、導電パターン層と電気的に接続される。従って、同一形状の独立した複数の電極材からなる電極層を、導電パターン層に積層して設けることにより、電極層に半田などの導電材を付着すれば、均等な大きさの複数の導電端子を設けることができる。しかも、導電パターン層と電極層とを樹脂によって支持することにより、基板を用いることなく電極パッケージを形成することができ、重量を軽くすることができると共に、この電極パッケージを用いて半導体装置を製造する際に、基板を剥がす必要も、均等な導電端子を設けるためのマスクを形成する必要もなくなる。   According to the invention described in claim 2, the semiconductor element is mounted on the plate surface where the conductive pattern layer of the plate-shaped resin is exposed in the electrode package according to claim 1, and is electrically connected to the conductive pattern layer. The Therefore, by providing an electrode layer made of a plurality of independent electrode materials of the same shape on the conductive pattern layer, a plurality of conductive terminals of equal size can be obtained by attaching a conductive material such as solder to the electrode layer. Can be provided. Moreover, by supporting the conductive pattern layer and the electrode layer with resin, an electrode package can be formed without using a substrate, the weight can be reduced, and a semiconductor device can be manufactured using this electrode package. In this case, it is not necessary to peel off the substrate or to form a mask for providing uniform conductive terminals.

以上説明したように請求項１及び２記載の発明によれば、同一形状の複数の独立した電極材からなる電極層を、導電パターン層に積層して設けることにより、電極層に半田などの導電材を付着すれば、均等な大きさの複数の導電端子を設けることができる。しかも、導電パターン層と電極層とを樹脂によって支持することにより、基板を用いることなく電極パッケージを形成することができ、重量を軽くすることができると共に、この電極パッケージを用いて半導体装置を製造する際に、基板を剥がす必要も、均等な導電端子を設けるためのマスクを形成する必要もなくなるので、安価に、表面実装型の半導体装置を製造することができる電極パッケージ及び当該電極パッケージを用いた半導体装置を得ることができる。   As described above, according to the first and second aspects of the invention, an electrode layer made of a plurality of independent electrode materials having the same shape is laminated on the conductive pattern layer, whereby a conductive material such as solder is provided on the electrode layer. If the material is attached, a plurality of conductive terminals of equal size can be provided. Moreover, by supporting the conductive pattern layer and the electrode layer with resin, an electrode package can be formed without using a substrate, the weight can be reduced, and a semiconductor device can be manufactured using this electrode package. In this case, it is not necessary to peel off the substrate or to form a mask for providing a uniform conductive terminal. Therefore, an electrode package capable of manufacturing a surface-mount type semiconductor device at low cost and the electrode package are used. The obtained semiconductor device can be obtained.

以下、本発明の電極パッケージ及び該電極パッケージを用いた半導体装置について、図面を参照して説明する。なお、本発明は、樹脂封止されたリードレス表面実装型の半導体装置に関し、その製造工程で使用される電極パッケージについて説明する。   Hereinafter, an electrode package of the present invention and a semiconductor device using the electrode package will be described with reference to the drawings. The present invention relates to a resin-sealed leadless surface mounting type semiconductor device, and an electrode package used in the manufacturing process will be described.

図１は、本発明の電極パッケージの一実施の形態を示しており、同図（ａ）はその表面図、同図（ｂ）はその背面図、同図（ｃ）はＩ−Ｉ線断面図である。同図に示すように、電極パッケージ２０は、後述する半導体素子が搭載されると共に、半導体素子と電気的に接続される導電パターン層２１と、この導電パターン層２１に積層して設けられ、同一形状の複数の独立した電極材からなる電極層２２とを備えている。この導電パターン層２１及び電極層２２とは、板状樹脂２３内に封止され、この板状樹脂２３の一方の板面から導電パターン層２１が露出し、他方の板面から電極層２２が露出している。   1A and 1B show an embodiment of an electrode package of the present invention, in which FIG. 1A is a front view thereof, FIG. 1B is a rear view thereof, and FIG. FIG. As shown in the figure, the electrode package 20 is provided with a semiconductor element to be described later, a conductive pattern layer 21 that is electrically connected to the semiconductor element, and a stacked layer provided on the conductive pattern layer 21. And an electrode layer 22 made of a plurality of independent electrode materials. The conductive pattern layer 21 and the electrode layer 22 are sealed in a plate-like resin 23, the conductive pattern layer 21 is exposed from one plate surface of the plate-like resin 23, and the electrode layer 22 is formed from the other plate surface. Exposed.

導電パターン層２１は、その露出面側に形成された金（Ａｕ）ワイヤーが接続可能な金（Ａｕ）又は銀（Ａｇ）薄膜層と、このＡｕ又はＡｇ薄膜層に積層して形成された、ニッケル（Ｎｉ）、ニッケル・コバルト（Ｎｉ・Ｃｏ）又は銅（Ｃｕ）合金を電着したＮｉ、Ｎｉ・Ｃｏ又はＣｕ薄膜層とから構成される。また、電極層２２は、その露出面側に形成された、半田乗りの良い金（Ａｕ）又は錫（Ｓｎ）薄膜層と、このＡｕ又はＳｎ薄膜層に積層して形成された、Ｎｉ、Ｎｉ・Ｃｏ又はＣｕ合金を電着したＮｉ、Ｎｉ・Ｃｏ又はＣｕ薄膜層とから構成される。その厚さは、Ｎｉ、Ｎｉ・Ｃｏ又はＣｕの薄膜層の厚さが２０〜５０μｍであり、Ａｕ、Ｓｎ又はＡｇ薄膜層の厚さが０．０５〜１０μｍである。   The conductive pattern layer 21 was formed by laminating a gold (Au) or silver (Ag) thin film layer to which a gold (Au) wire formed on the exposed surface side can be connected, and the Au or Ag thin film layer. It consists of a Ni, Ni.Co or Cu thin film layer electrodeposited with nickel (Ni), nickel-cobalt (Ni.Co) or copper (Cu) alloy. In addition, the electrode layer 22 is formed by laminating a gold (Au) or tin (Sn) thin film layer with good soldering and formed on the Au or Sn thin film layer on the exposed surface side. -It consists of Ni, Ni-Co or Cu thin film layer which electrodeposited Co or Cu alloy. The thickness of the thin film layer of Ni, Ni · Co or Cu is 20 to 50 μm, and the thickness of the Au, Sn or Ag thin film layer is 0.05 to 10 μm.

続いて、図１の電極パッケージ２０の製造方法の一実施の形態について、図２及び図３を参照して説明する。先ず、図２（ａ）に示すように、電極パッケージ２０を製造するにあたり、可撓性平板状の金属基板３０を用意する。金属基板３０は、薄いステンレス鋼板であり、その厚さは、０．１ｍｍである。そして、金属基板３０の表面上において、導電パターン層２２を形成する部分を除いた部分に、レジスト膜３１を形成する。   Next, an embodiment of a method for manufacturing the electrode package 20 of FIG. 1 will be described with reference to FIGS. First, as shown in FIG. 2A, in manufacturing the electrode package 20, a flexible flat metal substrate 30 is prepared. The metal substrate 30 is a thin stainless steel plate, and its thickness is 0.1 mm. Then, a resist film 31 is formed on the surface of the metal substrate 30 except for the portion where the conductive pattern layer 22 is formed.

その後、金属基板３０を電着漕に侵漬し、金属基板３０と電着漕内の電極との間を通電して、レジスト膜３１が形成されていない部分の金属基板３０上に、Ａｕ又はＡｇ→Ｎｉ、Ｎｉ・Ｃｏ、Ｃｕ合金の順に電気鋳造技術を用いて電着させる。以上の工程により、図２（ｂ）に示すように、金属基板３０の表面に、Ａｕ又はＡｇ薄膜層、Ｎｉ、Ｎｉ・Ｃｏ又はＣｕ薄膜層からなる導電パターン層２１が形成される。   Thereafter, the metal substrate 30 is immersed in the electrodeposition electrode, and a current is passed between the metal substrate 30 and the electrode in the electrodeposition electrode, so that Au or Au is deposited on the portion of the metal substrate 30 where the resist film 31 is not formed. Electrodeposition is performed in the order of Ag → Ni, Ni · Co, and Cu alloy using an electroforming technique. 2B, the conductive pattern layer 21 made of an Au or Ag thin film layer, Ni, Ni.Co, or Cu thin film layer is formed on the surface of the metal substrate 30. As shown in FIG.

続いて、図２（ｃ）に示すように、導電パターン層２１上において、電極層２２を形成する部分を除いた部分に、レジスト膜３２を形成する。その後、金属基板３０を電着槽に侵漬し、金属基板３０と電着漕内の電極との間を通電して、図２（ｄ）に示すように、レジスト膜３２が形成されていない部分の導電パターン層２１に、Ｎｉ、Ｎｉ・Ｃｏ又はＣｕ合金→Ａｕ又はＳｕの順に電着させる。以上の工程により、導電パターン層２１上に電極層２２が形成される。   Subsequently, as illustrated in FIG. 2C, a resist film 32 is formed on the conductive pattern layer 21 in a portion excluding the portion where the electrode layer 22 is formed. Thereafter, the metal substrate 30 is immersed in the electrodeposition tank, and a current is passed between the metal substrate 30 and the electrode in the electrodeposition vessel, so that the resist film 32 is not formed as shown in FIG. A part of the conductive pattern layer 21 is electrodeposited in the order of Ni, Ni · Co or Cu alloy → Au or Su. Through the above steps, the electrode layer 22 is formed on the conductive pattern layer 21.

次に、図２（ｅ）に示すように、レジスト膜３１、３２を同時に除去した後、図２（ｆ）に示すように、スピン塗布法などにより樹脂２３を塗布する。その後、表面全体を削って、図２（ｇ）に示すように、樹脂２３の表面側から電極層２２を露出させると共に、金属基板３０を剥離する。上述したように、導電パターン層２３は、電気鋳造技術を用いて、金属基板３０上に電着されており、さらに、金属基板３０は可撓性のある平板状であるので、簡単に樹脂２３から引き離すことができる。   Next, as shown in FIG. 2E, the resist films 31 and 32 are simultaneously removed, and then a resin 23 is applied by a spin coating method or the like as shown in FIG. Thereafter, the entire surface is shaved to expose the electrode layer 22 from the surface side of the resin 23 and peel off the metal substrate 30 as shown in FIG. As described above, the conductive pattern layer 23 is electrodeposited on the metal substrate 30 by using an electroforming technique. Further, since the metal substrate 30 has a flexible flat plate shape, the resin 23 can be easily formed. Can be pulled away from.

なお、上述した製造工程としては、上述した場合に限定せず、例えば、レジスト膜３１、３２として、ポリイミド系樹脂などの永久レジストを使用すれば、レジスト膜３１、３２を除去したり、除去した後に、樹脂封止したりする必要をなくすことが考えられる。また、例えば、Ｎｉ、Ｎｉ・Ｃｏ又はＣｕ薄膜層のみを樹脂封止した後に、金属基板３０を剥がし、電着漕に侵漬して、表面と裏面とを一緒に同一鍍金することも考えられる。   The manufacturing process described above is not limited to the case described above. For example, if a permanent resist such as a polyimide resin is used as the resist films 31 and 32, the resist films 31 and 32 are removed or removed. Later, it may be possible to eliminate the need for resin sealing. Further, for example, it is also conceivable that, after only the Ni, Ni · Co or Cu thin film layer is resin-sealed, the metal substrate 30 is peeled off and immersed in an electrodeposition plating so that the front and back surfaces are plated together. .

また、導電パターン層２１、電極層２２の成膜法としては、金属基板３０上に導電パターン層２１、電極層２２を電着又はフラッシュ法等で真空蒸着した後、エッチングにより、導電パターン層２１、電極層２２以外の部分を除去することが考えられる。さらに、レジスト膜３１、３２は、導電パターン層２１及び電極層２２を形成した後、同時に除去していたが、導電パターン層２１を電着した後に、レジスト膜３１を除去し、電極層２２を電着した後に、レジスト膜３２を除去することも考えられる。   As a method for forming the conductive pattern layer 21 and the electrode layer 22, the conductive pattern layer 21 and the electrode layer 22 are vacuum-deposited on the metal substrate 30 by electrodeposition or a flash method, and then the conductive pattern layer 21 is etched. It is conceivable to remove portions other than the electrode layer 22. Further, the resist films 31 and 32 were removed at the same time after the conductive pattern layer 21 and the electrode layer 22 were formed. However, after the conductive pattern layer 21 was electrodeposited, the resist film 31 was removed and the electrode layer 22 was removed. It may be considered to remove the resist film 32 after electrodeposition.

上述した電極パッケージ２０は、半導体装置のメーカに納品され、メーカでは、電極パッケージ２０上に半導体素子を搭載して、半導体装置を製造する。続いて、上述した電極パッケージを用いた半導体装置の製造方法について、図３を参照して説明する。まず、同図に示すように、上述した電極パッケージ２０の背面側を上にして、導電パターン層２１上に半導体素子３３を接着して搭載する。半導体素子３３の表面には、電極パッド（図示せず）が形成されている。   The above-described electrode package 20 is delivered to a semiconductor device manufacturer, and the manufacturer mounts a semiconductor element on the electrode package 20 to manufacture the semiconductor device. Next, a method for manufacturing a semiconductor device using the above-described electrode package will be described with reference to FIG. First, as shown in the figure, the semiconductor element 33 is mounted on the conductive pattern layer 21 with the back side of the electrode package 20 described above facing upward. An electrode pad (not shown) is formed on the surface of the semiconductor element 33.

半導体素子３３が搭載された後、金ワイヤ３４によって、半導体素子３３の電極パッドと導電パターン層２１とを電気的に接続する。金ワイヤ３４は、超音波ボンディングなどによって接続される。また、金ワイヤ３４を用いずに、半導体素子３３の表面に設けた電極パッドと導電パターン２１とを直接接続するものもある。次に、半導体素子３３が搭載されて、ワイヤボンディングされた後の電極パッケージ２０が、モールド金型（下型）に装着される。   After the semiconductor element 33 is mounted, the electrode pad of the semiconductor element 33 and the conductive pattern layer 21 are electrically connected by the gold wire 34. The gold wire 34 is connected by ultrasonic bonding or the like. In addition, there is a type that directly connects the electrode pad provided on the surface of the semiconductor element 33 and the conductive pattern 21 without using the gold wire 34. Next, the electrode package 20 on which the semiconductor element 33 is mounted and wire-bonded is mounted on a mold (lower mold).

モールド金型内には、エポキシ樹脂がモールド金型（上型）に形成されたキャビティ（図示せず）により注入される。このモールド金型では、電極パッケージ２０が下型としての機能を果たす。この工程により、半導体素子３２が樹脂３５（樹脂パッケージ）内に封止され、半導体素子３３、導電パターン層２１、電極層２２が樹脂封止された樹脂封止体３６が形成される。また、この樹脂封止体３６の底面から露出している電極層２２上に半田などの導電材を付着して、ボール状の導電端子１２を設ける。   An epoxy resin is injected into the mold through a cavity (not shown) formed in the mold (upper mold). In this mold, the electrode package 20 functions as a lower mold. By this step, the semiconductor element 32 is sealed in the resin 35 (resin package), and the resin sealing body 36 in which the semiconductor element 33, the conductive pattern layer 21, and the electrode layer 22 are sealed with resin is formed. Further, a conductive material such as solder is attached on the electrode layer 22 exposed from the bottom surface of the resin sealing body 36 to provide the ball-shaped conductive terminal 12.

以上述べたように、図１に示す本発明の電極パッケージ２０によれば、同一形状の複数の独立した電極材からなる電極層２２を、導電パターン層２１に積層して設けることにより、電極層２２に半田などの導電材を付着すれば、均等な大きさの複数の導電端子１２を設けることができる。しかも、導電パターン層２１と電極層２２とを樹脂２３によって支持している。このため、従来のように金属基板を用いなくても電極パッケージ２０を形成することができ、重量を軽くすることができ、半導体装置のメーカに、電極パッケージ２０を納品する際のコストを削減することができる。   As described above, according to the electrode package 20 of the present invention shown in FIG. 1, the electrode layer 22 made of a plurality of independent electrode materials having the same shape is stacked on the conductive pattern layer 21 to provide the electrode layer. If a conductive material such as solder is attached to 22, a plurality of conductive terminals 12 of equal size can be provided. In addition, the conductive pattern layer 21 and the electrode layer 22 are supported by the resin 23. Therefore, the electrode package 20 can be formed without using a metal substrate as in the conventional case, the weight can be reduced, and the cost for delivering the electrode package 20 to the manufacturer of the semiconductor device is reduced. be able to.

また、この電極パッケージを用いて半導体装置を製造する過程において、従来のように金属基板３０を剥離する工程も、均等な導電端子１２を設けるためのレジスト膜１０を形成する必要もなくなる。このため、メーカ毎に、金属基板を剥離する装置や、レジスト膜２０を形成する装置も必要がなくなり、製造コストの削減を図ることができる。   Further, in the process of manufacturing a semiconductor device using this electrode package, the process of peeling the metal substrate 30 as in the prior art and the necessity of forming the resist film 10 for providing the uniform conductive terminals 12 are eliminated. For this reason, there is no need for an apparatus for peeling the metal substrate and an apparatus for forming the resist film 20 for each manufacturer, and the manufacturing cost can be reduced.

なお、上述した実施形態では、導電パターン層２１や、電極層２２の露出面側に、半田乗りのよいＡｕ又はＳｎ薄膜層を成膜していた。しかしながら、例えば、半導体素子３３を搭載する過程でＡｕ又はＳｎ薄膜層を成膜する場合、導電パターン層２１や、電極層２２としては、Ｎｉ薄膜層又はＮｉ・Ｃｏ薄膜層からのみ構成しても良い。また、導電パターン層２１や、電極層２２の材料としては、上述した材料に限定されるものではなく、導電パターンや電極の材料と成りうるものであればなんでもよい。   In the embodiment described above, an Au or Sn thin film layer with good soldering is formed on the exposed surface side of the conductive pattern layer 21 and the electrode layer 22. However, for example, when an Au or Sn thin film layer is formed in the process of mounting the semiconductor element 33, the conductive pattern layer 21 and the electrode layer 22 may be composed only of a Ni thin film layer or a Ni / Co thin film layer. good. Further, the material of the conductive pattern layer 21 and the electrode layer 22 is not limited to the above-described material, and any material can be used as long as it can be a material of the conductive pattern or the electrode.

また、電極パッケージ２０は、ボール状の導電端子１２を形成しない状態で、納品していたが、例えば、電極層２２に半田を付着して、ボール状の導電端子１２を形成した状態で、半導体装置のメーカに納品することも考えられる。   In addition, the electrode package 20 has been delivered without forming the ball-shaped conductive terminals 12. However, for example, in the state where the ball-shaped conductive terminals 12 are formed by attaching solder to the electrode layer 22, the semiconductor package is formed. Delivery to the manufacturer of the equipment is also conceivable.

（ａ）〜（ｃ）は各々、本発明の電極パッケージの一実施の形態を示す表面図、背面図及びＩ−Ｉ線断面図である。(A)-(c) is the surface view, back view, and II sectional view which respectively show one Embodiment of the electrode package of this invention. 図１に示す電極パッケージの製造方法の一例を示す図である。It is a figure which shows an example of the manufacturing method of the electrode package shown in FIG. （ａ）及び（ｂ）は各々、図１に示す電極パッケージを用いた半導体装置の表面図と断面図である。(A) And (b) is the surface view and sectional drawing of a semiconductor device using the electrode package shown in FIG. 1, respectively. 従来の電極パッケージの一例である電着フレームを示す断面図である。It is sectional drawing which shows the electrodeposition flame | frame which is an example of the conventional electrode package. 図４に示す電着フレームを用いた半導体装置の製造方法の一例を示す図である。It is a figure which shows an example of the manufacturing method of the semiconductor device using the electrodeposition frame shown in FIG.

符号の説明Explanation of symbols

２１ 導電パターン層
２２ 電極層
２３ 板状樹脂
３３ 半導体素子
３４ ワイヤー
３５ 樹脂（樹脂パッケージ） 21 conductive pattern layer 22 electrode layer 23 plate-shaped resin 33 semiconductor element 34 wire 35 resin (resin package)

Claims (2)

半導体素子が搭載されると共に、前記半導体素子と電気的に接続される導電パターン層と、
前記導電パターン層に積層して設けられ、同一形状の複数の独立した電極材から成る電極層と、
前記導電パターン層と前記電極層とを封止する板状樹脂とを備え、
前記板状樹脂の一方の板面から前記導電パターン層が露出し、他方の板面から前記電極層が露出していることを特徴とする電極パッケージ。 A conductive pattern layer mounted with a semiconductor element and electrically connected to the semiconductor element;
An electrode layer comprising a plurality of independent electrode materials of the same shape, provided to be laminated on the conductive pattern layer;
A plate-like resin that seals the conductive pattern layer and the electrode layer;
The electrode package, wherein the conductive pattern layer is exposed from one plate surface of the plate-like resin, and the electrode layer is exposed from the other plate surface. 請求項１記載の電極パッケージと、
前記電極パッケージにおいて、前記板状樹脂の導電パターン層が露出している板面に搭載され、前記導電パターン層と電気的に接続された半導体素子と、
前記半導体素子を封止する樹脂パッケージとを備えたことを特徴とする半導体装置。 The electrode package according to claim 1,
In the electrode package, a semiconductor element mounted on a plate surface where the conductive pattern layer of the plate-like resin is exposed, and electrically connected to the conductive pattern layer;
A semiconductor device comprising: a resin package for sealing the semiconductor element.
JP2004053690A 2004-02-27 2004-02-27 Electrode package and semiconductor device Pending JP2005244033A (en)

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