JP2005150693A - チップパッケージ構造 - Google Patents
チップパッケージ構造 Download PDFInfo
- Publication number
- JP2005150693A JP2005150693A JP2004272789A JP2004272789A JP2005150693A JP 2005150693 A JP2005150693 A JP 2005150693A JP 2004272789 A JP2004272789 A JP 2004272789A JP 2004272789 A JP2004272789 A JP 2004272789A JP 2005150693 A JP2005150693 A JP 2005150693A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- leads
- lead
- package structure
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】
チップパッケージ構造はチップ、インナー・アウターリードを具えた複数のリード、チップ上表面を露出しチップ周囲を覆う樹脂封止部及び該チップとリードを電気的に接続する複数個のワイヤを具え、該リードは内向きにチップの表面両側部まで延伸し、該リードと該チップ表面両側部の接触部分は粘着方式でチップをマウントしてダイパッドに代え、該リードのアウターリード或いはリード下表面は樹脂封止部外に露出して、はんだ流出を避けはんだ集中を容易にし、樹脂封止材料を節約し、目視での位置決めと再加工ができるようにし、外部電気的接続の接点とする。このようにして、該リードを内向きに延伸してダイパッドの構造に代えることにより、該パッケージ構造の体積を縮小し放熱しやすくし、且つ樹脂封止材料を節約するとともに、良好且つ安定した導通の効果を得る。。
【選択図】 図1
Description
パッケージ構造はチップ1、良好な導電性を具えた複数個のリード12、該チップ11とリード12とを電気的に接続する複数個のワイヤ13、及びチップ11の周囲を覆う樹脂封止部14を具える。該チップ11はメモリチップ、マイクロプロセッサ、ロジック或いはRFチップとしてよく、材質はケイ素、ガリウム砒素或いはその他半導体材料とし、該チップ11は表面111及び表面112を具え、該チップ11の表面111は樹脂封止部14外に露出して、放熱に役立つと同時に封止材料を節約する。
12 リード
13 ワイヤ
14 樹脂封止部
111 上表面
112 下表面
113 粘着材料
126 リード下表面
121、122 二つの平行段
123 垂直段
1211 下表面
1221 上表面
1212 上表面
12a リード
124 カーブ部
125 平面部
Claims (3)
- チップパッケージ構造において、チップ、優れた導電性を具えた複数のリード、該チップとリードを電気的に接続する複数のワイヤ、及び樹脂封止部を具え、
複数のリードは一定の配列順序を呈するように設け、それらのリードはチップの二つの側辺から内側に向かって該チップの表面の両側部まで延伸し、それらのリードの該チップ表面両側部との接触部分は粘着材料でチップ上に粘着固定し、よって粘着方式でチップをマウントすることによりダイパッドに代え、それらのリードのアウターリード或いはリード表面は樹脂封止部外に露出して、外部電気的接続する箇所とするようにして成ることを特徴とするチップパッケージ構造。 - 該樹脂封止部はチップを覆って且つチップの表面を露出するようにして成ることを特徴とする請求項1記載のチップパッケージ構造。
- 該チップのリードは二つの平行段及び該二つの平行段を接続する垂直段から構成してよく、且つ該ワイヤをそのうち一つの平行段の一面上に接続するようにして成ることを特徴とする請求項1記載のチップパッケージ構造。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW092131856A TWI244173B (en) | 2003-11-12 | 2003-11-12 | Semiconductor chip package structure |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2005150693A true JP2005150693A (ja) | 2005-06-09 |
Family
ID=34546516
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004272789A Pending JP2005150693A (ja) | 2003-11-12 | 2004-09-21 | チップパッケージ構造 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7309918B2 (ja) |
JP (1) | JP2005150693A (ja) |
TW (1) | TWI244173B (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009081723A1 (ja) * | 2007-12-20 | 2009-07-02 | Fuji Electric Device Technology Co., Ltd. | 半導体装置およびその製造方法 |
US9818675B2 (en) * | 2015-03-31 | 2017-11-14 | Stmicroelectronics, Inc. | Semiconductor device including conductive clip with flexible leads and related methods |
CN110235260A (zh) * | 2017-01-31 | 2019-09-13 | 晶化成半导体公司 | 用于增强紫外发光器件的可靠性的方法和封装 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3846544A (en) * | 1963-02-11 | 1974-11-05 | Bayer Ag | Sparingly-soluble kallikrein-inactivator derivative and processes involving said derivative |
US3996447A (en) * | 1974-11-29 | 1976-12-07 | Texas Instruments Incorporated | PTC resistance heater |
US4415025A (en) * | 1981-08-10 | 1983-11-15 | International Business Machines Corporation | Thermal conduction element for semiconductor devices |
US4479140A (en) * | 1982-06-28 | 1984-10-23 | International Business Machines Corporation | Thermal conduction element for conducting heat from semiconductor devices to a cold plate |
US5549090A (en) * | 1990-07-31 | 1996-08-27 | Blount; David H. | Electronic ignition system for combustion engines |
US5107330A (en) * | 1990-10-19 | 1992-04-21 | At&T Bell Laboratories | Self-adjusting heat sink design for vlsi packages |
EP0512186A1 (en) * | 1991-05-03 | 1992-11-11 | International Business Machines Corporation | Cooling structures and package modules for semiconductors |
US5801330A (en) * | 1995-02-09 | 1998-09-01 | Robert Bosch Gmbh | Housing for an electrical device having spring means |
US5875096A (en) * | 1997-01-02 | 1999-02-23 | At&T Corp. | Apparatus for heating and cooling an electronic device |
JPH11330283A (ja) * | 1998-05-15 | 1999-11-30 | Toshiba Corp | 半導体モジュール及び大型半導体モジュール |
WO2001077611A1 (en) * | 2000-04-11 | 2001-10-18 | Martin Marietta Materials, Inc. | Evaluating aggregate particle shapes through multiple ratio analysis |
JP3280954B2 (ja) * | 2000-06-02 | 2002-05-13 | 株式会社東芝 | 回路モジュール及び回路モジュールを搭載した電子機器 |
US6417563B1 (en) * | 2000-07-14 | 2002-07-09 | Advanced Micro Devices, Inc. | Spring frame for protecting packaged electronic devices |
FR2835651B1 (fr) * | 2002-02-06 | 2005-04-15 | St Microelectronics Sa | Dispositif de montage d'un boitier semi-conducteur sur une plaque-support par l'intermediaire d'une embase |
KR100416980B1 (ko) * | 2002-02-22 | 2004-02-05 | 삼성전자주식회사 | 볼 그리드 어레이 칩 고정장치 |
US7019976B1 (en) * | 2003-06-04 | 2006-03-28 | Cisco Technology, Inc. | Methods and apparatus for thermally coupling a heat sink to a circuit board component |
US6977434B2 (en) * | 2003-10-20 | 2005-12-20 | Hewlett-Packard Development Company, L.P. | Semiconductor assembly and spring member therefor |
US7280362B2 (en) * | 2003-12-04 | 2007-10-09 | Dell Products L.P. | Method and apparatus for attaching a processor and corresponding heat sink to a circuit board |
JP2005228954A (ja) * | 2004-02-13 | 2005-08-25 | Fujitsu Ltd | 熱伝導機構、放熱システムおよび通信装置 |
-
2003
- 2003-11-12 TW TW092131856A patent/TWI244173B/zh not_active IP Right Cessation
-
2004
- 2004-09-21 JP JP2004272789A patent/JP2005150693A/ja active Pending
- 2004-10-28 US US10/974,728 patent/US7309918B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20050098872A1 (en) | 2005-05-12 |
US7309918B2 (en) | 2007-12-18 |
TW200516741A (en) | 2005-05-16 |
TWI244173B (en) | 2005-11-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2006318996A (ja) | リードフレームおよび樹脂封止型半導体装置 | |
JPH09260550A (ja) | 半導体装置 | |
KR100825784B1 (ko) | 휨 및 와이어 단선을 억제하는 반도체 패키지 및 그제조방법 | |
KR20070000292A (ko) | 패키지 프레임 및 그를 이용한 반도체 패키지 | |
US20080073763A1 (en) | Semiconductor device and method of manufacturing the same | |
JP4767277B2 (ja) | リードフレームおよび樹脂封止型半導体装置 | |
JP6909630B2 (ja) | 半導体装置 | |
JP2002359338A (ja) | リードフレーム及びそれを用いた半導体装置並びにその製造方法 | |
JP2005150693A (ja) | チップパッケージ構造 | |
JPH04316357A (ja) | 樹脂封止型半導体装置 | |
JP6909629B2 (ja) | 半導体装置 | |
JP2007150044A (ja) | 半導体装置 | |
KR20020093250A (ko) | 리드 노출형 리드 프레임 및 그를 이용한 리드 노출형반도체 패키지 | |
JP2009158825A (ja) | 半導体装置 | |
JP4994883B2 (ja) | 樹脂封止型半導体装置 | |
JP2003023126A (ja) | 半導体装置 | |
JP2008288493A (ja) | 半導体装置 | |
JP2007042702A (ja) | 半導体装置 | |
JP4246598B2 (ja) | 電力用半導体装置 | |
JPH0831986A (ja) | 放熱板付半導体装置 | |
JP4241408B2 (ja) | 半導体装置およびその製造方法 | |
JP3918748B2 (ja) | 半導体装置 | |
KR100370480B1 (ko) | 반도체 패키지용 리드 프레임 | |
KR100216843B1 (ko) | 리드프레임의 구조 및 이를 이용한 반도체 패키지 | |
JPS6245159A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060421 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060621 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20060621 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060621 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20081217 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081222 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20090519 |