JP2005101218A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
JP2005101218A
JP2005101218A JP2003332112A JP2003332112A JP2005101218A JP 2005101218 A JP2005101218 A JP 2005101218A JP 2003332112 A JP2003332112 A JP 2003332112A JP 2003332112 A JP2003332112 A JP 2003332112A JP 2005101218 A JP2005101218 A JP 2005101218A
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Prior art keywords
terminals
electrode
terminal
substrate
semiconductor device
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Japanese (ja)
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Takashi Kabasawa
敬 椛澤
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which can improve throughput by shortening a manufacturing process including an electric characteristic test. <P>SOLUTION: The method of manufacturing a semiconductor device comprises an element formation process, a test process, and a connection process. In the element formation process, a transistor 12 having first and second electrodes 12d and 12s and a gate electrode 12g, a first terminal 24 connected to the first electrode 12d, second and third terminals 16 and 23 connected to the second electrode 12s, inductor 11 whose one end is connected to the first electrode 12d on a first substrate 21, and a fourth terminal 15 connected to the other end of the inductor 11, are formed on the first substrate 21. In the test process, DC is measured using the terminals connected to the first and second electrodes 12d and 12s respectively to test the transistor 12 for electric characteristics. In the connection process, the second and fourth terminals 16 and 15 are electrically connected via a connection member after the test process. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、並列接続されたインダクタとトランジスタを有する半導体装置の製造方法に
関する。 The present invention relates to a method for manufacturing a semiconductor device having an inductor and a transistor connected in parallel.

並列接続した絶縁ゲート型電界効果トランジスタ（以下、ＦＥＴという）とスパイラル
インダクタを有する共振型スイッチ回路が、例えば、特許文献１に開示されている。この
共振型スイッチ回路の基本構成を図７に示す。図７において、並列接続した第１のインダ
クタ８１と第１のＦＥＴ８２を有する第１のスイッチ８０ａ、及び、並列接続した第２の
インダクタ８３と第２のＦＥＴ８４を有する第２のスイッチ８０ｂが、直列接続されてい
る。第１及び第２のインダクタ８１，８３は、それぞれ、第１及び第２のＦＥＴ８２，８
４のＯＦＦ容量と並列共振回路を構成している。 A resonant switch circuit including an insulated gate field effect transistor (hereinafter referred to as an FET) and a spiral inductor connected in parallel is disclosed in Patent Document 1, for example. FIG. 7 shows a basic configuration of this resonance type switch circuit. In FIG. 7, a first switch 80a having a first inductor 81 and a first FET 82 connected in parallel, and a second switch 80b having a second inductor 83 and a second FET 84 connected in parallel are connected in series. It is connected. The first and second inductors 81 and 83 are respectively the first and second FETs 82 and 8.
4 constitutes a parallel resonance circuit with an OFF capacitance.

図７において、信号を入力または出力する信号端子、例えば、図中の中央のアンテナ端
子８５は、接続端８６に接続され、並列接続された第１のインダクタ８１と第１のＦＥＴ
８２を介して、信号端子、例えば、図中の左の受信側の端子８７に接続されている。また
、アンテナ端子８５は、接続端８６に接続され、並列接続された第２のインダクタ８３と
第２のＦＥＴ８４を介して、信号端子、例えば、図中の右の送信側の端子８８に接続され
ている。受信モードのときには、第１のスイッチ８０ａがＯＮになり、受信側の端子８７
からアンテナ端子８５へ信号が流れる。また、送信モードのときには、第２のスイッチ８
０ｂがＯＮになり、アンテナ端子８５から送信側の端子８８へ信号が流れる。 In FIG. 7, a signal terminal for inputting or outputting a signal, for example, a central antenna terminal 85 in the figure is connected to a connection end 86 and is connected in parallel to a first inductor 81 and a first FET.
82 is connected to a signal terminal, for example, a terminal 87 on the left side in the drawing. The antenna terminal 85 is connected to the connection end 86 and is connected to a signal terminal, for example, a terminal 88 on the right side in the drawing via a second inductor 83 and a second FET 84 connected in parallel. ing. In the reception mode, the first switch 80a is turned on, and the terminal 87 on the reception side.
To the antenna terminal 85. In the transmission mode, the second switch 8
0b is turned ON, and a signal flows from the antenna terminal 85 to the terminal 88 on the transmission side.

このように構成された回路は、Ｓｉ基板やＧａＡｓ基板などの半導体基板からなる半導
体チップに形成され、この半導体チップは、セラミック基板上に搭載される。セラミック
基板は、表面にグランド端子や電源端子などが形成され、かつ内部に配線層及びビアが形
成されている。半導体チップ上に設けられた各端子は、ワイヤを介して、セラミック基板
の表面に設けられた電極端子に接続されて、外部に接続できるように形成されている。あ
るいは、半導体チップは、リードフレームのダイパッド上に搭載される。半導体チップ上
に設けられた各端子は、ワイヤを介して、インナーリードに接続される。半導体チップ及
びインナーリードは、ハウジング内に設置されている。インナーリードをハウジングから
外部に延びるアウターリードにそれぞれ接続することによって、外部に接続できるように
形成されている。半導体チップは、ハウジング内に設置されている。
特開平９−２３１０１号公報（図１） The circuit configured as described above is formed on a semiconductor chip made of a semiconductor substrate such as a Si substrate or a GaAs substrate, and this semiconductor chip is mounted on a ceramic substrate. The ceramic substrate has a ground terminal, a power supply terminal, and the like formed on the surface, and a wiring layer and a via formed therein. Each terminal provided on the semiconductor chip is connected to an electrode terminal provided on the surface of the ceramic substrate via a wire so that it can be connected to the outside. Alternatively, the semiconductor chip is mounted on a die pad of the lead frame. Each terminal provided on the semiconductor chip is connected to the inner lead via a wire. The semiconductor chip and the inner lead are installed in the housing. The inner leads are formed so as to be connected to the outside by being connected to outer leads extending from the housing to the outside. The semiconductor chip is installed in the housing.
Japanese Patent Laid-Open No. 9-23101 (FIG. 1)

前述したスイッチ回路を搭載した半導体装置の製造方法の工程中には、ＤＣ測定または
ＡＣ測定によって、素子の電気特性の確認が行われる。スイッチ回路のＦＥＴのしきい値
や耐圧などの電気特性をテストする場合、ＤＣ測定を行うと、インダクタとＦＥＴが並列
接続されているため、ＦＥＴのドレイン−ソース間がショートしてしまい、電気特性を調
べることができない。よって、ＦＥＴの電気特性をテストする場合は、後で述べる理由に
より、スイッチ回路等を形成した半導体チップをリードフレームやセラミック基板に搭載
した後（組立後）に、ＡＣ測定によって電気特性を調べる必要がある。この場合、ＤＣ測
定は、直流電流（電圧）による測定であり、ＡＣ測定は周波数を変化させた交流電流（電
圧）による測定である。したがって、ＤＣ測定は、一点データによる測定が可能であるた
め１秒以内で終了するのに対して、ＡＣ測定は数点以上のデータを測定する必要があるた
め数秒程度を要する。よって、ＡＣ測定は、時間がかかるため、組立後にＡＣ測定によっ
て電気特性を調べると、スループットが低下し、ひいてはコストの上昇を招いている。こ
のため、特に、組立前のウェーハ状態で素子に対してＡＣ測定を実施することは避ける必
要がある。しかし、組立後にＡＣ測定を行うと、前述したスループットの問題に加えて、
組立前に不良を発見することができないため、組立ロスが生じるという問題もある。 During the process of the method for manufacturing the semiconductor device mounted with the switch circuit described above, the electrical characteristics of the element are confirmed by DC measurement or AC measurement. When testing the electrical characteristics such as the threshold voltage and breakdown voltage of the FET of the switch circuit, if the DC measurement is performed, the inductor and FET are connected in parallel, so the drain and source of the FET are short-circuited. I can't find out. Therefore, when testing the electrical characteristics of an FET, it is necessary to examine the electrical characteristics by AC measurement after mounting a semiconductor chip on which a switch circuit or the like is formed on a lead frame or a ceramic substrate (after assembly) for the reason described later. There is. In this case, the DC measurement is a measurement using a direct current (voltage), and the AC measurement is a measurement using an alternating current (voltage) whose frequency is changed. Accordingly, the DC measurement can be completed within one second because it can be measured with one point data, whereas the AC measurement requires several seconds because it is necessary to measure several points of data. Therefore, since AC measurement takes time, if the electrical characteristics are examined by AC measurement after assembly, the throughput is reduced, which leads to an increase in cost. For this reason, in particular, it is necessary to avoid performing AC measurement on the device in the wafer state before assembly. However, when AC measurement is performed after assembly, in addition to the above-mentioned throughput problem,
There is also a problem that an assembly loss occurs because a defect cannot be found before assembly.

本発明は、上記した問題点を解決するためになされたもので、電気特性のテストを含め
た製造工程の短縮が可能で、スループットを向上することができる、並列接続されたイン
ダクタとトランジスタを有する半導体装置の製造方法を提供することを目的とする。 The present invention has been made to solve the above-described problems, and has a parallel-connected inductor and transistor that can shorten the manufacturing process including the test of electrical characteristics and can improve the throughput. An object is to provide a method for manufacturing a semiconductor device.

上記した目的を達成するための本発明の半導体装置の製造方法の一態様は、第１の基板
上に、第１及び第２の電極とゲート電極を有するトランジスタ、前記第１の電極に接続さ
れる第１の端子、前記第２の電極に接続される第２及び第３の端子、前記第１の基板上に
一端が前記第１の電極に接続されるインダクタ、前記インダクタの他端に接続される第４
の端子を形成する素子形成工程と、
前記第１及び第２の電極にそれぞれ接続された前記端子を用いて、ＤＣ測定を行い、前記
トランジスタの電気特性をテストするテスト工程と、
前記テスト工程の後に、前記第２及び第４の端子を、接続部材を介して電気的に接続する
接続工程と、
を具備したことを特徴としている。 In one embodiment of a method for manufacturing a semiconductor device of the present invention for achieving the above object, a transistor having first and second electrodes and a gate electrode on a first substrate is connected to the first electrode. A first terminal connected to the second electrode, a third terminal connected to the second electrode, an inductor having one end connected to the first electrode on the first substrate, and a second terminal connected to the other end of the inductor 4th done
An element forming step of forming a terminal of
Using the terminals connected to the first and second electrodes, respectively, performing a DC measurement and testing electrical characteristics of the transistor;
A connecting step of electrically connecting the second and fourth terminals via a connecting member after the test step;
It is characterized by comprising.

以上詳述したように、本発明によれば、電気特性のテストを含めた製造工程の短縮を可
能とし、スループットを向上することができる。 As described above in detail, according to the present invention, it is possible to shorten the manufacturing process including the test of electrical characteristics, and to improve the throughput.

（第１の実施の形態）
図１を参照して、本発明の第１の実施の形態に係る半導体装置の製造方法について、詳
細に説明する。本実施の形態に示す半導体装置は、並列接続した電界効果型電界効果トラ
ンジスタ（以下、「ＦＥＴ」という。）とインダクタを有する共振型スイッチ回路であり
、その製造方法では、ウェーハ状態でのトランジスタなどの素子の電気特性を測定する工
程を含む。 (First embodiment)
With reference to FIG. 1, the manufacturing method of the semiconductor device concerning the 1st Embodiment of this invention is demonstrated in detail. The semiconductor device described in this embodiment is a resonant switch circuit including a field-effect field-effect transistor (hereinafter referred to as “FET”) and an inductor that are connected in parallel. Measuring the electrical characteristics of the device.

まず、図１（ａ）に示すように、Ｓｉ基板またはＧａＡｓ基板などからなる半導体チッ
プ２１上に、スイッチ回路の能動素子である第１及び第２のＦＥＴ１２，１４と、第１及
び第２のインダクタ１１，１３を形成する。第１のインダクタ１１の一端及び第１のＦＥ
Ｔ１２の一端（ここでは、ソース電極１２ｓ）には、テスト用接続端子１５，１６をそれ
ぞれ形成する。テスト用接続端子１５，１６は、離間して形成されており、離間距離は、
８０μｍ程度である。第１のインダクタ１１の他端及び第１のＦＥＴ１２の他端（ここで
は、ドレイン電極１２ｄ）は配線によって接続されており、受信側の端子２４が形成され
ている。 First, as shown in FIG. 1A, on the semiconductor chip 21 made of an Si substrate or a GaAs substrate, the first and second FETs 12 and 14 which are active elements of the switch circuit, and the first and second FETs. Inductors 11 and 13 are formed. One end of the first inductor 11 and the first FE
Test connection terminals 15 and 16 are formed at one end of T12 (here, the source electrode 12s). The test connection terminals 15 and 16 are formed to be separated from each other.
It is about 80 μm. The other end of the first inductor 11 and the other end (here, the drain electrode 12d) of the first FET 12 are connected by a wiring, and a receiving-side terminal 24 is formed.

また、第２のインダクタ１３の一端及び第２のＦＥＴ１４の一端（ここでは、ドレイン
電極１４ｄ）には、テスト用接続端子１７，１８がそれぞれ形成されている。テスト用接
続端子１７，１８は、離間して形成されており、離間距離は、８０μｍ程度である。第２
のインダクタ１３の他端及び第２のＦＥＴ１４の他端（ここでは、ソース電極１４ｓ）は
配線によって接続されており、送信側の端子２５が形成されている。テスト用接続端子１
５，１６のうちの一方、例えば、テスト用接続端子１６と、テスト用接続端子１７，１８
のうちの一方、例えば、テスト用接続端子１８は、接続端２２に接続され、アンテナ端子
２３が形成されている。第１及び第２のＦＥＴ１２，１４のテスト用接続端子は、ソース
電極またはドレイン電極に接続するよう形成されている。第１及び第２のＦＥＴ１２，１
４のゲート電極１２ｇ，１４ｇは、半導体チップ２１上に設けられた図示しない端子にそ
れぞれ接続されている。この素子形成工程では、トランジスタやインダクタなどの素子と
各端子を、同時に形成してもよいし、所望の順序で形成してもよい。 Further, test connection terminals 17 and 18 are formed at one end of the second inductor 13 and one end (here, the drain electrode 14d) of the second FET 14, respectively. The test connection terminals 17 and 18 are formed apart from each other, and the separation distance is about 80 μm. Second
The other end of the inductor 13 and the other end of the second FET 14 (here, the source electrode 14s) are connected by a wiring, and a terminal 25 on the transmission side is formed. Test connection terminal 1
5, 16, for example, the test connection terminal 16 and the test connection terminals 17, 18
For example, the test connection terminal 18 is connected to the connection end 22 to form an antenna terminal 23. The test connection terminals of the first and second FETs 12 and 14 are formed so as to be connected to the source electrode or the drain electrode. First and second FETs 12, 1
The four gate electrodes 12g and 14g are connected to terminals (not shown) provided on the semiconductor chip 21, respectively. In this element formation step, elements such as transistors and inductors and terminals may be formed simultaneously or in a desired order.

次に、図１（ｂ）に示すように、第１のＦＥＴ１２及び第２のＦＥＴ１４の電気特性を
測定する。このとき、第１のＦＥＴ１２の一端に形成されたテスト用接続端子１６と、他
端に形成された受信側の端子２４にＤＣ測定装置１００の端子を接続して、ＤＣ測定を行
う。または、第２のＦＥＴ１４の一端に形成されたテスト用接続端子１８と、他端に形成
された送信側の端子２５を用いて、同様にＤＣ測定を行う。 Next, as shown in FIG. 1B, the electrical characteristics of the first FET 12 and the second FET 14 are measured. At this time, the terminal of the DC measuring device 100 is connected to the test connection terminal 16 formed at one end of the first FET 12 and the receiving-side terminal 24 formed at the other end to perform DC measurement. Alternatively, DC measurement is similarly performed using the test connection terminal 18 formed at one end of the second FET 14 and the transmission-side terminal 25 formed at the other end.

第１のインダクタ１１及び第１のＦＥＴ１２と第２のインダクタ１３及び第２のＦＥＴ
１４は、それぞれ並列接続されていない。よって、ＦＥＴのドレイン−ソース間は、電気
的にショートしていないため、ＦＥＴの電気特性をＤＣ測定によって調べることができる
。 First inductor 11 and first FET 12, second inductor 13 and second FET
14 are not connected in parallel. Therefore, since the FET drain-source is not electrically short-circuited, the electrical characteristics of the FET can be examined by DC measurement.

第１のＦＥＴ１２のＤＣ測定を行うときには、テスト用接続端子１６を用いずに、アン
テナ端子２３と受信側の端子２４を用いて、ＤＣ測定を行ってもよい。あるいは、第１の
ＦＥＴ１２のドレイン電極１２ｄに、別のテスト用接続端子を設け、このテスト用接続端
子と、第１のＦＥＴ１２のソース電極１２ｓに設けられたテスト用接続端子１６を用いて
、ＤＣ測定を行ってもよい。 When performing DC measurement of the first FET 12, DC measurement may be performed using the antenna terminal 23 and the reception-side terminal 24 without using the test connection terminal 16. Alternatively, another test connection terminal is provided on the drain electrode 12 d of the first FET 12, and the test connection terminal 16 and the test connection terminal 16 provided on the source electrode 12 s of the first FET 12 are used to create a DC connection. Measurement may be performed.

次に、図１（ｃ）に示すように、テスト用接続端子１５，１６間及びテスト用接続端子
１５，１６の一部上に、直径１００μｍのバンプ１９を形成し、テスト用接続端子１５，
１６を、バンプ１９を介して接続する。また、テスト用接続端子１７，１８間及びテスト
用接続端子１７，１８の一部上に、直径１００μｍのバンプ１９を形成し、テスト用接続
端子１７，１８を、バンプ１９を介して接続する。バンプ１９は、それぞれテスト用接続
端子１５，１６とテスト用接続端子１７，１８の上から、それぞれの間に至るような形状
になる。このようにして、第１のインダクタ１１と第１のＦＥＴ１２は並列接続され、第
２のインダクタ１３と第２のＦＥＴ１４も同様に並列接続されている。第１及び第２のイ
ンダクタ１１，１３は、それぞれ、第１及び第２のＦＥＴ１２，１４のＯＦＦ容量と並列
共振回路を構成している。これらの第１のスイッチ１０ａ及び第２のスイッチ１０ｂは、
接続端２２で接続され、直列接続されている。続いて、半導体チップ２１を、ワイヤ２８
によって、セラミック基板２７に接続する。セラミック基板２７の表面には、グランド端
子や電源端子などの電極端子２６が形成され、図示しない内部に配線層や配線層同士を接
続するビアが形成されている。 半導体チップ２１は、図示しない樹脂などのハウジング
内に設置される
このようにして形成された並列接続したＦＥＴとインダクタを有する共振型スイッチ回
路では、図１（ｃ）に示すように、半導体チップ２１上に、並列接続した第１のインダク
タ１１と第１のＦＥＴ１２を有する第１のスイッチ１０ａ、及び、並列接続した第２のイ
ンダクタ１３と第２のＦＥＴ１４を有する第２のスイッチ１０ｂが形成されている。第１
及び第２のインダクタ１１，１３は、それぞれ、第１及び第２のＦＥＴ１２，１４のＯＦ
Ｆ容量と並列共振回路を構成している。第１のスイッチ１０ａ及び第２のスイッチ１０ｂ
は、接続端２２で接続され、直列接続されており、３端子を有するシングルポールデュア
ルスルー（Ｓｉｎｇｌｅ Ｐｏｌｅ ＤｕａｌＴｈｒｏｕｇｈ）スイッチを構成している
。このスイッチ回路は、例えば、デジタルコードレス電話機のアンテナを受信状態または
送信状態に切り換えるために用いられる。 Next, as shown in FIG. 1C, bumps 19 having a diameter of 100 μm are formed between the test connection terminals 15 and 16 and part of the test connection terminals 15 and 16,
16 are connected via bumps 19. A bump 19 having a diameter of 100 μm is formed between the test connection terminals 17 and 18 and on a part of the test connection terminals 17 and 18, and the test connection terminals 17 and 18 are connected via the bumps 19. The bumps 19 are shaped so as to reach between the test connection terminals 15 and 16 and the test connection terminals 17 and 18, respectively. In this way, the first inductor 11 and the first FET 12 are connected in parallel, and the second inductor 13 and the second FET 14 are similarly connected in parallel. The first and second inductors 11 and 13 form a parallel resonance circuit with the OFF capacitances of the first and second FETs 12 and 14, respectively. These first switch 10a and second switch 10b are:
They are connected at the connection end 22 and are connected in series. Subsequently, the semiconductor chip 21 is attached to the wire 28.
To connect to the ceramic substrate 27. On the surface of the ceramic substrate 27, electrode terminals 26 such as a ground terminal and a power supply terminal are formed, and a wiring layer and a via for connecting the wiring layers to each other are formed in an inside (not shown). The semiconductor chip 21 is installed in a housing such as resin (not shown). In the resonance type switch circuit having the FET and inductor connected in parallel formed in this way, as shown in FIG. A first switch 10a having a first inductor 11 and a first FET 12 connected in parallel and a second switch 10b having a second inductor 13 and a second FET 14 connected in parallel are formed on the top. Yes. First
And the second inductors 11 and 13 are the OFs of the first and second FETs 12 and 14, respectively.
An F capacitor and a parallel resonance circuit are configured. First switch 10a and second switch 10b
Are connected at the connection end 22 and are connected in series to constitute a single pole dual through switch having three terminals. This switch circuit is used, for example, to switch the antenna of a digital cordless telephone to a reception state or a transmission state.

さらに、図１（ｃ）に示すスイッチ回路では、信号を入力または出力する信号端子、例
えば、図中の中央のアンテナ端子２３は、接続端２２に接続され、並列接続された第１の
インダクタ１１と第１のＦＥＴ１２を介して、信号端子、例えば、図中の左の受信側の端
子２４に接続されている。また、アンテナ端子２３は、並列接続された第２のインダクタ
１３と第２のＦＥＴ１４を介して、信号端子、例えば、図中の右の送信側の端子２５に接
続されている。受信モードのときには、第１のスイッチ１０ａがＯＮになり、受信側の端
子からアンテナ端子へ信号が流れる。また、送信モードのときには、第２のスイッチ１０
ｂがＯＮになり、アンテナ端子から送信側の端子へ信号が流れる。このようにして、アン
テナを受信状態または送信状態に切り換えることができる。 Further, in the switch circuit shown in FIG. 1C, a signal terminal for inputting or outputting a signal, for example, the central antenna terminal 23 in the figure is connected to the connection end 22 and connected in parallel to the first inductor 11. And the first FET 12 to be connected to a signal terminal, for example, a terminal 24 on the left side in the drawing. The antenna terminal 23 is connected to a signal terminal, for example, a terminal 25 on the right side in the drawing via a second inductor 13 and a second FET 14 connected in parallel. In the reception mode, the first switch 10a is turned on, and a signal flows from the reception side terminal to the antenna terminal. In the transmission mode, the second switch 10
b is turned ON, and a signal flows from the antenna terminal to the transmitting terminal. In this way, the antenna can be switched to the reception state or the transmission state.

テスト用接続端子間の距離は、８０μｍに限定されず、離間して形成されていればよい
。テスト用接続端子間の距離は、例えば、１０μｍ以上８０μｍ以下程度で形成される。
また、バンプ１９は、テスト用接続端子間の距離よりもできるだけ大きい径のものを配置
して形成すると、より信頼性が向上するため、好ましい。テスト用接続端子間は、バンプ
を介して接続されているため、電流の流れる断面積を大きく形成することができ、配線層
による接続やワイヤによる接続に比べて、電気抵抗を低減することができる。 The distance between the test connection terminals is not limited to 80 μm, and may be formed so as to be spaced apart. The distance between the test connection terminals is, for example, about 10 μm to 80 μm.
In addition, it is preferable that the bumps 19 be formed with a diameter as large as possible that is greater than the distance between the test connection terminals, since the reliability is further improved. Since the test connection terminals are connected via bumps, the cross-sectional area through which the current flows can be increased, and the electrical resistance can be reduced as compared with the connection by the wiring layer or the connection by the wire. .

本実施の形態では、ウェーハ状態で、ＤＣ測定を行うことによって、電気特性のテスト
しているため、組立後にＡＣ測定によって調べる場合と比べて、短い時間で実施すること
ができるため、電気特性のテストを含めた製造工程の短縮を行うことができ、スループッ
トを向上させ、ひいてはコストを低減することができる。また、組立前に不良を発見する
ことができるため、組立ロスの発生を低減することができる。 In this embodiment, since the electrical characteristics are tested by performing DC measurement in the wafer state, it can be performed in a shorter time as compared with the case of examining by AC measurement after assembly. Manufacturing processes including tests can be shortened, throughput can be improved, and cost can be reduced. In addition, since a defect can be found before assembly, the occurrence of assembly loss can be reduced.

（第１の変形例）
図２に示す第１の変形例では、図１（ｃ）に示した、対応するテスト用接続端子１５，
１６同士及びテスト用接続端子１７，１８同士を接続する工程において、テスト用接続端
子１５，１６同士を接続する際に用いたバンプによる接続に代えて、ワイヤ３１を用いて
接続している。テスト用接続端子１７，１８同士を接続する際も同様に、ワイヤ３１を用
いて接続している。このようにして、ＦＥＴ及びインダクタを並列接続して形成する。テ
スト用接続端子間の距離は、任意の距離で形成することができる。 (First modification)
In the first modification shown in FIG. 2, the corresponding test connection terminals 15, shown in FIG.
In the step of connecting the test terminals 16 and 18 and the test connection terminals 17 and 18, the wires 31 are used instead of the bump connection used when connecting the test connection terminals 15 and 16. Similarly, when connecting the test connection terminals 17, 18, the wires 31 are used for connection. In this way, the FET and the inductor are connected in parallel. The distance between the connection terminals for testing can be formed at an arbitrary distance.

（第２の変形例）
図３に示す第２の変形例では、図１（ｃ）に示した、対応するテスト用接続端子１５，
１６同士及びテスト用接続端子１７，１８同士を接続する工程において、テスト用接続端
子１５，１６同士を接続する際に用いたバンプによる接続に代えて、図３に示すように、
ワイヤ４２を用いて接続している。このとき、図１（ａ）に示す素子及びテスト用接続端
子を形成する工程において、セラミック基板２７の表面に、大きめの電極端子４１を形成
し、対応するテスト用接続端子同士を接続する工程において、テスト用接続端子１５，１
６のそれぞれから、電極端子４１にワイヤ４２を形成することによって、テスト用接続端
子１５，１６を接続している。また、テスト用接続端子１７，１８のそれぞれから、電極
端子４１にワイヤ４２を形成することによって、テスト用接続端子１７，１８を接続して
いる。このようにして、並列接続したＦＥＴ及びインダクタを形成する。テスト用接続端
子間の距離は、任意の距離で形成することができる。 (Second modification)
In the second modification shown in FIG. 3, the corresponding test connection terminals 15, shown in FIG.
As shown in FIG. 3, instead of the connection by the bump used when connecting the test connection terminals 15 and 16 in the process of connecting the 16 connection terminals and the test connection terminals 17 and 18, as shown in FIG.
The wire 42 is used for connection. At this time, in the step of forming the element and the test connection terminal shown in FIG. 1A, in the step of forming the large electrode terminal 41 on the surface of the ceramic substrate 27 and connecting the corresponding test connection terminals to each other. , Test connection terminals 15, 1
6, the test connection terminals 15 and 16 are connected by forming a wire 42 on the electrode terminal 41. Further, the test connection terminals 17 and 18 are connected to the electrode terminal 41 by forming the wire 42 from each of the test connection terminals 17 and 18. In this way, FETs and inductors connected in parallel are formed. The distance between the connection terminals for testing can be formed at an arbitrary distance.

（第３の変形例）
図４に示す第３の変形例では、図１（ａ）に示した素子及びテスト用接続端子を形成す
る工程において、図４（ａ）に示すように、半導体チップ２１をリードフレームのダイパ
ッド５１上に形成している。半導体チップ２１及びインナーリード５２-1〜6は、図示し
ないハウジング内に設置され、インナーリード５２-1〜6をハウジングから外部に延びる
アウターリード（図示しない）にそれぞれ接続することによって、外部に接続できるよう
に形成している。また、第３の変形例では、図１（ｃ）に示した、対応するテスト用接続
端子を接続する工程において、バンプによる接続に代えて、図４（ｂ）に示すように、リ
ードフレームのインナーリード５２-2に、テスト用接続端子１５，１７のそれぞれから、
ワイヤ５３を形成している。なお、受信側の端子２４、送信側の端子２５及びアンテナ端
子２３は、それぞれワイヤ２８を介してリードフレームのインナーリード５２-4,6,2に接
続されている。テスト用接続端子１６，１８は、アンテナ端子２３に接続されており、イ
ンナーリード５２-2と同電位であるため、テスト用接続端子１５，１７からワイヤ５３を
形成することによって、テスト用接続端子１５，１６及びテスト用接続端子１７，１８を
それぞれ接続している。このようにして、並列接続したＦＥＴ及びインダクタを形成する
。 (Third Modification)
In the third modification shown in FIG. 4, in the step of forming the element and the test connection terminal shown in FIG. 1A, as shown in FIG. 4A, the semiconductor chip 21 is replaced with the die pad 51 of the lead frame. Formed on top. The semiconductor chip 21 and the inner leads 52-1 to 6 are installed in a housing (not shown), and are connected to the outside by connecting the inner leads 52-1 to 6 to outer leads (not shown) extending from the housing to the outside. It is formed so that it can be done. Further, in the third modification, in the step of connecting the corresponding test connection terminals shown in FIG. 1C, instead of the connection by the bump, as shown in FIG. From each of the test connection terminals 15 and 17 to the inner lead 52-2,
A wire 53 is formed. The receiving terminal 24, the transmitting terminal 25, and the antenna terminal 23 are connected to the inner leads 52-4, 6, 2 of the lead frame via wires 28, respectively. Since the test connection terminals 16 and 18 are connected to the antenna terminal 23 and have the same potential as the inner lead 52-2, the test connection terminals are formed by forming the wires 53 from the test connection terminals 15 and 17. 15 and 16 and test connection terminals 17 and 18 are connected to each other. In this way, FETs and inductors connected in parallel are formed.

リードフレームに設けられたリード数（ピン数）に余裕がある場合には、テスト用接続
端子１５，１６からインナーリードにワイヤ５３を形成し、同様に、テスト用接続端子１
７，１８から別のインナーリードに、ワイヤ５３を形成して、それぞれを接続してもよい
。また、テスト用接続端子１５〜１８のそれぞれからダイパッド５１にワイヤ５３を形成
することによって、接続することもできる。テスト用接続端子間の距離は、任意の距離で
形成することができる。 When there is a margin in the number of leads (number of pins) provided on the lead frame, a wire 53 is formed from the test connection terminals 15 and 16 to the inner lead, and similarly, the test connection terminal 1
Alternatively, the wires 53 may be formed on the inner leads 7 and 18 and connected to each other. Moreover, it can also connect by forming the wire 53 to the die pad 51 from each of the test connection terminals 15-18. The distance between the connection terminals for testing can be formed at an arbitrary distance.

（第２の実施の形態）
図５を参照して、本発明の第２の実施の形態に係る半導体装置の製造方法について、詳
細に説明する。図５において、図１と同一部分は、同一符号で示す。本実施の形態に示す
半導体装置は、並列接続したＦＥＴとインダクタを有する共振型スイッチ回路であり、そ
の製造方法では、ウェーハ状態でのトランジスタなどの素子の電気特性を測定する工程を
含む。 (Second Embodiment)
With reference to FIG. 5, a method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described in detail. In FIG. 5, the same parts as those in FIG. 1 are denoted by the same reference numerals. The semiconductor device described in this embodiment is a resonant switch circuit including an FET and an inductor connected in parallel, and the manufacturing method thereof includes a step of measuring electrical characteristics of an element such as a transistor in a wafer state.

まず、図５（ａ）に示すように、Ｓｉ基板またはＧａＡｓ基板などからなる半導体チッ
プ２１上に、スイッチ回路の能動素子である第１及び第２のＦＥＴ１２，１４と、第１及
び第２のインダクタ１１，１３を形成する。第１のインダクタ１１及び第１のＦＥＴ１２
の一端には、テスト用接続端子１５，１６をそれぞれ形成する。テスト用接続端子１５，
１６は、離間して形成されている。第１のインダクタ１１及び第１のＦＥＴ１２の他端は
接続されており、受信側の端子２４が形成されている。 First, as shown in FIG. 5A, on the semiconductor chip 21 made of a Si substrate or a GaAs substrate, the first and second FETs 12 and 14 which are active elements of the switch circuit, and the first and second FETs. Inductors 11 and 13 are formed. First inductor 11 and first FET 12
At one end, test connection terminals 15 and 16 are formed, respectively. Test connection terminal 15,
16 is formed apart. The other ends of the first inductor 11 and the first FET 12 are connected, and a receiving-side terminal 24 is formed.

また、第２のインダクタ１３及び第２のＦＥＴ１４の一端には、テスト用接続端子１７
，１８がそれぞれ形成されている。テスト用接続端子１７，１８は、離間して形成されて
いる。第２のインダクタ１３及び第２のＦＥＴ１４の他端は接続されており、送信側の端
子２５が形成されている。第１及び第２のＦＥＴ１２，１４のゲート電極１２ｇ，１４ｇ
は、半導体チップ２１上に設けられた図示しない端子にそれぞれ接続されている。 Further, one end of the second inductor 13 and the second FET 14 is connected to a test connection terminal 17.
, 18 are formed. The test connection terminals 17 and 18 are formed apart from each other. The other ends of the second inductor 13 and the second FET 14 are connected, and a transmission-side terminal 25 is formed. Gate electrodes 12g and 14g of the first and second FETs 12 and 14
Are respectively connected to terminals (not shown) provided on the semiconductor chip 21.

テスト用接続端子１５，１６のうちの一方、例えば、テスト用接続端子１６と、テスト
用接続端子１７，１８のうちの一方、例えば、テスト用接続端子１８は、接続端２２に接
続され、アンテナ端子２３が形成されている。また、セラミック基板２７上に、接続用配
線パターン６１，６２を形成する。接続用配線パターン６１，６２は、半導体チップ２１
上にセラミック基板２７を対向させて配置することによってフリップチップ実装する際に
、テスト用接続端子１５，１６またはテスト用接続端子１７，１８とそれぞれ対応する位
置に形成する。 One of the test connection terminals 15, 16, for example, the test connection terminal 16, and one of the test connection terminals 17, 18, for example, the test connection terminal 18, is connected to the connection end 22 and is connected to the antenna. A terminal 23 is formed. Further, connection wiring patterns 61 and 62 are formed on the ceramic substrate 27. The connection wiring patterns 61 and 62 are formed on the semiconductor chip 21.
When flip-chip mounting is performed by disposing the ceramic substrate 27 so as to face each other, the test connection terminals 15 and 16 or the test connection terminals 17 and 18 are formed at positions corresponding to the test connection terminals 15 and 16, respectively.

次に、図５（ｂ）に示すように、第１のＦＥＴ１２及び第２のＦＥＴ１４の電気特性を
測定する。このとき、第１のＦＥＴ１２の一端に形成されたテスト用接続端子１６と、他
端に形成された受信側の端子２４を用いて、ＤＣ測定を行う。または、第２のＦＥＴ１４
の一端に形成されたテスト用接続端子１７と、他端に形成された送信側の端子２５を用い
て、ＤＣ測定を行う。 Next, as shown in FIG. 5B, the electrical characteristics of the first FET 12 and the second FET 14 are measured. At this time, DC measurement is performed using the test connection terminal 16 formed at one end of the first FET 12 and the reception-side terminal 24 formed at the other end. Alternatively, the second FET 14
DC measurement is performed using the test connection terminal 17 formed at one end of the transmitter and the transmission-side terminal 25 formed at the other end.

第１のインダクタ１１及び第１のＦＥＴ１２と第２のインダクタ１３及び第２のＦＥＴ
１４は、それぞれ並列接続されていない。よって、ＦＥＴのドレイン−ソース間は、電気
的にショートしていないため、ＦＥＴの電気特性をＤＣ測定によって調べることができる
。 First inductor 11 and first FET 12, second inductor 13 and second FET
14 are not connected in parallel. Therefore, since the FET drain-source is not electrically short-circuited, the electrical characteristics of the FET can be examined by DC measurement.

第１のＦＥＴ１２のＤＣ測定を行うときには、テスト用接続端子１６を用いずに、アン
テナ端子２３と受信側の端子２４を用いて、ＤＣ測定を行ってもよい。あるいは、第１の
ＦＥＴ１２のドレイン電極に、別のテスト用接続端子を設け、このテスト用接続端子と、
第１のＦＥＴ１２のソース電極に設けられたテスト用接続端子１６を用いて、ＤＣ測定を
行ってもよい。 When performing DC measurement of the first FET 12, DC measurement may be performed using the antenna terminal 23 and the reception-side terminal 24 without using the test connection terminal 16. Alternatively, the drain electrode of the first FET 12 is provided with another test connection terminal, and this test connection terminal;
DC measurement may be performed using the test connection terminal 16 provided on the source electrode of the first FET 12.

次に、半導体チップ２１上にセラミック基板２７を対向させて配置し、図５（ｃ）の矢
印で示すように、テスト用接続端子１５，１６のそれぞれと接続用配線パターン６２を、
図示しないバンプを介して接続する。また、テスト用接続端子１７，１８のそれぞれと接
続用配線パターン６１を、図示しないバンプを介して接続する。第１のインダクタ１１と
第１のＦＥＴ１２は並列接続され、第２のインダクタ１３と第２のＦＥＴ１４も同様に並
列接続される。第１及び第２のインダクタ１１，１３は、それぞれ、第１及び第２のＦＥ
Ｔ１２，１４のＯＦＦ容量と並列共振回路を構成する。これらの第１のスイッチ１０ａ及
び第２のスイッチ１０ｂは、接続端２２で接続され、直列接続される。このようにして、
並列接続したＦＥＴ１２，１４及びインダクタ１１，１３を形成する。半導体チップをセ
ラミック基板にフリップチップ実装する場合、バンプを介して接続する例を記載したが、
これに限定されず、導電性ペーストからなる接続部材を用いて接続してもよい。テスト用
接続端子間の距離は、任意の距離で形成することができる。 Next, the ceramic substrate 27 is disposed on the semiconductor chip 21 so as to face each other. As shown by arrows in FIG. 5C, each of the test connection terminals 15 and 16 and the connection wiring pattern 62 are connected to each other.
Connection is made via a bump (not shown). Further, each of the test connection terminals 17 and 18 and the connection wiring pattern 61 are connected through bumps (not shown). The first inductor 11 and the first FET 12 are connected in parallel, and the second inductor 13 and the second FET 14 are similarly connected in parallel. The first and second inductors 11 and 13 have first and second FEs, respectively.
A parallel resonance circuit is formed with the OFF capacitors of T12 and T14. The first switch 10a and the second switch 10b are connected at the connection end 22 and are connected in series. In this way
The FETs 12 and 14 and the inductors 11 and 13 connected in parallel are formed. In the case of flip-chip mounting a semiconductor chip on a ceramic substrate, an example of connecting via a bump has been described.
It is not limited to this, You may connect using the connection member which consists of electrically conductive paste. The distance between the connection terminals for testing can be formed at an arbitrary distance.

続いて、図５（ｃ）に示す半導体装置の製造方法によって製造された半導体装置を実装
した場合の、Ａ−Ａにおける断面図を図６に示す。第１の実施の形態では、同一平面上で
のバンプによる接続を行っているのに対し、本実施の形態では、図６に示すように、バン
プ６３を用いたフリップチップ実装を行うことによって、テスト用接続端子１５，１６と
テスト用接続端子１７，１８を、それぞれ接続端子用配線パターン６２，６１を介して、
接続している。セラミック基板２７の表面には、グランド端子や電源端子などの図示しな
い電極端子が形成され、内部に配線層や配線層同士を接続するビアが形成されている。図
６では、半導体チップ２１は、樹脂などのハウジング６４内に設置されている。また、バ
ンプ６３以外にも半導体チップ及びセラミック基板を接続するバンプが形成されているが
、ここでは図示を省略する。 Next, FIG. 6 shows a cross-sectional view taken along line AA when the semiconductor device manufactured by the method for manufacturing a semiconductor device shown in FIG. In the first embodiment, the connection by the bumps on the same plane is performed. In the present embodiment, as shown in FIG. 6, by performing the flip chip mounting using the bumps 63, The test connection terminals 15 and 16 and the test connection terminals 17 and 18 are connected to the connection terminal wiring patterns 62 and 61, respectively.
Connected. On the surface of the ceramic substrate 27, electrode terminals (not shown) such as a ground terminal and a power supply terminal are formed, and a wiring layer and a via for connecting the wiring layers are formed therein. In FIG. 6, the semiconductor chip 21 is installed in a housing 64 made of resin or the like. In addition to the bumps 63, bumps for connecting the semiconductor chip and the ceramic substrate are formed, but the illustration is omitted here.

以上、第１及び第２の実施の形態では、第１及び第２のスイッチ１０ａ，１０ｂのテス
ト用接続端子１５〜１８を接続端２２側に設けた例を記載したが、テスト用接続端子１５
〜１８を接続端２２に対して反対側（受信側の端子２４側、または、送信側の端子２５側
）に設けてもかまわない。第１及び第２のスイッチ１０ａ，１０ｂのどちらか一方のテス
ト用接続端子（すなわち、テスト用接続端子１５，１６またはテスト用接続端子１７，１
８）を接続端２２に対して反対側に設けてもよい。このように、テスト用接続端子の位置
については、特に限定されない。 As described above, in the first and second embodiments, the example in which the test connection terminals 15 to 18 of the first and second switches 10a and 10b are provided on the connection end 22 side is described.
˜18 may be provided on the side opposite to the connection end 22 (the terminal 24 on the receiving side or the terminal 25 on the transmitting side). One of the test connection terminals of the first and second switches 10a and 10b (that is, the test connection terminals 15 and 16 or the test connection terminals 17 and 1).
8) may be provided on the side opposite to the connection end 22. Thus, the position of the test connection terminal is not particularly limited.

また、第１及び第２のスイッチ１０ａ，１０ｂが形成された３端子のシングルポールデ
ュアルスルーを例に説明したが、一つのＦＥＴ及びインダクタを有するスイッチに適用し
てもかまわないし、２以上の複数のＦＥＴ及びインダクタを有するスイッチに適用しても
かまわない。 Further, although the description has been given by taking as an example a three-terminal single pole dual through in which the first and second switches 10a and 10b are formed, the present invention may be applied to a switch having one FET and an inductor. It may be applied to a switch having a FET and an inductor.

また、一枚の半導体チップを形成した場合を例に説明したが、スイッチ回路のインダク
タ及びＦＥＴなどの素子数によっては、複数の半導体チップを相互に接続したスイッチ回
路にも同様に適用することができる。インダクタは、スパイラル型インダクタなど、特に
限定されない。また、半導体チップを搭載する基板として、セラミック基板を用いた例を
記載したがこれに限定されず、誘電体基板、絶縁基板であってもかまわない。 In addition, the case where a single semiconductor chip is formed has been described as an example, but depending on the number of elements such as inductors and FETs of the switch circuit, it can be similarly applied to a switch circuit in which a plurality of semiconductor chips are connected to each other. it can. The inductor is not particularly limited, such as a spiral inductor. Moreover, although the example which used the ceramic substrate was described as a board | substrate which mounts a semiconductor chip, it is not limited to this, A dielectric substrate and an insulating substrate may be sufficient.

本発明の第１の実施の形態に係る半導体装置の製造方法の各工程を示す平面図である。It is a top view which shows each process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の実施の形態の第１の変形例に係る半導体装置の製造方法の各工程を示す平面図である。It is a top view which shows each process of the manufacturing method of the semiconductor device which concerns on the 1st modification of embodiment of this invention. 本発明の実施の形態の第２の変形例に係る半導体装置の製造方法の各工程を示す平面図である。It is a top view which shows each process of the manufacturing method of the semiconductor device which concerns on the 2nd modification of embodiment of this invention. 本発明の実施の形態の第３の変形例に係る半導体装置の製造方法の各工程を示す平面図である。It is a top view which shows each process of the manufacturing method of the semiconductor device which concerns on the 3rd modification of embodiment of this invention. 本発明の第２の実施の形態に係る半導体装置の製造方法の各工程を示す平面図である。It is a top view which shows each process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. 図５（ｃ）のＡ−Ａにおける断面図である。It is sectional drawing in AA of FIG.5 (c). 共振型スイッチ回路の基本構成を示す回路図である。It is a circuit diagram which shows the basic composition of a resonance type switch circuit.

符号の説明Explanation of symbols

１０ａ 第１のスイッチ
１０ｂ 第２のスイッチ
１１ 第１のインダクタ
１２ 第１のＦＥＴ
１２ｓ，１４ｓ ソース電極
１２ｄ，１４ｄ ドレイン電極
１２ｇ，１４ｇ ゲート電極
１３ 第２のインダクタ
１４ 第２のＦＥＴ
１５，１６，１７，１８ テスト用接続端子
１９，６３ バンプ
２１ 半導体チップ
２２ 接続端
２３ アンテナ端子
２４ 受信側の端子
２５ 送信側の端子
２６，４１ 電極端子
２７ セラミック基板
２８，３１，４２，５３ ワイヤ
５１ ダイパッド
５２-1〜6 インナーリード
６１，６２ 接続端子用配線パターン
６４ ハウジング
１００ ＤＣ測定装置

10a 1st switch 10b 2nd switch 11 1st inductor 12 1st FET
12s, 14s Source electrodes 12d, 14d Drain electrodes 12g, 14g Gate electrode 13 Second inductor 14 Second FET
15, 16, 17, 18 Test connection terminals 19, 63 Bump 21 Semiconductor chip 22 Connection end 23 Antenna terminal 24 Reception side terminal 25 Transmission side terminal 26, 41 Electrode terminal 27 Ceramic substrate 28, 31, 42, 53 Wire 51 Die Pads 52-1 to 6 Inner Leads 61, 62 Connection Terminal Wiring Pattern 64 Housing 100 DC Measuring Device

Claims (9)

第１の基板上に、第１及び第２の電極とゲート電極を有するトランジスタ、前記第１の
電極に接続される第１の端子、前記第２の電極に接続される第２及び第３の端子、前記第
１の基板上に一端が前記第１の電極に接続されるインダクタ、及び前記インダクタの他端
に接続される第４の端子を形成する素子形成工程と、
前記第１及び第２の電極にそれぞれ接続された前記端子を用いて、ＤＣ測定を行い、前記
トランジスタの電気特性をテストするテスト工程と、
前記テスト工程の後に、前記第２及び第４の端子を、接続部材を介して電気的に接続する
接続工程と、
を具備したことを特徴とする半導体装置の製造方法。 A transistor having first and second electrodes and a gate electrode on a first substrate, a first terminal connected to the first electrode, and second and third terminals connected to the second electrode An element forming step of forming a terminal, an inductor having one end connected to the first electrode on the first substrate, and a fourth terminal connected to the other end of the inductor;
Using the terminals connected to the first and second electrodes, respectively, performing a DC measurement and testing electrical characteristics of the transistor;
A connecting step of electrically connecting the second and fourth terminals via a connecting member after the test step;
A method for manufacturing a semiconductor device, comprising: 前記第１及び第３の端子を信号端子として形成することを特徴とする請求項１に記載の
半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first and third terminals are formed as signal terminals. 前記接続工程は、前記第２及び第４の端子の上から、前記第２及び第４の端子間に至る
バンプを形成することによって、前記第２及び第４の端子を電気的に接続することを特徴
とする請求項１または請求項２に記載の半導体装置の製造方法。 The connecting step includes electrically connecting the second and fourth terminals by forming bumps extending from above the second and fourth terminals to between the second and fourth terminals. The method for manufacturing a semiconductor device according to claim 1, wherein: 前記接続回路を構成する工程は、ワイヤを介して前記第２及び第４の端子を電気的に接
続することを特徴とする請求項１または請求項２に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of configuring the connection circuit electrically connects the second and fourth terminals via a wire. 表面に電極端子を有する第２の基板を用意し、前記第２の基板上に前記第１の基板を搭
載する工程をさらに有し、
前記接続工程では、前記第２及び第４の端子と前記電極端子とがそれぞれ接続するようワ
イヤを形成することによって、前記第２及び第４の端子を電気的に接続することを特徴と
する請求項１または請求項２に記載の半導体装置の製造方法。 Providing a second substrate having electrode terminals on the surface, and further mounting the first substrate on the second substrate;
In the connecting step, the second and fourth terminals are electrically connected by forming wires so that the second and fourth terminals and the electrode terminals are connected to each other. A method for manufacturing a semiconductor device according to claim 1 or 2. 第２の基板の表面に配線パターンを形成する工程をさらに有し、
前記接続工程において、前記配線パターンが、前記第１の基板から離れて対向するように
前記第２の基板を配置し、前記第２及び第４の端子と前記配線パターンをそれぞれ接続す
るようにバンプを形成することによって、前記第２及び第４の端子を電気的に接続するこ
とを特徴とする請求項１または請求項２に記載の半導体装置の製造方法。 A step of forming a wiring pattern on the surface of the second substrate;
In the connecting step, the second substrate is disposed so that the wiring pattern faces away from the first substrate, and bumps are formed so as to connect the second and fourth terminals to the wiring pattern, respectively. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the second and fourth terminals are electrically connected by forming. ダイパッドとリードを有するとともに、表面に電極端子が設けられたリードフレームを
形成し、前記リードフレームのダイパッド上に前記第１の基板を搭載する工程をさらに有
し、
前記接続工程において、前記第３及び第４の端子から、それぞれ前記ダイパッドまたは同
じリードにワイヤを接続することによって、前記第２の端子と第４の端子を接続すること
を特徴とする請求項１または請求項２に記載の半導体装置の製造方法。 The method further includes a step of forming a lead frame having a die pad and a lead and having electrode terminals provided on the surface, and mounting the first substrate on the die pad of the lead frame,
2. The connecting step, wherein the second terminal and the fourth terminal are connected by connecting wires from the third and fourth terminals to the die pad or the same lead, respectively. A method for manufacturing a semiconductor device according to claim 2. ダイパッドとリードを有するとともに、表面に電極端子が設けられたリードフレームを
形成し、前記リードフレームのダイパッド上に前記第１の基板を搭載する工程をさらに有
し、
前記接続工程において、前記第２及び第４の端子から、それぞれ前記ダイパッドまたは同
じリードにワイヤを接続することによって、前記第２の端子と第４の端子を接続すること
を特徴とする請求項１または請求項２に記載の半導体装置の製造方法。 The method further includes a step of forming a lead frame having a die pad and a lead and having electrode terminals provided on the surface, and mounting the first substrate on the die pad of the lead frame,
2. The connecting step, wherein the second terminal and the fourth terminal are connected by connecting wires from the second and fourth terminals to the die pad or the same lead, respectively. A method for manufacturing a semiconductor device according to claim 2. 第１の基板上に、第１及び第２の電極とゲート電極を有する第１のトランジスタ、前記
第１の基板上に、前記第２の電極に接続される接続端を介して前記第２の電極に接続され
た第３の電極、第４の電極及びゲート電極を有する第２のトランジスタ、前記接続端に接
続される第１の信号端子、前記第２及び第３の電極に接続される第１及び第２の接続端子
、前記第１の電極に接続される第２の信号端子、前記第４の電極に接続される第３の信号
端子、前記第１の基板上に一端が前記第１及び第４の電極にそれぞれ接続される第１及び
第２のインダクタ、及び前記第１及び第２のインダクタの他端にそれぞれ接続される第３
及び第４の接続端子を形成する素子形成工程と、
前記第１の電極及び第２の電極にそれぞれ接続された前記端子を用いて、ＤＣ測定を行い
、前記第１のトランジスタの電気特性をテストする第１のテスト工程と、
前記第３の電極及び第４の電極にそれぞれ接続された前記端子を用いて、ＤＣ測定を行い
、前記第２のトランジスタの電気特性をテストする第２のテスト工程と、
前記テスト工程の後に、前記第１及び第３の接続端子と、前第２及び第４の接続端子を、
それぞれ接続部材を介して、それぞれ電気的に接続する接続工程と、
を具備したことを特徴とする半導体装置の製造方法。 A first transistor having first and second electrodes and a gate electrode on a first substrate, and the second transistor on a first substrate via a connection end connected to the second electrode. A third transistor connected to the electrode, a second transistor having a fourth electrode and a gate electrode, a first signal terminal connected to the connection end, and a second transistor connected to the second and third electrodes. 1 and 2nd connection terminal, 2nd signal terminal connected to the 1st electrode, 3rd signal terminal connected to the 4th electrode, one end on the 1st substrate is the 1st And a first inductor connected to the fourth electrode and a third inductor connected to the other end of the second inductor, respectively.
And an element forming step of forming a fourth connection terminal;
A first test step of performing DC measurement using the terminals connected to the first electrode and the second electrode, respectively, and testing electrical characteristics of the first transistor;
Using the terminals connected to the third electrode and the fourth electrode, respectively, performing a DC measurement and testing the electrical characteristics of the second transistor;
After the test step, the first and third connection terminals and the front second and fourth connection terminals,
A connecting step of electrically connecting each via a connecting member;
A method for manufacturing a semiconductor device, comprising:
JP2003332112A 2003-09-24 2003-09-24 Method of manufacturing semiconductor device Pending JP2005101218A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009049849A (en) * 2007-08-22 2009-03-05 Nec Electronics Corp Switch circuit and phase shifter
JP2015207736A (en) * 2014-04-23 2015-11-19 富士電機株式会社 Method of manufacturing semiconductor device, method of estimating semiconductor device and semiconductor device
JP2018164112A (en) * 2018-07-17 2018-10-18 富士電機株式会社 Semiconductor device manufacturing method and semiconductor device evaluating method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009049849A (en) * 2007-08-22 2009-03-05 Nec Electronics Corp Switch circuit and phase shifter
JP2015207736A (en) * 2014-04-23 2015-11-19 富士電機株式会社 Method of manufacturing semiconductor device, method of estimating semiconductor device and semiconductor device
JP2018164112A (en) * 2018-07-17 2018-10-18 富士電機株式会社 Semiconductor device manufacturing method and semiconductor device evaluating method

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