JP2005101106A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP2005101106A
JP2005101106A JP2003330427A JP2003330427A JP2005101106A JP 2005101106 A JP2005101106 A JP 2005101106A JP 2003330427 A JP2003330427 A JP 2003330427A JP 2003330427 A JP2003330427 A JP 2003330427A JP 2005101106 A JP2005101106 A JP 2005101106A
Authority
JP
Japan
Prior art keywords
semiconductor element
semiconductor device
recess
semiconductor
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003330427A
Other languages
Japanese (ja)
Inventor
Hisato Ogasawara
寿人 小笠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Takaya Electronic Industry Co Ltd
Original Assignee
Sharp Takaya Electronic Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Takaya Electronic Industry Co Ltd filed Critical Sharp Takaya Electronic Industry Co Ltd
Priority to JP2003330427A priority Critical patent/JP2005101106A/en
Publication of JP2005101106A publication Critical patent/JP2005101106A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which reduces a material cost and improves productivity. <P>SOLUTION: The semiconductor device 1 comprises semiconductor elements 3 and 4 which are stacked up in a vertical direction, and bonding pads 3a formed on the lower semiconductor element 3 located below are so configured as to be hidden under the upper semiconductor element 4 relatively located above the lower semiconductor element 3. Recesses 8 for forming spaces S for connecting wires 5 to the bonding pads 3a of the lower semiconductor element 3 are provided to the under surface of the upper semiconductor element 4. Concretely, the semiconductor elements 3 and 4 are nearly equal in size to each other in a plan view, the bonding pads 3a are provided on the peripheral edge of the top surface of the lower semiconductor element 3, and the recesses 8 are provided on the peripheral edge of the undersurface of the upper semiconductor element 4 confronting the bonding pads 3a respectively. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

本発明は、積層された複数の半導体素子を含む半導体装置及びその製造方法に関するものである。   The present invention relates to a semiconductor device including a plurality of stacked semiconductor elements and a method for manufacturing the same.

近年各種電子機器の小型化が進み、これらに用いられる半導体装置についても小型化が要求されている。そこで１つの半導体装置内に複数の半導体素子を積層して、小型化、高容量化を図った半導体装置が製造されている。   In recent years, miniaturization of various electronic devices has progressed, and miniaturization of semiconductor devices used for these devices is also required. Thus, a semiconductor device is manufactured in which a plurality of semiconductor elements are stacked in one semiconductor device to reduce the size and increase the capacity.

従来のこの種の半導体装置として、まず、特許文献１記載のものを例示する。この半導体装置８０は、図７に示すように、基板８１上に２つの半導体素子８２，８３が積層されている。そして、基板８１に直接接合される半導体素子である下側半導体素子８２よりも、その上側に積層される半導体素子である上側半導体素子８３のサイズが小さくなるように形成されている。これにより、下側半導体素子８２上に形成されたボンディングパッド８２ａにワイヤ８４を接続するための空間Ｓを確保するようにしている。しかしながら、本構造では、上側半導体素子８３のサイズを、下側半導体素子８２よりも小さくしなければならないという制約があるという問題がある。   As a conventional semiconductor device of this type, a device described in Patent Document 1 is first exemplified. In the semiconductor device 80, two semiconductor elements 82 and 83 are stacked on a substrate 81 as shown in FIG. The size of the upper semiconductor element 83 which is a semiconductor element stacked on the upper side of the lower semiconductor element 82 which is a semiconductor element directly bonded to the substrate 81 is smaller. Thus, a space S for connecting the wire 84 to the bonding pad 82a formed on the lower semiconductor element 82 is secured. However, this structure has a problem that the size of the upper semiconductor element 83 must be smaller than that of the lower semiconductor element 82.

そこで、例えば、特許文献２記載の半導体装置９０では、図８に示すように積層される上下の半導体素子９２，９２，…間に、スペーサー９１を介在させる構成を採用している。このスペーサー９１の厚みにより、相対的に下側の半導体素子９２上のボンディングパッド９２ａにワイヤ９４を接続するための空間Ｓを確保することで、上記制約を解消するようにしている。   Therefore, for example, in the semiconductor device 90 described in Patent Document 2, a configuration in which a spacer 91 is interposed between upper and lower semiconductor elements 92, 92,... Stacked as shown in FIG. The space 91 for connecting the wire 94 to the bonding pad 92a on the relatively lower semiconductor element 92 is secured by the thickness of the spacer 91, thereby eliminating the above-described restriction.

特開平１１−３０７５７１号公報（段落［０００３］、図１４）Japanese Patent Laid-Open No. 11-307571 (paragraph [0003], FIG. 14) 特開２００２−２６１２３３号公報JP 2002-261233 A

ところが、特許文献２記載の半導体素子９０を製造するには、各半導体素子９２間にスペーサー９１をボンディングする必要があり、スペーサー９１や接着材等の材料費が掛かるとともに工数が増えて生産性が低下するという問題がある。しかも、通常、半導体装置の生産ラインには、ボンディング回数に応じた数のボンディング装置が設けられるため、ボンディング回数に比例して生産設備コストも増大するという問題がある。特に、積層される半導体素子数が増加するほど、スペーサー９１の数も増え、この問題は大きくなる。   However, in order to manufacture the semiconductor element 90 described in Patent Document 2, it is necessary to bond the spacers 91 between the semiconductor elements 92, which increases the man-hours and productivity due to the cost of materials such as the spacers 91 and adhesives. There is a problem of lowering. In addition, since the number of bonding apparatuses corresponding to the number of bondings is usually provided in the production line of semiconductor devices, there is a problem that the production equipment cost increases in proportion to the number of bondings. In particular, as the number of stacked semiconductor elements increases, the number of spacers 91 increases, and this problem increases.

上記課題を解決するために、本発明の半導体装置は、
上下に積層された複数の半導体素子を含み、相対的に下側にある半導体素子である下側半導体素子に形成されたボンディングパッドが、相対的に上側にある半導体素子である上側半導体素子の下に隠れるように構成された半導体装置であって、
前記上側半導体素子は、その下面に、前記下側半導体素子の前記ボンディングパッドにワイヤを接続するための空間を形成する凹所が設けられている。 In order to solve the above problems, a semiconductor device of the present invention includes:
The bonding pad formed on the lower semiconductor element, which is a relatively lower semiconductor element, includes a plurality of semiconductor elements stacked one above the other. A semiconductor device configured to be hidden by
The upper semiconductor element is provided with a recess on the lower surface thereof for forming a space for connecting a wire to the bonding pad of the lower semiconductor element.

前記半導体装置としては、
前記下側半導体素子及び前記上側半導体素子は、平面視のサイズが略同一に形成されており、
前記下側半導体素子は、その上面の縁部に前記ボンディングパッドが配設されており、
前記上側半導体素子は、その下面における前記ボンディングパッドへ対峙する縁部に前記凹所が設けられている
態様を例示する。 As the semiconductor device,
The lower semiconductor element and the upper semiconductor element are formed to have substantially the same size in plan view,
The lower semiconductor element has the bonding pad disposed on the edge of the upper surface thereof,
The upper semiconductor element exemplifies a mode in which the recess is provided in an edge portion of the lower surface facing the bonding pad.

これらの構成によれば、前記上側半導体素子は、その下面における前記ボンディングパッドへ対峙する縁部に前記凹所が設けられているので、従来とは異なり、前記上側半導体素子と前記下側半導体素子の間にスペーサーを介在させなくてもよく、材料費を低減するとともに生産性を向上することができる。   According to these configurations, the upper semiconductor element and the lower semiconductor element are different from conventional ones because the upper semiconductor element is provided with the recess at the edge facing the bonding pad on the lower surface thereof. There is no need to interpose a spacer between them, and material costs can be reduced and productivity can be improved.

また、本発明の半導体装置の製造方法は、
上下に積層された複数の半導体素子を含み、相対的に下側にある半導体素子である下側半導体素子に形成されたボンディングパッドが、相対的に上側にある半導体素子である上側半導体素子の下に隠れるように構成された半導体装置の製造方法であって、
前記下側半導体素子の前記ボンディングパッド上にワイヤを接続するための空間を形成する凹所を、前記上側半導体素子の下面に設ける段階と、
前記ボンディングパッドに前記ワイヤが接続された前記下側半導体素子の上に前記上側半導体素子を積層する段階と
を含んでいる。 In addition, a method for manufacturing a semiconductor device of the present invention includes:
The bonding pad formed on the lower semiconductor element, which is a relatively lower semiconductor element, includes a plurality of semiconductor elements stacked one above the other. A method of manufacturing a semiconductor device configured to be hidden by
Providing a recess for forming a space for connecting a wire on the bonding pad of the lower semiconductor element on the lower surface of the upper semiconductor element;
Laminating the upper semiconductor element on the lower semiconductor element having the wire connected to the bonding pad.

この製造方法によっても、前記本発明に係る半導体装置と同様の効果を得ることができる。   Also by this manufacturing method, the same effect as the semiconductor device according to the present invention can be obtained.

本発明に係る半導体装置及びその製造方法によれば、材料費を低減するとともに生産性を向上することができるという優れた効果を奏する。   According to the semiconductor device and the manufacturing method thereof according to the present invention, there is an excellent effect that the material cost can be reduced and the productivity can be improved.

図１〜３は本発明を具体化した第一実施形態の半導体装置１及びその製造方法を示している。この半導体装置１は、基板２と、該基板２上に上下に積層された２つの半導体素子３，４と、半導体素子３，４のボンディングパッド３ａ，４ａ及び基板２の電極２ａを電気的に接続する金ワイヤ等のワイヤ５と、半導体素子３，４及びワイヤ５を基板２上に封止する樹脂パッケージ６とを備えている。以下、相対的に下側にある半導体素子３を「下側半導体素子３」といい、相対的に上側にある半導体素子４を「上側半導体素子４」という。   1 to 3 show a semiconductor device 1 according to a first embodiment embodying the present invention and a method for manufacturing the same. The semiconductor device 1 electrically connects a substrate 2, two semiconductor elements 3 and 4 stacked on the substrate 2, bonding pads 3 a and 4 a of the semiconductor elements 3 and 4, and an electrode 2 a of the substrate 2. A wire 5 such as a gold wire to be connected and a resin package 6 for sealing the semiconductor elements 3 and 4 and the wire 5 on the substrate 2 are provided. Hereinafter, the relatively lower semiconductor element 3 is referred to as a “lower semiconductor element 3”, and the relatively upper semiconductor element 4 is referred to as an “upper semiconductor element 4”.

下側半導体素子３と上側半導体素子４は、平面視で矩形状に形成されるとともに、その矩形サイズが略同一に形成されている。下側半導体素子３と上側半導体素子４の上面における周縁部には、それぞれボンディングパッド３ａ，４ａが列設されている。このため、平面視で、下側半導体素子３に設けられたボンディングパッド３ａが、上側半導体素子４の下に隠れるように構成されている。そこで、図３（ｂ）に示すように、上側半導体素子の下面における周縁部には、凹所８が設けられている。この凹所８は、下側半導体素子３のボンディングパッド３ａにワイヤ５を接続するための空間Ｓを形成するためのものである。凹所８の形状としては、特に限定されないが、本例では断面略矩形状に形成されている。また、凹所８の位置やサイズは、下側半導体素子３のボンディングパッド３ａのサイズや位置に応じて設定することが好ましい。   The lower semiconductor element 3 and the upper semiconductor element 4 are formed in a rectangular shape in plan view, and the rectangular sizes thereof are substantially the same. Bonding pads 3 a and 4 a are arranged in a row at the peripheral portions on the upper surfaces of the lower semiconductor element 3 and the upper semiconductor element 4. Therefore, the bonding pad 3 a provided on the lower semiconductor element 3 is configured to be hidden under the upper semiconductor element 4 in plan view. Therefore, as shown in FIG. 3B, a recess 8 is provided in the peripheral edge portion of the lower surface of the upper semiconductor element. The recess 8 is for forming a space S for connecting the wire 5 to the bonding pad 3 a of the lower semiconductor element 3. The shape of the recess 8 is not particularly limited, but is formed in a substantially rectangular cross section in this example. Further, the position and size of the recess 8 are preferably set according to the size and position of the bonding pad 3 a of the lower semiconductor element 3.

次に、本半導体装置１の製造方法について説明する。なお、本製造方法のうち、下側半導体素子３に関する部分については、従来の半導体装置１の製造方法と同様であるため、説明を省く。   Next, a method for manufacturing the semiconductor device 1 will be described. In the present manufacturing method, the portion related to the lower semiconductor element 3 is the same as the conventional method for manufacturing the semiconductor device 1, and thus the description thereof is omitted.

（１）図２（ａ）に示すように、半導体ウエハ１０の裏面（回路形成面１０ａの反対側の面）をバックグラインディングすることにより、所定の厚さに形成する。この厚さとしては、特に限定されないが、３００〜４００μｍ程度にすることを例示する（本例では３５０μｍ）。 (1) As shown in FIG. 2A, the back surface of the semiconductor wafer 10 (the surface opposite to the circuit forming surface 10a) is back-grounded to a predetermined thickness. Although it does not specifically limit as this thickness, Illustrating making it about 300-400 micrometers is illustrated (in this example, 350 micrometers).

（２）次いで、赤外線アライメントユニット等（図示略）により、半導体ウエハ１０に形成された回路形成面１０ａにおける切断領域を検出し、図２（ｂ）に示すように、先端が断面矩形に形成された第一のダイヤモンドブレード１１により、半導体ウエハ１０の裏面に網目状に溝入れする。このとき、特に限定されないが、切断幅Ｗ１としては、約５００〜７００μｍ（本例では５００μｍ）、切断深さＤ１としては１００〜２００μｍ（本例では１５０μｍ）とすることを例示する。そして、図２（ｃ）に示すように、回路形成面１０ａ側から、第一のダイヤモンドブレード１１よりも細い切断幅Ｗ２、例えば２０〜４０μｍ程度（本例では４０μｍ）に形成された第二のダイヤモンドブレード１２で、半導体ウエハ１０を個々の半導体素子４に切断分離する。すると、下面の縁部に、幅２３０μｍ、深さ１５０μｍの断面矩形状の凹所８を有する上側半導体素子４が得られる。図３（ａ）は切断された状態の半導体ウエハ１０、同図（ｂ）は切断により分離された一つの上側半導体素子４を示している。これが、下側半導体素子３のボンディングパッド３ａ上にワイヤ５を接続するための空間Ｓを形成する凹所８を、上側半導体素子４の下面に設ける段階である。 (2) Next, a cutting region in the circuit forming surface 10a formed on the semiconductor wafer 10 is detected by an infrared alignment unit or the like (not shown), and the tip is formed in a rectangular cross section as shown in FIG. The first diamond blade 11 is used to form grooves in a mesh shape on the back surface of the semiconductor wafer 10. At this time, although not particularly limited, the cutting width W1 is about 500 to 700 μm (500 μm in this example) and the cutting depth D1 is 100 to 200 μm (150 μm in this example). Then, as shown in FIG. 2 (c), the second width formed from the circuit forming surface 10a side to a cutting width W2 narrower than that of the first diamond blade 11, for example, about 20 to 40 μm (40 μm in this example). The semiconductor wafer 10 is cut and separated into individual semiconductor elements 4 by the diamond blade 12. As a result, the upper semiconductor element 4 having the recess 8 having a rectangular cross section with a width of 230 μm and a depth of 150 μm is obtained at the edge of the lower surface. FIG. 3A shows the semiconductor wafer 10 in a cut state, and FIG. 3B shows one upper semiconductor element 4 separated by cutting. This is a stage in which a recess 8 for forming a space S for connecting the wire 5 on the bonding pad 3 a of the lower semiconductor element 3 is provided on the lower surface of the upper semiconductor element 4.

（３）次いで、図２（ｄ）に示すように、基板２にボンディングされるとともに、基板２の電極２ａとボンディングパッド３ａとがワイヤ５で電気的に接続された状態の下側半導体素子３上に、ダイペースト又はダイ接合用フィルム等の接着手段９によって上側半導体素子４を積層する。これが、ボンディングパッド３ａにワイヤ５を接続した下側半導体素子３の上に上側半導体素子４を積層する段階である。そして、図２（ｅ）に示すように、上側半導体素子４上のボンディングパッド４ａと基板２の電極をワイヤ５で電気的に接続する。なお、３つ以上の半導体素子を積層する場合も、以上と同様の方法により積層する。 (3) Next, as shown in FIG. 2D, the lower semiconductor element 3 is bonded to the substrate 2 and the electrode 2a of the substrate 2 and the bonding pad 3a are electrically connected by the wire 5. On the upper side, the upper semiconductor element 4 is laminated by an adhesive means 9 such as a die paste or a die bonding film. This is a stage in which the upper semiconductor element 4 is laminated on the lower semiconductor element 3 in which the wire 5 is connected to the bonding pad 3a. Then, as shown in FIG. 2 (e), the bonding pads 4 a on the upper semiconductor element 4 and the electrodes of the substrate 2 are electrically connected by wires 5. Note that when three or more semiconductor elements are stacked, they are stacked by the same method as described above.

（４）次いで、図２（ｆ）に示すように、封止樹脂により、基板２上に、半導体素子及びワイヤをパッケージングするように樹脂パッケージ６を形成する。これで半導体装置１が完成する。 (4) Next, as shown in FIG. 2F, a resin package 6 is formed on the substrate 2 with a sealing resin so as to package semiconductor elements and wires. Thus, the semiconductor device 1 is completed.

以上のように構成された本例の半導体装置１及びその製造方法によれば、上側半導体素子４は、その下面におけるボンディングパッド３ａへ対峙する縁部に凹所８が設けられているので、従来とは異なり、上側半導体素子４と下側半導体素子３の間にスペーサーを介在させなくてもよく、材料費を低減するとともに、生産性を向上することができる。   According to the semiconductor device 1 of this example configured as described above and the manufacturing method thereof, the upper semiconductor element 4 is provided with the recess 8 at the edge facing the bonding pad 3a on the lower surface thereof. Unlike the above, it is not necessary to interpose a spacer between the upper semiconductor element 4 and the lower semiconductor element 3, and the material cost can be reduced and the productivity can be improved.

次に、図４は本発明を具体化した第二実施形態を示している。この半導体装置２０及びその製造方法は、以下に示す点において、主に第一実施形態と相違している。従って、同実施形態と共通する部分については、同一符号を付することにより重複説明を省く（以下の他の実施形態についても同様）。   Next, FIG. 4 shows a second embodiment that embodies the present invention. The semiconductor device 20 and the manufacturing method thereof are mainly different from the first embodiment in the following points. Accordingly, parts that are the same as those in the embodiment are given the same reference numerals, and redundant description is omitted (the same applies to the other embodiments below).

本例の半導体装置２０は、図４（ｆ）に示すように、上側半導体素子４の凹所２１付近における応力分散を図るために、該凹所２１付近における形状が急変する部分を減らすようにしている点が、第一実施形態と相違している。具体的には、本例では、上側半導体素子４の周縁部が外側ほど薄くなるように、下面の周縁部をテーパー状に傾斜させ、これにより凹所２１を形成するようにしている。   In the semiconductor device 20 of this example, as shown in FIG. 4 (f), in order to distribute the stress in the vicinity of the recess 21 of the upper semiconductor element 4, the portion where the shape in the vicinity of the recess 21 changes suddenly is reduced. This is different from the first embodiment. Specifically, in this example, the peripheral edge portion of the lower surface is inclined in a tapered shape so that the peripheral edge portion of the upper semiconductor element 4 becomes thinner toward the outer side, thereby forming the recess 21.

この半導体装置２０の製造方法は、図４に示すように、基本的に図２を参照して説明した第一実施形態の製造方法と同様であり、図４（ａ）〜（ｆ）は、図２（ａ）〜（ｆ）にそれぞれ対応している。図４（ｂ）に示すように、半導体ウエハ１０の裏面から先端が断面Ｖ字形のダイヤモンドブレード２５により溝入れする点が第一実施形態と相違している。このときのＶ字形の先端角度Ａ１は１１０〜１５０°（本例では１２０°）、Ｖ字形の先端の切断深さＤ２は２００〜２５０μｍ（本例では２２０μｍ）とすることを例示する。   As shown in FIG. 4, the manufacturing method of the semiconductor device 20 is basically the same as the manufacturing method of the first embodiment described with reference to FIG. 2, and FIGS. These correspond to FIGS. 2A to 2F, respectively. As shown in FIG. 4B, the semiconductor wafer 10 is different from the first embodiment in that the semiconductor wafer 10 is grooved by a diamond blade 25 whose tip is V-shaped in cross section. The V-shaped tip angle A1 at this time is 110 to 150 ° (120 ° in this example), and the cutting depth D2 of the V-shaped tip is 200 to 250 μm (220 μm in this example).

本例によれば、第一実施形態と同様の効果に加え、第一実施形態とは異なり、上側半導体素子４の凹所２１付近における応力分散を図るようにしている。このため、上側半導体素子４の凹所２１付近に外力が作用したとき（例えば、ボンディングパッド４ａへワイヤ５をボンディングしたときや、樹脂パッケージ形成のために封止樹脂を冷却したとき等）に、応力集中が生じ難く、強度が向上する。従って、例えば、上側半導体素子４を、第一実施形態と同等の強度を備えたものにする場合であれば、第一実施形態よりも上側半導体素子４の厚さを薄くすることができ、半導体装置２０をより薄く構成することができる。   According to this example, in addition to the same effect as the first embodiment, unlike the first embodiment, the stress distribution near the recess 21 of the upper semiconductor element 4 is achieved. For this reason, when an external force acts near the recess 21 of the upper semiconductor element 4 (for example, when the wire 5 is bonded to the bonding pad 4a or when the sealing resin is cooled to form the resin package), Stress concentration hardly occurs and the strength is improved. Therefore, for example, if the upper semiconductor element 4 has the same strength as that of the first embodiment, the thickness of the upper semiconductor element 4 can be made thinner than that of the first embodiment. The device 20 can be made thinner.

次に、図５は本発明を具体化した第三実施形態を示している。この半導体装置３０及びその製造方法は、以下に示す点において、主に第二実施形態と相違している。   Next, FIG. 5 shows a third embodiment embodying the present invention. The semiconductor device 30 and the manufacturing method thereof are mainly different from the second embodiment in the following points.

本例の半導体装置３０は、図５（ｆ）に示すように、上側半導体素子４の凹所３１付近における応力分散を図るために、該凹所３１付近における形状が急変する部分を減らすようにしている点は第二実施形態と同様である。具体的には、本例では、第二実施形態よりも大きい傾斜角度でテーパー状に傾斜させてなる傾斜面と、該傾斜面の外縁から略水平に延設してなる平面とにより、下面の周縁部に凹所３１を形成することにより、凹所３１により形成される空間Ｓを広く確保している点が第二実施形態と相違している。   In the semiconductor device 30 of this example, as shown in FIG. 5 (f), in order to distribute the stress in the vicinity of the recess 31 of the upper semiconductor element 4, the portion where the shape in the vicinity of the recess 31 changes suddenly is reduced. This is the same as in the second embodiment. Specifically, in this example, the lower surface is formed by an inclined surface that is inclined in a tapered manner at a larger inclination angle than in the second embodiment, and a plane that extends substantially horizontally from the outer edge of the inclined surface. The difference between the second embodiment and the second embodiment is that a space S formed by the recess 31 is widely secured by forming the recess 31 at the peripheral edge.

この半導体装置３０の製造方法は、図５に示すように、基本的に図４を参照して説明した第二実施形態の製造方法と同様であり、図５（ａ）〜（ｆ）は、図４（ａ）〜（ｆ）にそれぞれ対応している。図５（ｂ）に示すように、半導体ウエハ１０の裏面から先端が断面台形のダイヤモンドブレード３５により溝入れする点が第二実施形態と相違している。このときの台形の先端側の幅Ｗ３は２００〜４００μｍ（本例では２００μｍ）、水平面に対する斜面の傾斜角度Ａ２は、３０〜４０°（本例では３０°）、台形の先端の切断深さＤ３は２００〜２５０μｍ（本例では２００μｍ）とすることを例示する。   As shown in FIG. 5, the manufacturing method of the semiconductor device 30 is basically the same as the manufacturing method of the second embodiment described with reference to FIG. 4, and FIGS. These correspond to FIGS. 4A to 4F, respectively. As shown in FIG. 5B, the semiconductor wafer 10 is different from the second embodiment in that the semiconductor wafer 10 is grooved by a diamond blade 35 having a trapezoidal cross section at the tip. At this time, the width W3 on the tip side of the trapezoid is 200 to 400 μm (200 μm in this example), the inclination angle A2 of the slope with respect to the horizontal plane is 30 to 40 ° (30 ° in this example), and the cutting depth D3 of the trapezoid tip. Is 200 to 250 μm (200 μm in this example).

本例によれば、第二実施形態と同様の効果に加え、凹所３１により形成される空間Ｓを第二実施形態よりも広く確保することができる。   According to this example, in addition to the effect similar to 2nd embodiment, the space S formed by the recess 31 can be ensured wider than 2nd embodiment.

次に、図６は本発明を具体化した第四実施形態を示している。この半導体装置４０及びその製造方法は、以下に示す点において、主に第二実施形態と相違している。   Next, FIG. 6 shows a fourth embodiment that embodies the present invention. This semiconductor device 40 and its manufacturing method are mainly different from the second embodiment in the following points.

本例の半導体装置４０は、図６（ｆ）に示すように、上側半導体素子４の下面の縁部に断面凹円弧形の凹所４１が設けられている点が第二実施形態と相違している。   The semiconductor device 40 of this example is different from the second embodiment in that a recess 41 having a concave arc shape in cross section is provided at the edge of the lower surface of the upper semiconductor element 4 as shown in FIG. doing.

この半導体装置４０の製造方法は、図６に示すように、基本的に図４を参照して説明した第二実施形態の製造方法と同様であり、図６（ａ）〜（ｆ）は、図４（ａ）〜（ｆ）にそれぞれ対応している。図６（ｂ）に示すように、半導体ウエハ１０の裏面から先端が断面略半円形のダイヤモンドブレード４５により溝入れする点が第一実施形態と相違している。このときの円弧Ｒの半径は２５０〜３００μｍ（本例では２５０μｍ）、切断深さＤ４は２５０〜３００μｍ（本例では２５０μｍ）とすることを例示する。   The manufacturing method of the semiconductor device 40 is basically the same as the manufacturing method of the second embodiment described with reference to FIG. 4 as shown in FIG. 6, and FIGS. These correspond to FIGS. 4A to 4F, respectively. As shown in FIG. 6B, the semiconductor wafer 10 is different from the first embodiment in that the semiconductor wafer 10 is grooved by a diamond blade 45 whose tip is substantially semicircular in cross section. In this case, the radius of the arc R is 250 to 300 μm (250 μm in this example), and the cutting depth D4 is 250 to 300 μm (250 μm in this example).

本例によれば、第二実施形態と同様の効果に加え、凹所４１が断面凹円弧形に形成されているので、該凹所４１により形成される空間Ｓを第二実施形態よりも広く確保することができる。   According to this example, in addition to the same effects as in the second embodiment, the recess 41 is formed in a concave arc shape in cross section, so that the space S formed by the recess 41 is more than in the second embodiment. Widely secured.

なお、本発明は前記実施形態に限定されるものではなく、例えば以下のように、発明の趣旨から逸脱しない範囲で適宜変更して具体化することもできる。
（１）他の形態の半導体装置に使用すること。
（２）凹所の形状、位置、サイズ等を適宜変更すること。
（３）上下の半導体素子３，４の形状やサイズが互いに異なるように構成すること。
（４）３つ以上の半導体素子を積層した構成とすること。 In addition, this invention is not limited to the said embodiment, For example, it can also be suitably changed and embodied as follows, for example in the range which does not deviate from the meaning of invention.
(1) Use for other types of semiconductor devices.
(2) Change the shape, position, size, etc. of the recess as appropriate.
(3) The upper and lower semiconductor elements 3 and 4 are configured to have different shapes and sizes.
(4) A configuration in which three or more semiconductor elements are stacked.

本発明を具体化した第一実施形態に係る半導体装置の一部破断斜視図である。1 is a partially broken perspective view of a semiconductor device according to a first embodiment embodying the present invention. 同半導体装置及びその製造方法を示す断面図である。2 is a cross-sectional view showing the same semiconductor device and a method for manufacturing the same. FIG. 同半導体装置の半導体素子を下側から見た斜視図であり、（ａ）は半導体ウエハをダイシングすることにより得られた複数の半導体素子の図、（ｂ）は単体の半導体素子の図である。FIG. 2 is a perspective view of the semiconductor element of the semiconductor device as viewed from below, where (a) is a diagram of a plurality of semiconductor elements obtained by dicing a semiconductor wafer, and (b) is a diagram of a single semiconductor element. . 本発明を具体化した第二実施形態に係る半導体装置及びその製造方法を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on 2nd embodiment which actualized this invention, and its manufacturing method. 本発明を具体化した第三実施形態に係る半導体装置及びその製造方法を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on 3rd embodiment which actualized this invention, and its manufacturing method. 本発明を具体化した第四実施形態に係る半導体装置及びその製造方法を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on 4th embodiment which actualized this invention, and its manufacturing method. 従来の半導体装置を示す断面図である。It is sectional drawing which shows the conventional semiconductor device. 従来の別の半導体装置を示す断面図である。It is sectional drawing which shows another conventional semiconductor device.

符号の説明Explanation of symbols

１ 半導体装置
２ 基板
２ａ 電極
３ 下側半導体素子
３ａ ボンディングパッド
４ 上側半導体素子
４ａ ボンディングパッド
５ ワイヤ
６ 樹脂パッケージ
８ 凹所
１０ 半導体ウエハ
１０ａ 回路形成面
２０ 半導体装置
２１ 凹所
３０ 半導体装置
３１ 凹所
４０ 半導体装置
４１ 凹所
Ｓ 空間 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Board | substrate 2a Electrode 3 Lower semiconductor element 3a Bonding pad 4 Upper semiconductor element 4a Bonding pad 5 Wire 6 Resin package 8 Recess 10 Semiconductor wafer 10a Circuit formation surface 20 Semiconductor device 21 Recess 30 Semiconductor device 31 Recess 40 Semiconductor device 41 Recess S Space

Claims (3)

上下に積層された複数の半導体素子を含み、相対的に下側にある半導体素子である下側半導体素子に形成されたボンディングパッドが、相対的に上側にある半導体素子である上側半導体素子の下に隠れるように構成された半導体装置であって、
前記上側半導体素子は、その下面に、前記下側半導体素子の前記ボンディングパッドにワイヤを接続するための空間を形成する凹所が設けられた半導体装置。 The bonding pad formed on the lower semiconductor element, which is a relatively lower semiconductor element, includes a plurality of semiconductor elements stacked one above the other. A semiconductor device configured to be hidden by
The upper semiconductor element is a semiconductor device in which a recess for forming a space for connecting a wire to the bonding pad of the lower semiconductor element is provided on the lower surface thereof. 前記下側半導体素子及び前記上側半導体素子は、平面視のサイズが略同一に形成されており、
前記下側半導体素子は、その上面の縁部に前記ボンディングパッドが配設されており、
前記上側半導体素子は、その下面における前記ボンディングパッドへ対峙する縁部に前記凹所が設けられている
請求項１記載の半導体装置。 The lower semiconductor element and the upper semiconductor element are formed to have substantially the same size in plan view,
The lower semiconductor element has the bonding pad disposed on the edge of the upper surface thereof,
The semiconductor device according to claim 1, wherein the upper semiconductor element is provided with the recess at an edge portion of the lower surface facing the bonding pad. 上下に積層された複数の半導体素子を含み、相対的に下側にある半導体素子である下側半導体素子に形成されたボンディングパッドが、相対的に上側にある半導体素子である上側半導体素子の下に隠れるように構成された半導体装置の製造方法であって、
前記下側半導体素子の前記ボンディングパッド上にワイヤを接続するための空間を形成する凹所を、前記上側半導体素子の下面に設ける段階と、
前記ボンディングパッドに前記ワイヤが接続された前記下側半導体素子の上に前記上側半導体素子を積層する段階と
を含む半導体装置の製造方法。
The bonding pad formed on the lower semiconductor element, which is a relatively lower semiconductor element, includes a plurality of semiconductor elements stacked one above the other. A method of manufacturing a semiconductor device configured to be hidden by
Providing a recess for forming a space for connecting a wire on the bonding pad of the lower semiconductor element on the lower surface of the upper semiconductor element;
Laminating the upper semiconductor element on the lower semiconductor element in which the wire is connected to the bonding pad.
JP2003330427A 2003-09-22 2003-09-22 Semiconductor device and its manufacturing method Pending JP2005101106A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003330427A JP2005101106A (en) 2003-09-22 2003-09-22 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003330427A JP2005101106A (en) 2003-09-22 2003-09-22 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2005101106A true JP2005101106A (en) 2005-04-14

Family

ID=34459399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003330427A Pending JP2005101106A (en) 2003-09-22 2003-09-22 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2005101106A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101118719B1 (en) * 2008-06-30 2012-03-13 샌디스크 코포레이션 Stacked semiconductor package with localized cavities for wire bonding and method of fabricating the same
US8294251B2 (en) 2008-06-30 2012-10-23 Sandisk Technologies Inc. Stacked semiconductor package with localized cavities for wire bonding
US8470640B2 (en) 2008-06-30 2013-06-25 Sandisk Technologies Inc. Method of fabricating stacked semiconductor package with localized cavities for wire bonding

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101118719B1 (en) * 2008-06-30 2012-03-13 샌디스크 코포레이션 Stacked semiconductor package with localized cavities for wire bonding and method of fabricating the same
US8294251B2 (en) 2008-06-30 2012-10-23 Sandisk Technologies Inc. Stacked semiconductor package with localized cavities for wire bonding
US8470640B2 (en) 2008-06-30 2013-06-25 Sandisk Technologies Inc. Method of fabricating stacked semiconductor package with localized cavities for wire bonding

Similar Documents

Publication Publication Date Title
JP5529371B2 (en) Semiconductor device and manufacturing method thereof
JP4867990B2 (en) Memory card
JP2005197491A (en) Semiconductor device
JP6535509B2 (en) Semiconductor device
JP4495916B2 (en) Manufacturing method of semiconductor chip
JP2009064854A (en) Lead frame, semiconductor device, and manufacturing method of semiconductor device
JP2008053290A (en) Optical semiconductor device and its manufacturing method
JP5974595B2 (en) Semiconductor sensor and manufacturing method thereof
JP2002141459A (en) Semiconductor device and its manufacturing method
JP5295146B2 (en) Power semiconductor device and manufacturing method thereof
JP4058637B2 (en) Semiconductor chip, semiconductor device, circuit board, and electronic equipment
JP2005101106A (en) Semiconductor device and its manufacturing method
CN110635011A (en) Chip flexible packaging structure and preparation method thereof
US7696619B2 (en) Stack combination of plural chip package units
JP5546363B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2006173416A (en) Semiconductor device
EP3176841B1 (en) Chip substrate
JP2007141947A (en) Semiconductor device and its manufacturing method
JP2007103804A (en) Semiconductor laser device
JP2005026630A (en) Semiconductor device and its manufacturing method
JP4579941B2 (en) Semiconductor device and semiconductor device manufacturing method
JP2004363224A (en) Connection structure of semiconductor chip
JP2004228142A (en) Semiconductor element and multi-chip package
JP2008091734A (en) Semiconductor device, and its manufacturing method
JP4808540B2 (en) Semiconductor wafer