JP2005026630A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2005026630A
JP2005026630A JP2003270820A JP2003270820A JP2005026630A JP 2005026630 A JP2005026630 A JP 2005026630A JP 2003270820 A JP2003270820 A JP 2003270820A JP 2003270820 A JP2003270820 A JP 2003270820A JP 2005026630 A JP2005026630 A JP 2005026630A
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bump
semiconductor chip
semiconductor device
chip
electrode pad
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Takaya Kuroda
隆哉 黒田
Yoichiro Kurita
洋一郎 栗田
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NEC Electronics Corp
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NEC Electronics Corp
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip-on-chip semiconductor device in which the variations of the bonding strength is reduced, and provide its manufacturing method. <P>SOLUTION: A bump 4 rectangular in a plane view, is formed on a chip connecting electrode pad 3 provided on the surface of a semiconductor chip 1, and a bump 5 rectangular in a plane view, is formed on a chip connecting electrode pad 3 that is provided on the surface of a semiconductor chip 2. The bumps 4 and 5 are then bonded to cross each other. An external terminal connecting electrode pad 7 of the semiconductor chip 1 and a wiring board 8 are connected by a bonding wire 9 thereafter, and the semiconductor chip 1 and an external terminal are connected. Further, the gap between the semiconductor chip 1 and the semiconductor chip 2 is filled with resin 6 and then sealed to obtain a chip-on-chip semiconductor device. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体チップに他の半導体チップが重ね合わせて接合されたチップ・オン・チップ型の半導体装置及びその製造方法に関する。   The present invention relates to a chip-on-chip type semiconductor device in which another semiconductor chip is overlapped and bonded to a semiconductor chip and a method for manufacturing the same.

近時、半導体装置を高密度化するために、半導体チップに他の半導体チップを重ね合わせて接合する半導体装置、即ち、ＣＯＣ（Chip On Chip；チップ・オン・チップ）型の半導体装置が検討されている（例えば、特許文献１及び２参照）。図９（ａ）乃至（ｃ）は従来のＣＯＣ型半導体装置の製造方法を示す平面図である。   Recently, in order to increase the density of a semiconductor device, a semiconductor device in which another semiconductor chip is overlapped and bonded to a semiconductor chip, that is, a COC (Chip On Chip) type semiconductor device has been studied. (For example, see Patent Documents 1 and 2). 9A to 9C are plan views showing a conventional method for manufacturing a COC type semiconductor device.

従来のＣＯＣ型半導体装置においては、例えば、外周部に複数個の外部端子接続用電極パッド７が形成され、外部端子接続用電極パッド７より内側に複数個のチップ接続用電極パッドが形成された半導体チップ１と、この半導体チップ１より小さく、外周部に複数個のチップ接続用電極パッドが形成されている半導体チップ２とが使用される。この半導体チップ１及び半導体チップ２におけるチップ接続用電極パッドは、その数、形状及び配置が等しくなるように形成されている。そして、図９（ａ）及び（ｂ）に示すように、半導体チップ１及び半導体チップ２のチップ接続用電極パッド上には、めっき法等によりチップ接続用電極パッドと同じ形状のバンプ４及びバンプ５が形成されている。このような半導体チップ１及び半導体チップ２は、図９（ｃ）に示すように、バンプが形成されている面同士を対向させて、バンプ４とバンプ５とを接合することにより、チップ１とチップ２とが相互に接続されている。   In the conventional COC type semiconductor device, for example, a plurality of external terminal connection electrode pads 7 are formed on the outer periphery, and a plurality of chip connection electrode pads are formed inside the external terminal connection electrode pads 7. A semiconductor chip 1 and a semiconductor chip 2 smaller than the semiconductor chip 1 and having a plurality of chip connection electrode pads formed on the outer periphery thereof are used. The chip connecting electrode pads in the semiconductor chip 1 and the semiconductor chip 2 are formed so as to have the same number, shape and arrangement. 9A and 9B, bumps 4 and bumps having the same shape as the chip connection electrode pads are formed on the chip connection electrode pads of the semiconductor chip 1 and the semiconductor chip 2 by plating or the like. 5 is formed. As shown in FIG. 9C, the semiconductor chip 1 and the semiconductor chip 2 are bonded to the bump 4 and the bump 5 with the surfaces on which the bumps are formed facing each other. The chip 2 is connected to each other.

特開２００１−１５５５３号公報 （第３頁、第１図）JP 2001-15553 A (page 3, FIG. 1) 特開２００１−９３９３１号公報 （第３−４頁、第１図）JP 2001-93931 A (page 3-4, FIG. 1)

しかしながら、上述の従来の技術には以下に示す問題点がある。図１０（ａ）は従来のＣＯＣ型半導体装置におけるバンプの接合状態を示す模式図であり、図１０（ｂ）及び（ｃ）はその中の１つを示す拡大模式図である。図１０（ａ）に示すように、従来の方法で製造されたＣＯＣ型半導体装置においては、バンプ同士を接合する際に、接合位置が角度θ程度斜めにずれることがある。従来の半導体装置のバンプは一般に正方形状であるため、図１０（ｂ）に示すずれが少ないバンプ４ａ及びバンプ５ａと、図１０（ｃ）に示すずれが大きいバンプ４ｂ及びバンプ５ｂとでは、位置ずれした分だけ接合部１０の面積に差が生じるという問題点がある。同一チップ内において各バンプの接合面積が異なると、半導体チップ間の接合強度がばらつく。   However, the conventional techniques described above have the following problems. FIG. 10A is a schematic diagram showing a bonding state of bumps in a conventional COC type semiconductor device, and FIGS. 10B and 10C are enlarged schematic diagrams showing one of them. As shown in FIG. 10A, in the COC type semiconductor device manufactured by the conventional method, when the bumps are bonded to each other, the bonding position may be shifted obliquely by an angle θ. Since the bumps of the conventional semiconductor device are generally square, the positions of the bump 4a and the bump 5a with a small shift shown in FIG. 10B and the bump 4b and the bump 5b with a large shift shown in FIG. There is a problem that a difference occurs in the area of the joint portion 10 by the amount of displacement. If the bonding area of each bump is different in the same chip, the bonding strength between the semiconductor chips varies.

本発明はかかる問題点に鑑みてなされたものであって、接合強度にばらつきが少ないチップ・オン・チップ型の半導体装置及びその製造方法を提供することを目的とする。   The present invention has been made in view of such problems, and an object thereof is to provide a chip-on-chip type semiconductor device with little variation in bonding strength and a method for manufacturing the same.

本願第１発明に係る半導体装置は、第１の半導体チップの表面に設けられた電極パッド上に形成された第１のバンプと、第２の半導体チップの表面に設けられた電極パッド上に形成された第２のバンプとが接合されている半導体装置において、前記第１のバンプ及び前記第２のバンプは、平面視で長方形状をなし、前記第１のバンプと前記第２のバンプとが交差するように接合されていることを特徴とする。   A semiconductor device according to the first invention of the present application is formed on a first bump formed on an electrode pad provided on a surface of a first semiconductor chip and an electrode pad provided on a surface of a second semiconductor chip. In the semiconductor device in which the second bump is bonded, the first bump and the second bump have a rectangular shape in plan view, and the first bump and the second bump are It is characterized by being joined so as to intersect.

本発明においては、電極パッド上に形成されたパッドが平面視で長方形状であり、互いに交差するように接合されている。これにより、バンプ接合時に位置ずれを生じても、互いのバンプ幅分の接合面積を確保することができるため、接合面積が常に一定になる。その結果、バンプ接合強度のばらつきが低減される。また、本発明においては、電極パッド全面にバンプを形成していないため、電極パッドの幅を従来の半導体装置より狭くすることができ、これにより、電極パッドピッチを狭くすることができる。   In the present invention, the pads formed on the electrode pads have a rectangular shape in plan view and are joined so as to cross each other. Thereby, even if a positional shift occurs during bump bonding, a bonding area corresponding to each bump width can be secured, so that the bonding area is always constant. As a result, variation in bump bonding strength is reduced. Further, in the present invention, since no bump is formed on the entire surface of the electrode pad, the width of the electrode pad can be made narrower than that of the conventional semiconductor device, and thereby the electrode pad pitch can be reduced.

本願第２発明に係る半導体装置は、第１の半導体チップの表面に設けられた電極パッド上に形成された第１のバンプと、第２の半導体チップの表面に設けられた電極パッド上に形成された第２のバンプとが接合されている半導体装置において、前記第１のバンプ及び前記第２のバンプは、平面視で平行四辺形状をなし、前記第１のバンプと前記第２のバンプとが交差するように接合されていることを特徴とする。   A semiconductor device according to a second invention of the present application is formed on a first bump formed on an electrode pad provided on a surface of a first semiconductor chip and an electrode pad provided on a surface of a second semiconductor chip. In the semiconductor device bonded to the second bump, the first bump and the second bump have a parallelogram shape in plan view, and the first bump and the second bump Are joined so as to cross each other.

本発明においては、電極パッド上に形成されたパッドが平面視で平行四辺形状であり、互いに交差するように接合されている。これにより、バンプ接合時に位置ずれが生じても、接合面積を一定にすることができるため、半導体チップ内におけるバンプ接合強度が均一になる。また、平面視でのバンプ形状における長辺と短辺とがなす角度を大きくすると、電極パッドの幅を狭くすることができるため、電極パッドピッチを狭くすることができる。   In the present invention, the pads formed on the electrode pads have a parallelogram shape in plan view and are joined so as to cross each other. Thereby, even if a positional shift occurs at the time of bump bonding, the bonding area can be made constant, so that the bump bonding strength in the semiconductor chip becomes uniform. Further, when the angle formed by the long side and the short side in the bump shape in plan view is increased, the width of the electrode pad can be reduced, so that the electrode pad pitch can be reduced.

前記半導体装置は、前記第１のバンプは１又は複数群毎にそれに属する複数個のバンプが相互に平行であり、前記第２のバンプは１又は複数群毎にそれに属する複数個のバンプが相互に平行であって、前記第１及び第２のバンプは各群毎に対応するもの同士が接合されていることが好ましい。また、前記第２の半導体チップが接合された前記第１の半導体チップは、基板上に実装され、更に封止されていてもよい。更に、前記第１の半導体チップと前記第２の半導体チップとの間には樹脂を充填することもできる。   In the semiconductor device, the first bump has a plurality of bumps belonging to one or a plurality of groups parallel to each other, and the second bump has a plurality of bumps belonging to the one or a plurality of groups mutually. It is preferable that the first and second bumps corresponding to each group are bonded to each other. The first semiconductor chip to which the second semiconductor chip is bonded may be mounted on a substrate and further sealed. Further, a resin can be filled between the first semiconductor chip and the second semiconductor chip.

本願第３発明に係る半導体装置の製造方法は、第１の半導体チップの表面に設けられた電極パッド上に第１のバンプを形成する工程と、第２の半導体チップの表面に設けられた電極パッド上に第２のバンプを形成する工程と、前記第１のバンプと前記第２のバンプとが交差するように前記第１のバンプと前記第２のバンプとを接合する工程と、を有し、前記第１のバンプ及び前記第２のバンプは、平面視で平行四辺形状をなすことを特徴とする。   According to a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first bump on an electrode pad provided on a surface of a first semiconductor chip; and an electrode provided on a surface of a second semiconductor chip. Forming a second bump on the pad, and bonding the first bump and the second bump so that the first bump and the second bump intersect. The first bump and the second bump have a parallelogram shape in plan view.

本発明においては、平面視で長方形状をなすバンプを、互いに交差するように接合するため、半導体チップを重ね合わせる際に位置ずれが生じても、バンプ同士の接合面積を一定にすることができる。これにより、接合強度のばらつきが少なくなるため、歩留まりが向上する。また、半導体チップ同士を接合する際の位置決めが容易になるため、生産性が向上する。   In the present invention, the bumps having a rectangular shape in plan view are joined so as to cross each other, so that even if a positional deviation occurs when the semiconductor chips are overlapped, the joining area between the bumps can be made constant. . As a result, variations in bonding strength are reduced, and yield is improved. Further, since the positioning at the time of joining the semiconductor chips becomes easy, the productivity is improved.

本願第４発明に係る半導体装置の製造方法は、第１の半導体チップの表面に設けられた電極パッド上に第１のバンプを形成する工程と、第２の半導体チップの表面に設けられた電極パッド上に第２のバンプを形成する工程と、前記第１のバンプと前記第２のバンプとが交差するように前記第１のバンプと前記第２のバンプとを接合する工程と、を有し、前記第１のバンプ及び前記第２のバンプは、平面視で平行四辺形状をなすことを特徴とする。   According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first bump on an electrode pad provided on a surface of a first semiconductor chip; and an electrode provided on a surface of a second semiconductor chip. Forming a second bump on the pad, and bonding the first bump and the second bump so that the first bump and the second bump intersect. The first bump and the second bump have a parallelogram shape in plan view.

本発明においては、平面視で平行四辺形状をなすバンプを、互いに交差するように接合するため、半導体チップを接合する際に位置ずれが生じても、バンプ同士の接合面積を一定にすることができる。これにより、接合強度が均一になるため、歩留まりが向上する。   In the present invention, the bumps having a parallelogram shape in plan view are joined so as to cross each other, so that even if a positional deviation occurs when joining the semiconductor chips, the joining area between the bumps can be made constant. it can. Thereby, since the bonding strength becomes uniform, the yield is improved.

本発明によれば、半導体チップ同士を接続するバンプの平面視での形状を長方形状又は平行四辺形状とし、一方の半導体チップに形成されたバンプと他方の半導体チップに形成されたバンプとが交差するように接合することにより、半導体チップ同士を重ね合わせる際に位置ずれが生じても、バンプ同士の接合面積は一定になるため、接合強度のばらつきを低減することができる。   According to the present invention, the shape of the bump connecting the semiconductor chips in a plan view is rectangular or parallelogram, and the bump formed on one semiconductor chip and the bump formed on the other semiconductor chip intersect. By bonding in such a manner, even if a positional shift occurs when the semiconductor chips are overlapped with each other, the bonding area between the bumps is constant, so that variation in bonding strength can be reduced.

以下、本発明の実施形態に係る半導体装置について、添付の図面を参照して具体的に説明する。図１は本実施形態の半導体装置を示す断面図である。図１に示すように、本実施形態の半導体装置は、配線基板８上に、半導体チップ１及び半導体チップ２の２つの半導体チップが実装されてパッケージングされたものであり、半導体チップ１上に半導体チップ２がフェースダウン方式で搭載されているＣＯＣ型の半導体装置である。   Hereinafter, a semiconductor device according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing the semiconductor device of this embodiment. As shown in FIG. 1, the semiconductor device of the present embodiment is obtained by mounting and packaging two semiconductor chips, a semiconductor chip 1 and a semiconductor chip 2, on a wiring substrate 8. This is a COC type semiconductor device in which the semiconductor chip 2 is mounted in a face-down manner.

図２（ａ）は図１に示す半導体チップ１を示す平面図であり、図２（ｂ）は図１に示す半導体チップ２を示す平面図である。図２（ａ）に示すように、半導体チップ１は、その中央部に半導体チップ２と接続するためのチップ接続用電極パッド３が設けられ、外周部には外部端子に接続するための外部端子接続用電極パッド７が設けられている。これらのチップ接続用電極パッド３及び外部端子接続用電極パッド７は、共に正方形状である。そして、チップ接続用電極パッド３上には、半導体チップ１と半導体チップ２とを接続するバンプ１４が形成されている。このバンプ１４は、チップ接続用電極パッド３の表面に垂直な方向から見た形状、即ち、平面視が長方形状であり、各バンプ１４が相互に平行になるように形成されている。   2A is a plan view showing the semiconductor chip 1 shown in FIG. 1, and FIG. 2B is a plan view showing the semiconductor chip 2 shown in FIG. As shown in FIG. 2A, the semiconductor chip 1 is provided with a chip connection electrode pad 3 for connection to the semiconductor chip 2 at the center thereof, and an external terminal for connection to an external terminal at the outer peripheral portion. Connection electrode pads 7 are provided. Both the chip connection electrode pad 3 and the external terminal connection electrode pad 7 have a square shape. A bump 14 for connecting the semiconductor chip 1 and the semiconductor chip 2 is formed on the chip connection electrode pad 3. The bumps 14 have a shape viewed from a direction perpendicular to the surface of the chip connection electrode pad 3, that is, a rectangular shape in plan view, and are formed so that the bumps 14 are parallel to each other.

また、図２（ｂ）に示すように、半導体チップ２は、その外周部に半導体チップ１と接続するためのチップ接続用電極パッド３が形成されている。このチップ接続用電極パッド３も、前述の半導体チップ１と同様に正方形状であり、その上には、半導体チップ１と半導体チップ２とを接続するバンプ１５が形成されている。このバンプ１５の平面視での形状は、前述の半導体チップ１と同様に長方形状であり、各バンプ１５が相互に平行になるように形成されている。   Further, as shown in FIG. 2B, the semiconductor chip 2 has chip connection electrode pads 3 for connection to the semiconductor chip 1 formed on the outer periphery thereof. The chip connection electrode pad 3 has a square shape like the semiconductor chip 1 described above, and bumps 15 for connecting the semiconductor chip 1 and the semiconductor chip 2 are formed thereon. The shape of the bump 15 in a plan view is a rectangular shape like the semiconductor chip 1 described above, and the bumps 15 are formed so as to be parallel to each other.

更に、前述のバンプ１４及びバンプ１５は、接合されるバンプ同士が交差するように形成されている。これらのバンプ１４及びバンプ１５の材質としては、例えば、Ａｕ又は半田等を使用することができ、その形成方法としては、例えば、めっき法等が適用可能である。   Further, the bumps 14 and 15 described above are formed so that the bumps to be joined cross each other. As a material of these bumps 14 and 15, for example, Au or solder can be used, and as a forming method thereof, for example, a plating method or the like can be applied.

本実施形態の半導体装置においては、バンプ形成面が対向するように半導体チップ１及び半導体チップ２を重ね合わせて、バンプ１４とバンプ１５とが接合されている。これにより、半導体チップ１と半導体チップ２とが相互に接続され、チップ間の信号のやり取りが行われる。図３（ａ）は本実施形態における半導体チップの接合状態を示す平面図であり、図３（ｂ）は図３（ａ）のバンプ接合状態を示す模式図である。図３（ａ）及び（ｂ）に示すように、本実施形態の半導体装置においては、バンプ１４とバンプ１５とが交差するように接合されている。   In the semiconductor device of the present embodiment, the semiconductor chip 1 and the semiconductor chip 2 are overlapped so that the bump formation surfaces face each other, and the bumps 14 and the bumps 15 are joined. As a result, the semiconductor chip 1 and the semiconductor chip 2 are connected to each other, and signals are exchanged between the chips. FIG. 3A is a plan view showing the bonding state of the semiconductor chip in the present embodiment, and FIG. 3B is a schematic diagram showing the bump bonding state of FIG. As shown in FIGS. 3A and 3B, in the semiconductor device of this embodiment, the bumps 14 and the bumps 15 are joined so as to intersect.

また、半導体チップ１の外部端子接続用電極パッド７と配線基板８とは、ボンディングワイヤ９により結線されており、これにより、半導体チップ１と外部端子とが接続されている。更に、半導体チップ１と半導体チップ２との隙間には樹脂６が充填されている。   Further, the external terminal connection electrode pads 7 of the semiconductor chip 1 and the wiring substrate 8 are connected by bonding wires 9, whereby the semiconductor chip 1 and the external terminals are connected. Further, the gap between the semiconductor chip 1 and the semiconductor chip 2 is filled with a resin 6.

次に、本実施形態の変形例に係る半導体装置について説明する。図４（ａ）は本変形例における半導体チップ１を示す平面図であり、図４（ｂ）は本変形例における半導体チップ２を示す平面図である。図４（ａ）及び（ｂ）に示すように、本変形例の半導体装置においては、チップ接続用電極パッド３上に、平面視で平行四辺形状をなすバンプ２４及びバンプ２５が形成されている。そして、これらのバンプ２４及びバンプ２５は、半導体チップの各辺に対応する各群に属する複数個のバンプは相互に平行になるように形成されている。図５（ａ）は本変形例における半導体チップの接合状態を示す平面図であり、図５（ｂ）は図５（ａ）のバンプ接合状態を示す模式図である。図５（ａ）及び（ｂ）に示すように、本変形例の半導体装置においては、バンプ２４とバンプ２５とが交差するように接合されており、これにより、半導体チップ１と半導体チップ２とが接続されている。   Next, a semiconductor device according to a modification of this embodiment will be described. FIG. 4A is a plan view showing the semiconductor chip 1 in this modification, and FIG. 4B is a plan view showing the semiconductor chip 2 in this modification. As shown in FIGS. 4A and 4B, in the semiconductor device of this modification, bumps 24 and bumps 25 having a parallelogram shape in plan view are formed on the chip connection electrode pad 3. . The bumps 24 and the bumps 25 are formed such that a plurality of bumps belonging to each group corresponding to each side of the semiconductor chip are parallel to each other. FIG. 5A is a plan view showing the bonding state of the semiconductor chip in this modification, and FIG. 5B is a schematic diagram showing the bump bonding state of FIG. 5A. As shown in FIGS. 5A and 5B, in the semiconductor device of this modification, the bumps 24 and the bumps 25 are joined so as to intersect with each other, whereby the semiconductor chip 1 and the semiconductor chip 2 are bonded to each other. Is connected.

本実施形態の半導体装置においては、バンプを平面視で長方形状又は平行四辺形状をなす形状とし、一方の半導体チップに形成されたバンプと他方の半導体チップに形成されたバンプとが交差するように接合する。これにより、バンプ接合時に位置ずれが生じても、互いのバンプ幅分の接合面積を確保できるため、接合面積を常に一定にすることができる。その結果、１つの半導体チップ内におけるバンプ接合強度のばらつきを抑えることができる。   In the semiconductor device of the present embodiment, the bumps are formed in a rectangular shape or a parallelogram shape in plan view so that the bumps formed on one semiconductor chip and the bumps formed on the other semiconductor chip intersect. Join. Thereby, even if a positional shift occurs at the time of bump bonding, a bonding area corresponding to each bump width can be secured, so that the bonding area can always be made constant. As a result, it is possible to suppress variations in the bump bonding strength within one semiconductor chip.

図６（ａ）は本発明の実施形態の変形例におけるバンプの接合状態を示す模式図であり、図６（ｂ）及び図６（ｃ）は図６（ａ）に示すバンプの中の１つを示す拡大模式図である。図６（ａ）に示すように、本変形例の半導体装置は、バンプ同士を接合する際にずれが生じた場合においても、図６（ｂ）に示すずれが少ないバンプ２４ａ及びバンプ２５ａの接合部２０の面積、及び図６（ｃ）に示すずれが大きいバンプ２４ｂ及びバンプ２５ｂの接合部２０の面積はほぼ同等である。この効果は、平面視で長方形状をなす形状のバンプにおいても同様である。   FIG. 6A is a schematic diagram showing a bonding state of bumps in a modified example of the embodiment of the present invention, and FIGS. 6B and 6C show one of the bumps shown in FIG. FIG. As shown in FIG. 6A, the semiconductor device of this modification example is bonded to the bump 24a and the bump 25a shown in FIG. 6B with little deviation even when deviation occurs when the bumps are joined to each other. The area of the part 20 and the area of the joint part 20 of the bump 24b and the bump 25b with large deviation shown in FIG. 6C are substantially equal. This effect is the same for a bump having a rectangular shape in plan view.

また、一般に、電極パッド間の距離は、バンプ接合時の位置精度により決定されるため、バンプの形状とは関係なく一定である。本実施形態の半導体装置においては、平面視でのバンプ形状が長方形状又は平行四辺形状であるため、電極パッドの幅を従来の正方形状のパッドに比べて狭くすることができる。このため、電極パッドの幅及び電極パッド間の距離により決定される電極パッドピッチを狭くすることができる。   In general, since the distance between the electrode pads is determined by the positional accuracy at the time of bump bonding, it is constant regardless of the shape of the bump. In the semiconductor device of this embodiment, since the bump shape in plan view is a rectangular shape or a parallelogram shape, the width of the electrode pad can be made narrower than that of a conventional square pad. For this reason, the electrode pad pitch determined by the width of the electrode pads and the distance between the electrode pads can be reduced.

図７は本発明の実施形態の変形例における電極パッドピッチの狭ピッチ化を示す模式図である。図７に示すように、正方形状の電極パッド３０に平面視で平行四辺形状をなすバンプ３１を形成した場合、電極パッドピッチＡ１は、電極パッド３０の幅Ｐ１と隣り合う電極パッド３０間の距離Ｓとの和で表される。このとき、隣り合う電極パッド３０間の距離Ｓは、バンプ接合時の位置精度により決定されるため、バンプの形状とは関係なく一定である。そこで、バンプ３２のように、平面視での形状において、長辺と短辺とがなす角度を大きくすることにより、電極パッド３３の幅Ｐ２を電極パッド３０の幅Ｐ１より小さくすることができる。これにより、電極パッド３３の幅Ｐ２と隣り合う電極パッド３３間の距離Ｓとの和である電極パッド３３の電極パッドピッチＡ２を、前述の電極パッド３０における電極パッドピッチＡ１より狭くすることができる。 FIG. 7 is a schematic diagram showing a narrowing of the electrode pad pitch in a modification of the embodiment of the present invention. As shown in FIG. 7, when the bumps 31 having a parallelogram shape in plan view are formed on the square electrode pad 30, the electrode pad pitch A 1 is between the electrode pads 30 adjacent to the width P 1 of the electrode pad 30. It is represented by the sum with the distance S. At this time, since the distance S between the adjacent electrode pads 30 is determined by the positional accuracy at the time of bump bonding, it is constant regardless of the shape of the bump. Therefore, like the bump 32, the width P 2 of the electrode pad 33 can be made smaller than the width P 1 of the electrode pad 30 by increasing the angle formed by the long side and the short side in the shape in plan view. it can. As a result, the electrode pad pitch A 2 of the electrode pad 33, which is the sum of the width P 2 of the electrode pad 33 and the distance S between the adjacent electrode pads 33, is made smaller than the electrode pad pitch A 1 of the electrode pad 30 described above. be able to.

次に、上述の如く構成された本実施形態の半導体装置の製造方法について説明する。図８（ａ）乃至（ｄ）は本発明の実施形態の半導体装置の製造方法をその工程順に示す模式図である。先ず、ウェハの状態で、半導体チップ１の表面に設けられたチップ接続用電極パッド３上に平面視で長方形状をなすバンプ１４を、半導体チップ２の表面に設けられたチップ接続用電極パッド３上に平面視で長方形状をなすバンプ１５を形成する。   Next, a method for manufacturing the semiconductor device of the present embodiment configured as described above will be described. 8A to 8D are schematic views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. First, in a wafer state, bumps 14 having a rectangular shape in plan view are formed on the chip connection electrode pads 3 provided on the surface of the semiconductor chip 1, and the chip connection electrode pads 3 provided on the surface of the semiconductor chip 2. A bump 15 having a rectangular shape in plan view is formed thereon.

そして、バンプ１４及びバンプ１５が形成された半導体チップ１及び半導体チップ２を、一般的なダイシング方法により個片化する。次に、図８（ａ）に示すように、半導体チップ１を配線基板８上に実装する。その後、図８（ｂ）に示すように、半導体チップ１のバンプ形成面と半導体チップ２のバンプ形成面とが対向するように、半導体チップ２を裏返して半導体チップ１上に配置し、バンプ４とバンプ５とが交差するように接合する。その接合方法としては、例えば、加熱条件下で加圧する熱圧着法、又は熱と共に超音波を付加する超音波併用熱圧着法等を使用することができる。   Then, the semiconductor chip 1 and the semiconductor chip 2 on which the bumps 14 and 15 are formed are separated into pieces by a general dicing method. Next, as shown in FIG. 8A, the semiconductor chip 1 is mounted on the wiring board 8. Thereafter, as shown in FIG. 8B, the semiconductor chip 2 is turned over and placed on the semiconductor chip 1 so that the bump formation surface of the semiconductor chip 1 and the bump formation surface of the semiconductor chip 2 face each other, and the bump 4 And the bump 5 are joined so as to intersect. As the bonding method, for example, a thermocompression bonding method in which pressure is applied under heating conditions, or an ultrasonic combined thermocompression method in which ultrasonic waves are added together with heat can be used.

次に、図８（ｃ）に示すように、半導体チップ１の外部端子接続用電極パッド７と配線基板８とをボンディングワイヤ９により結線する。これにより、半導体チップ１は外部端子と接続される。その後、図８（ｄ）に示すように、半導体チップ１と半導体チップ２との間の隙間に樹脂６を充填し、封止及び仕上げ工程を行ってＣＯＣ型の半導体装置にする。   Next, as shown in FIG. 8C, the external terminal connecting electrode pad 7 of the semiconductor chip 1 and the wiring substrate 8 are connected by a bonding wire 9. Thereby, the semiconductor chip 1 is connected to the external terminal. Thereafter, as shown in FIG. 8D, a resin 6 is filled in a gap between the semiconductor chip 1 and the semiconductor chip 2, and a sealing and finishing process is performed to obtain a COC type semiconductor device.

本実施形態の半導体装置の製造方法においては、平面視で長方形状又は平行四辺形状をなすバンプを、互いに交差するように接合するため、半導体チップを重ね合わせる際に位置ずれが生じても、バンプ同士の接合面積は一定になる。これにより、半導体チップ内におけるバンプ接合強度のばらつきを小さくすることができ、歩留まりが向上する。また、半導体チップを重ね合わせる際の位置決めが容易になるため、生産性を向上することができる。   In the method for manufacturing a semiconductor device according to the present embodiment, bumps having a rectangular shape or parallelogram shape in plan view are joined so as to intersect with each other. The joint area between them is constant. Thereby, the variation in the bump bonding strength in the semiconductor chip can be reduced, and the yield is improved. Further, since the positioning when the semiconductor chips are overlaid becomes easy, the productivity can be improved.

なお、本実施形態においては、本構造の半導体装置はリード足曲げ型の半導体装置を例に説明したが、本発明はこれに限定されるものではなく、例えば、ＢＧＡ（Ball Grid Array）型の半導体装置にも適用することができる。また、本実施形態においては、電極パッドの形状が同じである半導体チップを使用する場合について述べたが、本発明はこれに限定されるものではなく、例えば、半導体チップ１のチップ接合用電極パッド及び半導体チップ２のチップ接合用電極パッドを、長方形状又は平行四辺形状にして、互いに交差するように接合してもよい。   In the present embodiment, the semiconductor device of this structure has been described by taking a lead foot bending type semiconductor device as an example. However, the present invention is not limited to this, for example, a BGA (Ball Grid Array) type semiconductor device. The present invention can also be applied to a semiconductor device. In the present embodiment, the case where semiconductor chips having the same electrode pad shape are used has been described. However, the present invention is not limited to this. For example, the chip bonding electrode pad of the semiconductor chip 1 is used. In addition, the chip bonding electrode pads of the semiconductor chip 2 may be formed in a rectangular shape or a parallelogram shape so as to cross each other.

本発明の実施形態の半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device of embodiment of this invention. （ａ）は図１に示す半導体チップ１を示す平面図であり、（ｂ）は図１に示す半導体チップ２を示す平面図である。(A) is a top view which shows the semiconductor chip 1 shown in FIG. 1, (b) is a top view which shows the semiconductor chip 2 shown in FIG. （ａ）は本発明の実施形態における半導体チップの接合状態を示す平面図であり、（ｂ）はバンプ接合状態を示す模式図である。(A) is a top view which shows the joining state of the semiconductor chip in embodiment of this invention, (b) is a schematic diagram which shows a bump joining state. （ａ）は本発明の実施形態の変形例における半導体チップ１を示す平面図であり、（ｂ）は本発明の実施形態の変形例における半導体チップ２を示す平面図である。(A) is a top view which shows the semiconductor chip 1 in the modification of embodiment of this invention, (b) is a top view which shows the semiconductor chip 2 in the modification of embodiment of this invention. （ａ）は本発明の実施形態の変形例における半導体チップの接合状態を示す平面図であり、（ｂ）は（ａ）のバンプ接合状態を示す模式図である。(A) is a top view which shows the joining state of the semiconductor chip in the modification of embodiment of this invention, (b) is a schematic diagram which shows the bump joining state of (a). （ａ）は本発明の実施形態の変形例におけるバンプの接合状態を示す模式図であり、（ｂ）及び（ｃ）は（ａ）に示すバンプの中の１つを示す拡大模式図である。(A) is a schematic diagram which shows the joining state of the bump in the modification of embodiment of this invention, (b) and (c) are the enlarged schematic diagrams which show one of the bumps shown to (a). . 本発明の実施形態の変形例における電極パッドピッチの狭ピッチ化を示す模式図である。It is a schematic diagram which shows narrowing of the electrode pad pitch in the modification of embodiment of this invention. （ａ）乃至（ｄ）は本発明の実施形態の半導体装置の製造方法をその工程順に示す模式図である。(A) thru | or (d) are the schematic diagrams which show the manufacturing method of the semiconductor device of embodiment of this invention in the order of the process. （ａ）乃至（ｃ）は従来のＣＯＣ型半導体装置の製造方法を示す平面図である。(A) thru | or (c) is a top view which shows the manufacturing method of the conventional COC type semiconductor device. （ａ）は従来のＣＯＣ型半導体装置におけるバンプの接合状態を示す模式図であり、（ｂ）及び（ｃ）は（ａ）に示すバンプの中の１つを示す拡大模式図である。(A) is a schematic diagram which shows the joining state of the bump in the conventional COC type | mold semiconductor device, (b) And (c) is an enlarged schematic diagram which shows one of the bumps shown to (a).

符号の説明Explanation of symbols

１、２；半導体チップ
３；チップ接続用電極パッド
４、４ａ、４ｂ、５、５ａ、５ｂ、１４、１５、２４、２４ａ、２４ｂ、２５、２５ａ、２５ｂ、３１、３２；バンプ
６；樹脂
７；外部端子接続用電極パッド
８；配線基板
９；ボンディングワイヤ
１０、２０；接合部
３０、３３；電極パッド
Ａ１、Ａ２；電極パッドピッチ
Ｐ１、Ｐ２；電極パッドの幅
Ｓ；隣り合う電極パッド間の距離 1, 2; Semiconductor chip 3; Chip connection electrode pads 4, 4a, 4b, 5, 5a, 5b, 14, 15, 24, 24a, 24b, 25, 25a, 25b, 31, 32; Bump 6; Resin 7 ; Electrode pad for external terminal connection 8; wiring board 9; bonding wires 10 and 20; junctions 30 and 33; electrode pads A 1 and A 2 ; electrode pad pitches P 1 and P 2 ; electrode pad width S; Distance between electrode pads

Claims (9)

第１の半導体チップの表面に設けられた電極パッド上に形成された第１のバンプと、第２の半導体チップの表面に設けられた電極パッド上に形成された第２のバンプとが接合されている半導体装置において、前記第１のバンプ及び前記第２のバンプは、平面視で長方形状をなし、前記第１のバンプと前記第２のバンプとが交差するように接合されていることを特徴とする半導体装置。 The first bump formed on the electrode pad provided on the surface of the first semiconductor chip and the second bump formed on the electrode pad provided on the surface of the second semiconductor chip are joined. In the semiconductor device, the first bump and the second bump have a rectangular shape in a plan view, and the first bump and the second bump are joined so as to intersect with each other. A featured semiconductor device. 第１の半導体チップの表面に設けられた電極パッド上に形成された第１のバンプと、第２の半導体チップの表面に設けられた電極パッド上に形成された第２のバンプとが接合されている半導体装置において、前記第１のバンプ及び前記第２のバンプは、平面視で平行四辺形状をなし、前記第１のバンプと前記第２のバンプとが交差するように接合されていることを特徴とする半導体装置。 The first bump formed on the electrode pad provided on the surface of the first semiconductor chip and the second bump formed on the electrode pad provided on the surface of the second semiconductor chip are joined. In the semiconductor device, the first bump and the second bump have a parallelogram shape in a plan view, and the first bump and the second bump are joined so as to intersect with each other. A semiconductor device characterized by the above. 前記第１のバンプは１又は複数群毎にそれに属する複数個のバンプが相互に平行であり、前記第２のバンプは１又は複数群毎にそれに属する複数個のバンプが相互に平行であって、前記第１及び第２のバンプは各群毎に対応するもの同士が接合されていることを特徴とする請求項１又は２に記載の半導体装置。 In the first bump, a plurality of bumps belonging to one or a plurality of groups are parallel to each other, and in the second bump, a plurality of bumps belonging to each of one or a plurality of groups are parallel to each other. The semiconductor device according to claim 1, wherein the first and second bumps corresponding to each group are bonded to each other. 前記第２の半導体チップが接合された前記第１の半導体チップは、基板上に実装され、更に封止されていることを特徴とする請求項１乃至３のいずれか１項に記載の半導体装置。 4. The semiconductor device according to claim 1, wherein the first semiconductor chip to which the second semiconductor chip is bonded is mounted on a substrate and further sealed. 5. . 前記第１の半導体チップと前記第２の半導体チップとの間には樹脂が充填されていることを特徴とする請求項１乃至４のいずれか１項に記載の半導体装置。 5. The semiconductor device according to claim 1, wherein a resin is filled between the first semiconductor chip and the second semiconductor chip. 6. 第１の半導体チップの表面に設けられた電極パッド上に第１のバンプを形成する工程と、第２の半導体チップの表面に設けられた電極パッド上に第２のバンプを形成する工程と、前記第１のバンプと前記第２のバンプとが交差するように前記第１のバンプと前記第２のバンプとを接合する工程と、を有し、前記第１のバンプ及び前記第２のバンプは、平面視で平行四辺形状をなすことを特徴とする半導体装置の製造方法。 Forming a first bump on the electrode pad provided on the surface of the first semiconductor chip; forming a second bump on the electrode pad provided on the surface of the second semiconductor chip; Bonding the first bump and the second bump so that the first bump and the second bump intersect, and the first bump and the second bump Is a method of manufacturing a semiconductor device, wherein the semiconductor device has a parallelogram shape in plan view. 第１の半導体チップの表面に設けられた電極パッド上に第１のバンプを形成する工程と、第２の半導体チップの表面に設けられた電極パッド上に第２のバンプを形成する工程と、前記第１のバンプと前記第２のバンプとが交差するように前記第１のバンプと前記第２のバンプとを接合する工程と、を有し、前記第１のバンプ及び前記第２のバンプは、平面視で平行四辺形状をなすことを特徴とする半導体装置の製造方法。 Forming a first bump on the electrode pad provided on the surface of the first semiconductor chip; forming a second bump on the electrode pad provided on the surface of the second semiconductor chip; Bonding the first bump and the second bump so that the first bump and the second bump intersect, and the first bump and the second bump Is a method of manufacturing a semiconductor device, wherein the semiconductor device has a parallelogram shape in plan view. 前記第２の半導体チップが接合された前記第１の半導体チップを封止する工程を有することを特徴とする請求項６又は７に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 6, further comprising a step of sealing the first semiconductor chip to which the second semiconductor chip is bonded. 前記第１の半導体チップと前記第２の半導体チップとの間に樹脂を充填する工程を有することを特徴とする請求項６乃至８のいずれか１項に記載の半導体装置の製造方法。
9. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of filling a resin between the first semiconductor chip and the second semiconductor chip.
JP2003270820A 2003-07-03 2003-07-03 Semiconductor device and its manufacturing method Pending JP2005026630A (en)

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Cited By (5)

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JP2017005262A (en) * 2016-08-24 2017-01-05 キヤノン株式会社 Solid-state imaging device
US10199355B2 (en) 2015-11-27 2019-02-05 Samsung Electronics Co., Ltd. Semiconductor devices including stacked semiconductor chips
CN109524412A (en) * 2018-11-14 2019-03-26 长江存储科技有限责任公司 Three-dimensional storage and its manufacturing method
US10497734B2 (en) 2010-06-30 2019-12-03 Canon Kabushiki Kaisha Solid-state imaging apparatus
US11271542B2 (en) 2016-09-06 2022-03-08 Taiyo Yuden Co., Ltd. Acoustic wave device and method of fabricating the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10497734B2 (en) 2010-06-30 2019-12-03 Canon Kabushiki Kaisha Solid-state imaging apparatus
US10199355B2 (en) 2015-11-27 2019-02-05 Samsung Electronics Co., Ltd. Semiconductor devices including stacked semiconductor chips
US10483243B2 (en) 2015-11-27 2019-11-19 Samsung Electronics Co., Ltd. Semiconductor devices including stacked semiconductor chips
JP2017005262A (en) * 2016-08-24 2017-01-05 キヤノン株式会社 Solid-state imaging device
US11271542B2 (en) 2016-09-06 2022-03-08 Taiyo Yuden Co., Ltd. Acoustic wave device and method of fabricating the same
CN109524412A (en) * 2018-11-14 2019-03-26 长江存储科技有限责任公司 Three-dimensional storage and its manufacturing method

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