JP2005039519A

JP2005039519A - Clock regenerating circuit

Info

Publication number: JP2005039519A
Application number: JP2003274419A
Authority: JP
Inventors: Shunji Kimura; 俊二木村; Hideyuki Nosaka; 秀之野坂; Yuuki Imai; 祐記今井; Makoto Nakamura; 誠中村; Yuji Akatsu; 祐史赤津; Masami Tokumitsu; 雅美徳光
Original assignee: Nippon Telegraph and Telephone Corp
Current assignee: Nippon Telegraph and Telephone Corp
Priority date: 2003-07-15
Filing date: 2003-07-15
Publication date: 2005-02-10
Anticipated expiration: 2023-07-15
Also published as: JP3859077B2

Abstract

<P>PROBLEM TO BE SOLVED: To regenerate a fine clock signal without being influenced by the duty ratio of an input signal and even when there is a difference between the transition time of a potential rising part of an input signal and that of a potential drop part. <P>SOLUTION: The clock regenerating circuit is provided with two input terminals 12, 13 to which complementary signals are inputted, delay elements 3, 4 for delaying a half bit of the complementary signals between the complementary signals inputted to the two input terminals 12, 13, an AND circuit 14 for inputting an output signal of each delay element, and an oscillation circuit 10 with an oscillating/stopping gate constituted so that a NAND output terminal 17 of the AND circuit 14 is connected to a gate terminal 11. An output terminal of the oscillation circuit 10 with the gate is used as a clock output terminal 2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、バースト伝送用受信装置に用いられ瞬時応答性能を有するクロック再生回路に関する。 The present invention relates to a clock recovery circuit used in a burst transmission receiver and having instantaneous response performance.

図１７に、従来の典型的な瞬時応答クロック再生回路のブロック図を示す。図中、１は信号入力端子、２はクロック出力端子、３，４は遅延素子（遅延手段）、５は遅延差、６は排他的論理和回路、７，８は排他的論理和回路６の入力端子、９は一致出力端子、１０は発振／停止用のゲート付き発振回路、１１はゲート端子を示す。瞬時応答クロック再生回路はバースト伝送用受信装置の論理回路にクロックを供給する回路として一般的に用いられている。 FIG. 17 shows a block diagram of a conventional typical instantaneous response clock recovery circuit. In the figure, 1 is a signal input terminal, 2 is a clock output terminal, 3 and 4 are delay elements (delay means), 5 is a delay difference, 6 is an exclusive OR circuit, and 7 and 8 are exclusive OR circuits 6. An input terminal, 9 is a coincidence output terminal, 10 is an oscillation circuit with a gate for oscillation / stop, and 11 is a gate terminal. The instantaneous response clock recovery circuit is generally used as a circuit for supplying a clock to a logic circuit of a burst transmission receiver.

図１８は従来の瞬時応答クロック再生回路の基本動作を示すタイムチャートで、図中の記号２’，７’，８’，９’，１１’は、図１７中同じ数字（ただし「’」無し）で示した端子の電圧信号（電圧波形）を示す。図中の電圧信号（電圧波形）は、高い部分が論理レベルの高電位側を示し、文中では符号“１”で示す。同様に低い部分が論理レベルの低電位側を示し、文中では符号“０”で示す。他のタイムチャートでも基本的にこれと同じ表現を用いることとする。 FIG. 18 is a time chart showing the basic operation of a conventional instantaneous response clock recovery circuit. Symbols 2 ', 7', 8 ', 9' and 11 'in the figure are the same numbers in FIG. The voltage signal (voltage waveform) of the terminal indicated by () is shown. In the voltage signal (voltage waveform) in the figure, the high portion indicates the high potential side of the logic level, and is indicated by the symbol “1” in the text. Similarly, the low part indicates the low potential side of the logic level, and is indicated by the symbol “0” in the text. In other time charts, the same expression is basically used.

一般に、間欠的に受信されるバースト信号もしくはパケット信号は、個々のバースト信号間もしくはパケット信号間の位相が必ずしも揃っていないので、バースト伝送用受信装置のクロック抽出回路には、バースト信号毎、もしくはパケット信号毎にクロックを瞬時に抽出する性能が必要となる。 In general, since burst signals or packet signals received intermittently do not necessarily have the same phase between individual burst signals or packet signals, the clock extraction circuit of the burst transmission receiving device includes each burst signal or A performance that instantaneously extracts a clock for each packet signal is required.

図１７において、入力端子１から入力されたバース信号もしくはパケット信号は２分岐され、遅延素子３，４によって該信号の1/2ビット分の遅延差５を与えられて排他的論理和回路６に入力される。排他的論理和回路６には分岐された同一の信号が入力されるため、その一致出力信号は基本的には符号“１”を出力するが、信号間に1/2ビット分の遅延差５が与えられているため、入力信号の電位上昇部と電位下降部に入力信号の1/2ビット分の符号“０”を出力する（９’＝１１’）。ゲート付き発振回路１０は、そのゲート端子１１に符号“１”が入力されている間だけ所定の周波数（入力信号のビットレートに対応した周波数）のクロックを発振し、符号“０”が入力されている間発振を停止する回路であるので、入力信号の1/2ビット分の符号“０”（以後便宜上、ゲート制御ビットと呼ぶ）によって発振停止、発振開始を瞬時に行うことができる。即ち、入力信号の電位上昇部及び電位下降部に位相同期のとれたクロック信号２’を瞬時に出力することができる。以上の内容は特許文献１、非特許文献１に記載がある。
特許第３３４６４４５号公報木村外５名著、「光パケットシステム用１０Ｇbit/sバーストモードクロックデータ再生装置」、ECOC、2002年9月8日、会報、第3巻、ペーパーナンバー8.2.5(S.Kimura,A.Okada,J.Endo,H.Tanobe,Y.Suzuki,and M.Matsuoka,“10-Gbit/s burst-mode clock and data recovery units for optical packet-based systems.,”ECOC 8th Sept.2002 Proceedings vol.3,Paper No. 8.2.5）。 In FIG. 17, the burst signal or packet signal input from the input terminal 1 is branched into two and given to the exclusive OR circuit 6 by being given a delay difference 5 of 1/2 bit of the signal by the delay elements 3 and 4. Entered. Since the same signal branched is input to the exclusive OR circuit 6, the coincidence output signal basically outputs a code “1”, but a delay difference of 1/2 bit between the signals is 5 Therefore, the code “0” corresponding to ½ bit of the input signal is output to the potential rising portion and the potential falling portion of the input signal (9 ′ = 11 ′). The gated oscillation circuit 10 oscillates a clock having a predetermined frequency (frequency corresponding to the bit rate of the input signal) only while the code “1” is input to the gate terminal 11, and the code “0” is input. Since this is a circuit that stops oscillation during this period, oscillation can be stopped and started instantly by means of a sign “0” (hereinafter referred to as a gate control bit for convenience) of 1/2 bits of the input signal. That is, it is possible to instantaneously output the clock signal 2 'phase-synchronized with the potential rising portion and the potential falling portion of the input signal. The above contents are described in Patent Document 1 and Non-Patent Document 1.
Japanese Patent No. 3346445 5 authors outside Kimura, “10Gbit / s burst mode clock data recovery device for optical packet system”, ECOC, September 8, 2002, newsletter, volume 3, paper number 8.2.5 (S. Kimura, A. Okada , J. Endo, H. Tanobe, Y. Suzuki, and M. Matsuoka, “10-Gbit / s burst-mode clock and data recovery units for optical packet-based systems.,” ECOC 8th Sept. 2002 Proceedings vol.3 Paper No. 8.2.5).

従来の瞬時応答クロック再生回路は、既に説明したように入力信号の電位上昇部及び電位下降部に同期のとれたクロック信号を抽出するため、一般に電位上昇部及び電位下降部の時間変動に対する耐性が低いという欠点がある。 Since the conventional instantaneous response clock recovery circuit extracts the clock signal synchronized with the potential rising portion and the potential falling portion of the input signal as already described, it is generally resistant to time fluctuations of the potential rising portion and the potential falling portion. There is a disadvantage that it is low.

図１９に入力信号のデューティ比が変動した場合の従来の瞬時応答クロック再生回路の動作のタイムチャートを示す。図では便宜上デューティ比が小さくなった場合（符号“１”の幅が狭くなり符号“０”の幅が広い場合）の動作を示している。排他的論理和回路６の一致出力信号波形９’は、電位下降部に生じるゲート制御ビットの時間軸上の位置が電位上昇部に生じるものに対して相対的に早まるため、電位下降部のゲート制御ビットの直前のクロック出力信号波形２’の幅が狭められ、品質が劣化することがわかる。 FIG. 19 shows a time chart of the operation of the conventional instantaneous response clock recovery circuit when the duty ratio of the input signal varies. For the sake of convenience, the figure shows the operation when the duty ratio is small (when the width of the code “1” is narrowed and the width of the code “0” is wide). Since the coincidence output signal waveform 9 ′ of the exclusive OR circuit 6 has a relatively earlier position on the time axis of the gate control bit generated in the potential lowering portion than that generated in the potential rising portion, the gate of the potential lowering portion It can be seen that the width of the clock output signal waveform 2 ′ immediately before the control bit is narrowed and the quality deteriorates.

図２０に入力信号の電位上昇部と電位下降部の遷移時間に差が生じた場合の従来の瞬時応答クロック再生回路の動作のタイムチャートを示す。図では便宜上、電位下降部の遷移時間が長い場合を例として示す。排他的論理和回路６の一致出力信号波形９’は、入力信号の電位上昇下降時間を反映するので、電位下降部に生じるゲート制御ビットは電位下降部、上昇部ともに遷移時間の長いものとなり、このゲート制御ビットで発振停止、発振開始を行った場合、発振回路１０から出力されるクロック信号も遷移時間の影響を受けて品質が劣化することが分かる。 FIG. 20 shows a time chart of the operation of the conventional instantaneous response clock recovery circuit when there is a difference between the transition times of the potential rising portion and the potential falling portion of the input signal. In the figure, for the sake of convenience, the case where the transition time of the potential lowering portion is long is shown as an example. Since the coincidence output signal waveform 9 ′ of the exclusive OR circuit 6 reflects the potential rise / fall time of the input signal, the gate control bit generated in the potential fall portion has a long transition time in both the potential fall portion and the rise portion. It can be seen that when the oscillation is stopped and started by this gate control bit, the quality of the clock signal output from the oscillation circuit 10 is also affected by the transition time.

本発明の目的は、入力信号のデューティ比の影響を受けず、且つ入力信号の電位上昇部と電位下降部の遷移時間に差がある場合でも良好なクロック信号を再生することができるようにしたクロック再生回路を提供することである。 An object of the present invention is to be able to reproduce a good clock signal even when there is a difference in transition time between the potential rising portion and the potential falling portion of the input signal without being affected by the duty ratio of the input signal. A clock recovery circuit is provided.

請求項１にかかるクロック再生回路の発明は、入力信号の電位上昇部もしくは電位下降部の一方に選択的にゲート制御ビットを発生させるゲート制御ビット発生手段と、該ゲート制御ビット発生手段で発生した前記ゲート制御ビットがゲート端子に入力することにより前記ゲート制御ビットに位相同期したクロックを発生する発振／停止用のゲート付き発振回路と、を具備することを特徴とする。
請求項２にかかるクロック再生回路の発明は、相補信号が入力する２つの入力端子と、該２つの入力端子に入力された相補信号間に該信号の２分の１ビット分の遅延差を与える遅延手段と、該遅延手段の２つの出力信号を入力する論理積回路と、該論理積回路の論理積出力端子もしくは否定論理積出力端子がゲート端子に接続される発振／停止用のゲート付き発振回路とを具備し、該ゲート付き発振回路の出力端子をクロック出力端子とすることを特徴とする。
請求項３にかかるクロック再生回路の発明は、相補信号が入力する２つの入力端子と、該２つの入力端子に入力された相補信号間に該信号の２分の１ビット分の遅延差を与える遅延手段と、該遅延手段の２つの出力信号を入力する論理和回路と、該論理和回路の論理和出力端子もしくは否定論理和出力端子がゲート端子に接続される発振／停止用のゲート付き発振回路とを具備し、該ゲート付き発振回路の出力端子をクロック出力端子とすることを特徴とする。
請求項４にかかるクロック再生回路の発明は、非反転出力端子及び反転出力端子を有する分配回路の入力端子を信号入力端子とし、前記分配回路の非反転出力端子と反転出力端子を請求項２に記載のクロック再生回路の前記２つの入力端子に各々接続することを特緻とする。
請求項５にかかるクロック再生回路の発明は、非反転出力端子及び反転出力端子を有する分配回路の入力端子を信号入力端子とし、前記分配回路の非反転出力端子と反転出力端子を請求項３に記載のクロック再生回路の前記２つの入力端子に各々接続することを特徴とする。
請求項６にかかるクロック再生回路の発明は、排他的論理和回路の２つの入力端子の一方を信号入力端子、他方を制御端子とし、該排他的論理和回路の排他的論理和出力端子と一致出力端子を請求項２に記載のクロック再生回路の前記２つの入力端子に各々接続することを特徴とする。
請求項７にかかるクロック再生回路の発明は、排他的論理和回路の２つの入力端子の一方を信号入力端子、他方を制御端子とし、該排他的論理和回路の排他的論理和出力端子と一致出力端子を請求項３に記載のクロック再生回路の前記２つの入力端子に各々接続することを特徴とする。 The invention of the clock recovery circuit according to claim 1 is generated by the gate control bit generating means for selectively generating the gate control bit at one of the potential rising portion or the potential falling portion of the input signal, and the gate control bit generating means. And an oscillation circuit with a gate for oscillating / stopping that generates a clock phase-synchronized with the gate control bit when the gate control bit is input to a gate terminal.
The invention of the clock recovery circuit according to claim 2 provides a delay difference corresponding to a half bit of the signal between the two input terminals to which the complementary signal is input and the complementary signal input to the two input terminals. Delay circuit, logical product circuit for inputting two output signals of the delay circuit, and oscillation with oscillation and stop gate for connecting logical product output terminal or negative logical product output terminal of the logical product circuit to gate terminal And an output terminal of the gated oscillation circuit as a clock output terminal.
The invention of the clock recovery circuit according to claim 3 provides a delay difference corresponding to a half bit of the signal between the two input terminals to which the complementary signal is input and the complementary signal input to the two input terminals. Delay means, OR circuit for inputting two output signals of the delay means, and oscillation with a gate for oscillation / stop where the OR output terminal or the NOT OR output terminal of the OR circuit is connected to the gate terminal And an output terminal of the gated oscillation circuit as a clock output terminal.
According to a fourth aspect of the present invention, the input circuit of the distribution circuit having a non-inverting output terminal and an inverting output terminal is used as a signal input terminal, and the non-inverting output terminal and the inverting output terminal of the distribution circuit are defined in claim 2. It is characterized in that it is connected to each of the two input terminals of the clock recovery circuit described.
The invention of the clock recovery circuit according to claim 5 is characterized in that the input terminal of the distribution circuit having the non-inverting output terminal and the inverting output terminal is a signal input terminal, and the non-inverting output terminal and the inverting output terminal of the distribution circuit are defined in claim 3. The clock recovery circuit is connected to each of the two input terminals.
The invention of the clock recovery circuit according to claim 6 uses one of the two input terminals of the exclusive OR circuit as a signal input terminal and the other as the control terminal, and matches the exclusive OR output terminal of the exclusive OR circuit. An output terminal is connected to each of the two input terminals of the clock recovery circuit according to claim 2.
The invention of the clock recovery circuit according to claim 7 is characterized in that one of two input terminals of the exclusive OR circuit is a signal input terminal and the other is a control terminal, and coincides with the exclusive OR output terminal of the exclusive OR circuit. An output terminal is connected to each of the two input terminals of the clock recovery circuit according to claim 3.

本発明では、クロックの同期をとるゲート制御ビットを入力信号の電位上昇部もしくは電位下降部の一方に選択的に生じさせるので、入力信号のデューティ比が変動した場合にも良好なクロック出力信号を得ることができ、また入力信号の電位上昇部と電位下降部の遷移時間に差がある場合にも、遷移時間の短い方を選択して発振回路の同期をとることができるので、良好なクロック出力信号を得ることができる。 In the present invention, the gate control bit for synchronizing the clock is selectively generated in one of the potential rising portion and the potential falling portion of the input signal, so that a good clock output signal can be generated even when the duty ratio of the input signal varies. Even if there is a difference in the transition time between the potential rising part and the potential falling part of the input signal, it is possible to select the shorter transition time and synchronize the oscillation circuit. An output signal can be obtained.

本発明では、ゲート付き発振回路のゲート端子に入力して発振停止、発振開始を制御するゲート制御ビットを、入力信号の電位上昇部もしくは電位下降部の一方に選択的に生じさせ、該電位上昇部もしくは電位下降部の一方に位相同期のとれたクロック信号をゲート付き発振回路から瞬時に出力させる。 In the present invention, a gate control bit for controlling the oscillation stop and oscillation start by inputting to the gate terminal of the gated oscillation circuit is selectively generated in one of the potential rising portion and the potential falling portion of the input signal, and the potential rise A clock signal in phase synchronization is instantaneously output from the gated oscillation circuit to one of the first and second potential lowering sections.

図１は本発明の実施例１のクロック再生回路を示す図で、図中、図１７と同様の記号は同様のものを示す。また、１２，１３は相補信号（差動信号）の入力端子、１４は論理積回路、１５，１６は論理積回路入力端子、１７は否定論理積出力端子、を示す。入力端子１２，１３と、遅延素子３，４と、否定論理積出力端子１７を有する論理積回路１４はゲート制御ビット発生手段を構成する。 FIG. 1 is a diagram showing a clock recovery circuit according to a first embodiment of the present invention, in which the same symbols as those in FIG. 17 indicate the same components. Reference numerals 12 and 13 denote complementary signal (differential signal) input terminals, reference numeral 14 denotes a logical product circuit, reference numerals 15 and 16 denote logical product circuit input terminals, and reference numeral 17 denotes a negative logical product output terminal. An AND circuit 14 having input terminals 12 and 13, delay elements 3 and 4, and a negative AND output terminal 17 constitutes a gate control bit generating means.

入力端子１２にバースト信号もしくはパケット信号の非反転信号を、入力端子１３に反転信号を入力した場合の本発明の実施例１の基本動作のフローチャートを、図２に示す。図から明らかなように、論理積回路１４の否定論理積出力信号１７’には非反転側の信号１５’の電位上昇部のみでゲート制御ビットが生じることが分かる。 FIG. 2 shows a flowchart of the basic operation of the first embodiment of the present invention when a burst signal or a non-inverted signal of a packet signal is input to the input terminal 12 and an inverted signal is input to the input terminal 13. As is apparent from the figure, the gate control bit is generated only in the potential rise portion of the non-inverted signal 15 ′ in the NAND output signal 17 ′ of the AND circuit 14.

図３に入力信号のデューティ比が変動した場合の本発明の実施例１の動作のタイムチャートを示す。図から明らかなように、本発明のクロック再生回路は非反転側の信号１５’の電位上昇部のみでゲート制御ビットを生じさせて同期をとっているので、図１９に見られるようなデューティ比の変動による電位上昇部のゲート制御ビットと電位下降部のゲート制御ビットの相対的な時間位置の変化によって生じるクロック出力信号波形の劣化が生じないことが分かる。 FIG. 3 shows a time chart of the operation of the first embodiment of the present invention when the duty ratio of the input signal varies. As is clear from the figure, the clock recovery circuit of the present invention is synchronized by generating a gate control bit only at the potential rising portion of the non-inverted signal 15 ', so that the duty ratio as shown in FIG. It can be seen that there is no deterioration in the waveform of the clock output signal caused by the change in the relative time position of the gate control bit of the potential rising portion and the gate control bit of the potential falling portion due to the fluctuation of the.

図４に入力信号の電位上昇部と電位下降部の遷移時間に差が生じた場合の本発明の実施例１の動作のタイムチャートを示す。図では便宜上、電位下降部の遷移時間が長い場合を示す。本発明のクロック再生回路は、非反転側の信号１５’の電位上昇部でのみゲート制御を行って同期をとるため、図２０に見られるような電位下降部の遷移時間の長さによるクロック出力信号波形の劣化が生じないことが分かる。 FIG. 4 shows a time chart of the operation of the first embodiment of the present invention when a difference occurs in the transition time between the potential rising portion and the potential falling portion of the input signal. In the figure, for the sake of convenience, the case where the transition time of the potential lowering portion is long is shown. Since the clock recovery circuit of the present invention performs synchronization by performing gate control only at the potential rising portion of the non-inverted signal 15 ′, the clock output according to the length of the transition time of the potential falling portion as shown in FIG. It can be seen that the signal waveform does not deteriorate.

入力端子１２にバースト信号もしくはパケット信号の反転信号を、入力端子１３に非反転信号を入力した場合の本発明の実施例１の基本動作のフローチャートを、図５に示す。図から明らかなように、論理積回路１４の否定論理積出力信号１７’には非反転側の信号１６’の電位下降部のみでゲート制御ビットが生じることが分かる。この場合もデューティ比の変動によるクロック出力信号波形の劣化は生じないし、図４の例とは逆に、非反転側の信号１６’の電位上昇部の遷移時間が電位下降部の遷移時間よりも長い場合に有効である。 FIG. 5 shows a flowchart of the basic operation of the first embodiment of the present invention when a burst signal or an inverted signal of a packet signal is input to the input terminal 12 and a non-inverted signal is input to the input terminal 13. As can be seen from the figure, the gate control bit is generated only in the potential falling portion of the non-inverted signal 16 'in the NAND output signal 17' of the AND circuit 14. In this case as well, the clock output signal waveform does not deteriorate due to the change in the duty ratio. Contrary to the example of FIG. 4, the transition time of the potential rising portion of the non-inverted signal 16 ′ is longer than the transition time of the potential falling portion. Effective when long.

図６は本発明の実施例２のクロック再生回路を示す図で、図中、図１と同様の記号は同様のものを示す。１８は論理積出力端子、１９はゲート付き発振回路（ゲート端子の極性が前記ゲート付き発振回路１０と反転しているもの）、２０はゲート端子、を示す。入力端子１２，１３と、遅延素子３，４と、論理積出力端子１８を有する論理積回路１４はゲート制御ビット発生手段を構成する。ここでは“１”のゲート制御ビットを使用する。 FIG. 6 is a diagram showing a clock recovery circuit according to the second embodiment of the present invention. In the figure, the same symbols as those in FIG. Reference numeral 18 denotes a logical product output terminal, 19 denotes a gated oscillation circuit (where the polarity of the gate terminal is inverted from that of the gated oscillation circuit 10), and 20 denotes a gate terminal. An AND circuit 14 having input terminals 12 and 13, delay elements 3 and 4, and an AND output terminal 18 constitutes a gate control bit generating means. Here, a gate control bit of “1” is used.

ゲート付き発振回路１９のゲート端子の極性が反転している場合、即ち符号“０”のゲート入力時に発振、符号“１”のゲート入力時に発振停止する発振回路１９を使用する場合に有効で、図１の否定論理積出力端子１７のかわりに論理積出力端子１８をゲート端子２０に接続した例である。 This is effective when the polarity of the gate terminal of the oscillation circuit 19 with gate is inverted, that is, when using the oscillation circuit 19 that oscillates when the gate of the sign “0” is input and stops oscillating when the gate input of the sign “1” is used. This is an example in which a logical product output terminal 18 is connected to a gate terminal 20 instead of the negative logical product output terminal 17 of FIG.

図７に本発明実施例２の基本動作のタイムチャートを示す。論理積回路１４の出力信号波形１８’とクロック出力信号波形２’が反転しているが、実施例１（図１）と同様の効果が得られることが分かる。 FIG. 7 shows a time chart of the basic operation of the second embodiment of the present invention. Although the output signal waveform 18 ′ and the clock output signal waveform 2 ′ of the AND circuit 14 are inverted, it can be seen that the same effect as in the first embodiment (FIG. 1) can be obtained.

図８は本発明実施例３のクロック再生回路を示す図で、図中、図１と同様の記号は同様のものを示す。２１は論理和回路、２２，２３は論理和回路入力端子、２４は論理和出力端子、を示す。入力端子１２，１３と、遅延素子３，４と、論理和出力端子２４を有する論理和回路２１はゲート制御ビット発生手段を構成する。 FIG. 8 is a diagram showing a clock recovery circuit according to the third embodiment of the present invention. In the figure, the same symbols as those in FIG. 21 represents a logical sum circuit, 22 and 23 represent logical sum circuit input terminals, and 24 represents a logical sum output terminal. An OR circuit 21 having input terminals 12 and 13, delay elements 3 and 4, and an OR output terminal 24 constitutes a gate control bit generating means.

入力端子１２にバースト信号もしくはパケット信号の非反転信号を、入力端子１３に反転信号を入力した場合の本発明の実施例３の基本動作のタイムチャートを、図９に示す。図から明らかなように、論理和回路２１の論理和出力信号２４’には非反転側の信号２２’の電位下降部のみでゲート制御ビットが生じることが分かる。即ち入力端子１２にバースト信号もしくはパケット信号の反転信号を、入力端子１３に非反転信号を入力した場合の実施例１（図５）と同様の効果が得られることが分かる。 FIG. 9 shows a time chart of the basic operation of the third embodiment of the present invention when a non-inverted signal of a burst signal or a packet signal is input to the input terminal 12 and an inverted signal is input to the input terminal 13. As is apparent from the figure, in the OR output signal 24 ′ of the OR circuit 21, a gate control bit is generated only at the potential falling portion of the non-inverted signal 22 ′. That is, it can be seen that the same effect as that of the first embodiment (FIG. 5) can be obtained when the burst signal or the inverted signal of the packet signal is input to the input terminal 12 and the non-inverted signal is input to the input terminal 13.

入力端子１２にバースト信号もしくはパケット信号の反転信号を、入力端子１３に非反転信号を入力した場合の本発明の実施例３の基本動作のタイムチャートを、図１０に示す。図から明らかなように、論理和回路２１の論理和出力信号２４’には非反転側の信号２３’の電位上昇部のみでゲート制御ビットが生じることが分かる。即ち、入力端子１２にバースト信号もしくはパケット信号の非反転信号を、入力端子１３に反転信号を入力した場合の実施例１（図２〜図４）と同様の効果が得られることが分かる。 A time chart of the basic operation of the third embodiment of the present invention when a burst signal or an inverted signal of a packet signal is input to the input terminal 12 and a non-inverted signal is input to the input terminal 13 is shown in FIG. As can be seen from the figure, in the OR output signal 24 ′ of the OR circuit 21, a gate control bit is generated only in the potential rising portion of the non-inverted signal 23 ′. That is, it can be seen that the same effect as in the first embodiment (FIGS. 2 to 4) can be obtained when a non-inverted signal of a burst signal or packet signal is input to the input terminal 12 and an inverted signal is input to the input terminal 13.

図１１は本発明の実施例４のクロック再生回路を示す図で、図中、図６、図８と同様の記号は同様のものを示す。２５は否定論理和出力端子を示す。これは実施例３にゲート端子２０の極性が反転しているゲート付き発振回路１９を用いた例である。入力端子１２，１３と、遅延素子３，４と、否定論理和出力端子２５を有する論理和回路２１はゲート制御ビット発生手段を構成する。ここでは“１”のゲート制御ビットを使用する。 FIG. 11 is a diagram showing a clock recovery circuit according to a fourth embodiment of the present invention, in which the same symbols as those in FIGS. 6 and 8 indicate the same components. Reference numeral 25 denotes a negative OR output terminal. This is an example in which the gated oscillation circuit 19 in which the polarity of the gate terminal 20 is inverted is used in the third embodiment. A logical sum circuit 21 having input terminals 12 and 13, delay elements 3 and 4, and a negative logical sum output terminal 25 constitutes a gate control bit generating means. Here, a gate control bit of “1” is used.

図１２に本発明実施例４の基本動作のタイムチャートを示す。論理和回路２１の出力信号波形２５’とクロック出力信号波形２’が反転しているが、実施例３（図８、図９）と同様の効果が得られることが分かる。 FIG. 12 shows a time chart of the basic operation of the fourth embodiment of the present invention. Although the output signal waveform 25 ′ and the clock output signal waveform 2 ′ of the OR circuit 21 are inverted, it can be seen that the same effect as in the third embodiment (FIGS. 8 and 9) can be obtained.

図１３は本発明実施例５のクロック再生回路を示す図で、図中、図１、図１７と同様の記号は同様のものを示す。２６は分配回路、２７は分配回路非反転出力端子、２８は分配回路反転出力端子を示す。 FIG. 13 is a diagram showing a clock recovery circuit according to the fifth embodiment of the present invention. In the figure, the same symbols as those in FIGS. 1 and 17 indicate the same components. Reference numeral 26 denotes a distribution circuit, 27 denotes a distribution circuit non-inverting output terminal, and 28 denotes a distribution circuit inverting output terminal.

本実施例は本発明の実施例１の２つの入力端子１２，１３に分配回路２６の非反転出力端子２７と反転出力端子２８を接続することにより、入力端子を分配回路２６の入力端子１つに削減できるというメリットがある。基本動作は実施例１と同様であるので、同様の効果が得られる。なお、図中では便宜上、分配回路２６より後段に実施例１のクロック再生回路を使用したが、実施例１〜４までの全ての実施例のクロック再生回路のいずれを用いても同様の効果が得られる。 In this embodiment, the non-inverting output terminal 27 and the inverting output terminal 28 of the distribution circuit 26 are connected to the two input terminals 12 and 13 of the first embodiment of the present invention, so that the input terminal is one input terminal of the distribution circuit 26. There is an advantage that it can be reduced. Since the basic operation is the same as that of the first embodiment, the same effect can be obtained. In the figure, for convenience, the clock recovery circuit of the first embodiment is used after the distribution circuit 26, but the same effect can be obtained by using any of the clock recovery circuits of the first to fourth embodiments. can get.

図１４は本発明実施例６のクロック再生回路を示す図で、図中、図１３と同様の記号は同様のものを示す。本実施例は、図５で示した実施例１の入力端子１２に反転信号を、入力端子１３に非反転信号を入力した場合の基本動作と同様の動作が得られるもので、分配回路２６の反転出力端子２８を入力端子１２側に、非反転出力端子２７を入力端子１３側に接続した例である。本実施例では便宜上、図１３と同様に分配回路２６より後段に実施例１のクロック再生回路を使用したが、実施例１〜４までの全ての実施例のクロック再生回路のいずれを用いても同様の効果が得られる。 FIG. 14 is a diagram showing a clock recovery circuit according to the sixth embodiment of the present invention. In the figure, the same symbols as those in FIG. 13 denote the same components. In this embodiment, an operation similar to the basic operation when an inverted signal is input to the input terminal 12 and a non-inverted signal is input to the input terminal 13 of the first embodiment shown in FIG. In this example, the inverting output terminal 28 is connected to the input terminal 12 side, and the non-inverting output terminal 27 is connected to the input terminal 13 side. In this embodiment, for the sake of convenience, the clock recovery circuit of the first embodiment is used after the distribution circuit 26 as in FIG. 13, but any of the clock recovery circuits of the first to fourth embodiments can be used. Similar effects can be obtained.

図１５は本発明実施例７のクロック再生回路を示す図で、図中、図１３と同様の記号は同様のものを示す。２９は排他的論理和回路、３０は排他的論理和出力端子、３１は一致出力端子、３２は制御端子、を示す。本実施例は、本発明実施例１の２つの入力端子１２，１３に排他的論理和回路２９の排他的論理和出力端子３０と一致出力端子３１を接続したものである。 FIG. 15 is a diagram showing a clock recovery circuit according to a seventh embodiment of the present invention. In the figure, the same symbols as those in FIG. 13 denote the same components. Reference numeral 29 denotes an exclusive OR circuit, 30 denotes an exclusive OR output terminal, 31 denotes a coincidence output terminal, and 32 denotes a control terminal. In the present embodiment, the exclusive OR output terminal 30 and the coincidence output terminal 31 of the exclusive OR circuit 29 are connected to the two input terminals 12 and 13 of the first embodiment of the present invention.

排他的論理和回路２９の２つの入力端子のうち一方を信号入力端子１とし、他方を制御端子３２とした場合、制御端子３２に符号“０”を入力すると排他的論理和出力信号３０’には信号入力端子１の入力信号の非反転信号が出力信号され、一致出力信号３１’には反転信号が出力されるため、本発明の実施例１の図２〜図４と同様に動作することがわかる。また、制御端子３２に符号“１”を入力すると、排他的論理和出力信号３０’に信号入力端子１の入力信号の反転信号が出力され、一致出力信号３１’には非反転信号が出力されるため、実施例１の図５で示した動作と同様の効果が得られる。 When one of the two input terminals of the exclusive OR circuit 29 is the signal input terminal 1 and the other is the control terminal 32, the code “0” is input to the control terminal 32 to generate the exclusive OR output signal 30 ′. Since the non-inverted signal of the input signal at the signal input terminal 1 is output and the inverted signal is output as the coincidence output signal 31 ′, the operation is the same as in FIGS. 2 to 4 of the first embodiment of the present invention. I understand. When a code “1” is input to the control terminal 32, an inverted signal of the input signal of the signal input terminal 1 is output to the exclusive OR output signal 30 ′, and a non-inverted signal is output to the coincidence output signal 31 ′. Therefore, the same effect as the operation shown in FIG.

即ち、入力端子１を１つに削減でき、且つ制御端子３２に入力する符号でゲート制御ビットを入力信号の電位上昇部に生じさせるか電位下降部に生じさせるかを選択できるというメリットがある。本実施例では便宜上、図１３と同様に排他的論理和回路２９より後段に実施例１のクロック再生回路を使用したが、実施例１〜４までの全ての実施例のクロック再生回路のいずれを用いても同様の効果が得られる。 That is, there is an advantage that the number of input terminals 1 can be reduced to one, and it is possible to select whether to generate a gate control bit in the potential rising portion or in the potential falling portion of the input signal by the code input to the control terminal 32. In the present embodiment, for the sake of convenience, the clock recovery circuit of the first embodiment is used after the exclusive OR circuit 29 as in FIG. 13, but any one of the clock recovery circuits of all the first to fourth embodiments is used. Even if it is used, the same effect can be obtained.

図１６は本発明実施例８のクロック再生回路を示す図で、図中、図１５と同様の記号は同様のものを示す。本実施例では、本発明実施例７（図１５）の排他的論理和回路２９の排他的論理和出力端子３０と一致出力端子３１を逆に接続しており、制御端子３２に符号“０”を入力した際に入力信号の電位下降部にゲート制御ビットを生じさせ、符号“１”を入力した際に電位上昇部にゲート制御ビットを生じさせることができる。本実施例では便宜上、図１５と同様に排他的論理和回路２９より後段に実施例１のクロック再生回路を使用したが、実施例１〜４までの全ての実施例のクロック再生回路のいずれを用いても同様の効果が得られる。 FIG. 16 is a diagram showing a clock recovery circuit according to the eighth embodiment of the present invention. In the figure, the same symbols as those in FIG. 15 indicate the same components. In the present embodiment, the exclusive OR output terminal 30 and the coincidence output terminal 31 of the exclusive OR circuit 29 of Embodiment 7 (FIG. 15) of the present invention are connected in reverse, and the control terminal 32 has the code “0”. When a signal is input, a gate control bit can be generated at the potential lowering portion of the input signal, and when a code “1” is input, a gate control bit can be generated at the potential increasing portion. In the present embodiment, for the sake of convenience, the clock recovery circuit of the first embodiment is used after the exclusive OR circuit 29 as in FIG. 15, but any of the clock recovery circuits of all the first to fourth embodiments is used. Even if it is used, the same effect can be obtained.

本発明で使用する遅延素子３，４（遅延手段）は少ない損失で遅延を生じるものであれば、伝送線路でもケーブルでも、遅延回路でもどのようなものを用いても構わない。遅延時間が短い方の遅延素子３に関しては、長い方の遅延素子４がバースト信号もしくはパケット信号等の入力信号の1/2ビット分丁度の場合に限って、省略可能である。また、本発明で使用する論理積回路１４、論理和回路２１、排他的論理和回路２９、分配回路２６、ゲート付き発振回路１０，１９に関しては、同様の動作をするものであれば回路構成の詳細は問わない。 The delay elements 3 and 4 (delay means) used in the present invention may be any transmission line, cable, or delay circuit as long as it causes a delay with a small loss. The delay element 3 with a shorter delay time can be omitted only when the longer delay element 4 is exactly 1/2 bit of an input signal such as a burst signal or a packet signal. The AND circuit 14, the OR circuit 21, the exclusive OR circuit 29, the distribution circuit 26, and the gated oscillation circuits 10 and 19 used in the present invention have a circuit configuration as long as they perform the same operation. Details do not matter.

本発明の実施例１のクロック再生回路の回路図である。1 is a circuit diagram of a clock recovery circuit according to a first embodiment of the present invention. 本発明の実施例１の基本動作を示すタイムチャートである。It is a time chart which shows the basic operation | movement of Example 1 of this invention. 本発明の効果を示すタイムチャート（デューティ比変動時）である。It is a time chart (at the time of duty ratio change) which shows the effect of the present invention. 本発明の効果を示すタイムチャート（電位上昇部及び電位下降部の遷移時間に差がある場合）である。It is a time chart which shows the effect of the present invention (when there is a difference in transition time between the potential rising portion and the potential falling portion). 本発明の実施例１の基本動作を示すタイムチャート（反転入力）である。It is a time chart (inversion input) which shows the basic operation | movement of Example 1 of this invention. 本発明の実施例２のクロック再生回路の回路図である。It is a circuit diagram of the clock reproduction circuit of Example 2 of the present invention. 本発明の実施例２の基本動作を示すタイムチャートである。It is a time chart which shows the basic operation | movement of Example 2 of this invention. 本発明の実施例３のクロック再生回路の回路図である。It is a circuit diagram of the clock reproduction circuit of Example 3 of the present invention. 本発明の実施例３の基本動作を示すタイムチャートである。It is a time chart which shows the basic operation | movement of Example 3 of this invention. 本発明の実施例３の基本動作を示すタイムチャート（反転入力）である。It is a time chart (inversion input) which shows the basic operation | movement of Example 3 of this invention. 本発明の実施例４のクロック再生回路の回路図である。It is a circuit diagram of the clock reproduction circuit of Example 4 of the present invention. 本発明の実施例４の基本動作を示すタイムチャートである。It is a time chart which shows the basic operation | movement of Example 4 of this invention. 本発明の実施例５のクロック再生回路の回路図である。FIG. 10 is a circuit diagram of a clock recovery circuit according to a fifth embodiment of the present invention. 本発明の実施例６のクロック再生回路の回路図である。FIG. 10 is a circuit diagram of a clock recovery circuit according to a sixth embodiment of the present invention. 本発明の実施例７のクロック再生回路の回路図である。It is a circuit diagram of the clock reproduction circuit of Example 7 of the present invention. 本発明の実施例８のクロック再生回路の回路図である。FIG. 10 is a circuit diagram of a clock recovery circuit according to an eighth embodiment of the present invention. 従来の瞬時応答クロック再生回路の回路図である。It is a circuit diagram of a conventional instantaneous response clock recovery circuit. 従来の瞬時応答クロック再生回路の基本動作を示すタイムチャートである。It is a time chart which shows the basic operation | movement of the conventional instantaneous response clock reproduction circuit. 従来の瞬時応答クロック再生回路のデューティ比変動時の動作を示すタイムチャートである。It is a time chart which shows the operation | movement at the time of the duty ratio fluctuation | variation of the conventional instantaneous response clock reproduction circuit. 従来の瞬時応答クロック再生回路の電位上昇部及び電位下降部の遷移時間に差がある場合の動作を示すタイムチャートである。It is a time chart which shows operation | movement in case there exists a difference in the transition time of the electric potential rise part of a conventional instantaneous response clock reproduction circuit, and an electric potential fall part.

符号の説明Explanation of symbols

１：信号入力端子
２：クロック出力端子
３，４：遅延素子
５：遅延差
６：排他的論理和回路
７，８：排他的論理和回路の入力端子
９：一致出力端子
１０：ゲート付き発振回路
１１：ゲート端子
１２，１３：入力端子
１４：論理積回路
１５，１６：論理積回路入力端子
１７：否定論理積出力端子
１８：論理積出力端子
１９：ゲート付き発振回路（ゲート端子の極性が反転しているもの）
２０：ゲート端子
２１：論理和回路
２２，２３：論理和回路入力端子
２４：論理和出力端子
２５：否定論理和出力端子
２６：分配回路
２７：非反転出力端子
２８：反転出力端子
２９：排他的論理和回路
３０：排他的論理和出力端子
３１：一致出力端子
３２：制御端子
図２〜図５における２’，１１’，１５’，１６’，１７’：図１の同じ数字（ただし「’」無し）で示した端子の電圧信号（電圧波形）
図７における２’，１５’，１６’，１８’，２０’：図６の同じ数字（ただし「’」無し）で示した端子の電圧信号（電圧波形）
図９，図１０における２’，１１’，２２’，２３’，２４’：図８の同じ数字（ただし「’」無し）で示した端子の電圧信号（電圧波形）
図１２における２’，２０’，２２’，２３’，２５’：図１１の同じ数字（ただし「’」無し）で示した端子の電圧信号（電圧波形）
図１８〜図２０における２’，７’，８’，９’，１１’：図１７の同じ数字（ただし「’」無し）で示した端子の電圧信号（電圧波形） 1: signal input terminal 2: clock output terminal 3, 4: delay element 5: delay difference 6: exclusive OR circuit 7, 8: input terminal of exclusive OR circuit 9: coincidence output terminal 10: oscillation circuit with gate 11: Gate terminal 12, 13: Input terminal 14: Logical product circuit 15, 16: Logical product circuit input terminal 17: Negative logical product output terminal 18: Logical product output terminal 19: Oscillation circuit with gate (the polarity of the gate terminal is inverted) What you do)
20: gate terminal 21: logical sum circuit 22, 23: logical sum circuit input terminal 24: logical sum output terminal 25: negative logical sum output terminal 26: distribution circuit 27: non-inverting output terminal 28: inverting output terminal 29: exclusive OR circuit 30: exclusive OR output terminal 31: coincidence output terminal 32: control terminal 2 ′, 11 ′, 15 ′, 16 ′, 17 ′ in FIGS. "No") terminal voltage signal (voltage waveform)
2 ', 15', 16 ', 18', 20 'in FIG. 7: voltage signals (voltage waveforms) at the terminals indicated by the same numerals (without """) in FIG.
9, 10, 2 ′, 11 ′, 22 ′, 23 ′, 24 ′: voltage signals (voltage waveforms) at terminals indicated by the same numbers (but without “′”) in FIG. 8.
2 ', 20', 22 ', 23', 25 'in FIG. 12: Voltage signals (voltage waveforms) at terminals indicated by the same numerals (but without "") in FIG.
18 to 20, 2 ′, 7 ′, 8 ′, 9 ′, 11 ′: voltage signals (voltage waveforms) at the terminals indicated by the same numbers in FIG. 17 (however, no “′”).

Claims

入力信号の電位上昇部もしくは電位下降部の一方に選択的にゲート制御ビットを発生させるゲート制御ビット発生手段と、該ゲート制御ビット発生手段で発生した前記ゲート制御ビットがゲート端子に入力することにより前記ゲート制御ビットに位相同期したクロックを発生する発振／停止用のゲート付き発振回路と、を具備することを特徴とするクロック再生回路。 A gate control bit generating means for selectively generating a gate control bit at one of a potential rising portion or a potential falling portion of the input signal, and the gate control bit generated by the gate control bit generating means being input to a gate terminal A clock recovery circuit comprising: an oscillation circuit with a gate for oscillation / stop that generates a clock phase-synchronized with the gate control bit.

相補信号が入力する２つの入力端子と、該２つの入力端子に入力された相補信号間に該信号の２分の１ビット分の遅延差を与える遅延手段と、該遅延手段の２つの出力信号を入力する論理積回路と、該論理積回路の論理積出力端子もしくは否定論理積出力端子がゲート端子に接続される発振／停止用のゲート付き発振回路とを具備し、該ゲート付き発振回路の出力端子をクロック出力端子とすることを特徴とするクロック再生回路。 Two input terminals to which complementary signals are input; delay means for providing a delay difference corresponding to a half bit of the signal between the complementary signals input to the two input terminals; and two output signals of the delay means And an oscillation circuit with a gate for oscillation / stop where the logical product output terminal or the negative logical product output terminal of the logical product circuit is connected to the gate terminal of the oscillation circuit with the gate. A clock recovery circuit, wherein the output terminal is a clock output terminal.

相補信号が入力する２つの入力端子と、該２つの入力端子に入力された相補信号間に該信号の２分の１ビット分の遅延差を与える遅延手段と、該遅延手段の２つの出力信号を入力する論理和回路と、該論理和回路の論理和出力端子もしくは否定論理和出力端子がゲート端子に接続される発振／停止用のゲート付き発振回路とを具備し、該ゲート付き発振回路の出力端子をクロック出力端子とすることを特徴とするクロック再生回路。 Two input terminals to which complementary signals are input; delay means for providing a delay difference corresponding to a half bit of the signal between the complementary signals input to the two input terminals; and two output signals of the delay means And an oscillation circuit with a gate for oscillating / stopping, in which the logical sum output terminal or the negative logical sum output terminal of the logical sum circuit is connected to the gate terminal of the gated oscillation circuit. A clock recovery circuit, wherein the output terminal is a clock output terminal.

非反転出力端子及び反転出力端子を有する分配回路の入力端子を信号入力端子とし、前記分配回路の非反転出力端子と反転出力端子を請求項２に記載のクロック再生回路の前記２つの入力端子に各々接続することを特緻とするクロック再生回路。 The input terminal of a distribution circuit having a non-inverting output terminal and an inverting output terminal is used as a signal input terminal, and the non-inverting output terminal and the inverting output terminal of the distribution circuit are connected to the two input terminals of the clock recovery circuit according to claim 2. A clock recovery circuit characterized by being connected to each other.

非反転出力端子及び反転出力端子を有する分配回路の入力端子を信号入力端子とし、前記分配回路の非反転出力端子と反転出力端子を請求項３に記載のクロック再生回路の前記２つの入力端子に各々接続することを特徴とするクロック再生回路。 The input terminal of a distribution circuit having a non-inverting output terminal and an inverting output terminal is used as a signal input terminal, and the non-inverting output terminal and the inverting output terminal of the distribution circuit are connected to the two input terminals of the clock recovery circuit according to claim 3. A clock recovery circuit connected to each other.

排他的論理和回路の２つの入力端子の一方を信号入力端子、他方を制御端子とし、該排他的論理和回路の排他的論理和出力端子と一致出力端子を請求項２に記載のクロック再生回路の前記２つの入力端子に各々接続することを特徴とするクロック再生回路。 3. The clock recovery circuit according to claim 2, wherein one of two input terminals of the exclusive OR circuit is a signal input terminal and the other is a control terminal, and the exclusive OR output terminal and the coincidence output terminal of the exclusive OR circuit are the same. A clock recovery circuit connected to each of the two input terminals.

排他的論理和回路の２つの入力端子の一方を信号入力端子、他方を制御端子とし、該排他的論理和回路の排他的論理和出力端子と一致出力端子を請求項３に記載のクロック再生回路の前記２つの入力端子に各々接続することを特徴とするクロック再生回路。 4. The clock recovery circuit according to claim 3, wherein one of two input terminals of the exclusive OR circuit is a signal input terminal and the other is a control terminal, and the exclusive OR output terminal and the coincidence output terminal of the exclusive OR circuit are the same. A clock recovery circuit connected to each of the two input terminals.