JP2004335726A - Method of manufacturing multilayer printed wiring board with cavity - Google Patents

Method of manufacturing multilayer printed wiring board with cavity Download PDF

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Publication number
JP2004335726A
JP2004335726A JP2003129332A JP2003129332A JP2004335726A JP 2004335726 A JP2004335726 A JP 2004335726A JP 2003129332 A JP2003129332 A JP 2003129332A JP 2003129332 A JP2003129332 A JP 2003129332A JP 2004335726 A JP2004335726 A JP 2004335726A
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Japan
Prior art keywords
copper
clad laminate
layer
metal
conductor
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JP2003129332A
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JP4117390B2 (en
Inventor
Osamu Oonagane
修 太長根
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Kyocera Circuit Solutions Inc
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NEC Toppan Circuit Solutions Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer printed wiring board with cavities by which the bad influence by variations in thickness between layers or in thickness of a conductor can be prevented. <P>SOLUTION: The method of manufacturing the multilayer printed wiring board with cavities comprises processes of forming a cavity 2 by spot facing in a copper clad laminate 1 which constitutes a base layer in such a manner that it is extended through a resin layer 1-1 to expose a copper layer 1-2 before making the copper clad laminate into a multilayer structure, filling the cavity with a metal 3 different from copper, forming copper plating layers 4-1 and 4-2 on both faces of the copper clad laminate, forming circuit patterns 5-1 and 5-2 from the copper plating layers including the copper layer on both faces of the copper clad laminate, forming insulation layers 6-1 and 6-2 and circuit patterns 8-1 and 8-2 each forming at least a single layer on both faces of the copper clad laminate to laminate into a multilayer structure, forming a cavity 9 by spot facing from one face side of the copper clad laminate to the metal 3, and removing the metal by etching. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子や抵抗、コンデンサ等のチップ部品を実装するためのキャビティを有するキャビティ付き多層プリント配線板の製造方法に関する。
【０００２】
【従来の技術】
この種のプリント配線板の製造方法として以下のような製造方法が提案されている。この製造方法は、多層プリント配線板の一方の面側からキャビティ部分をＮＣ加工機によるドリルで座ぐり加工する方法であり、以下のような工程を経て実施される。互いに電気的に接続された内層回路パターンの座標とスルーホールの座標とを予めメモリしておき、最初にこのスルーホールと、座ぐり加工具との間の電気接続の有無を監視しながら前記メモリした内層回路パターンの座標で座ぐり加工を行い、前記スルーホールと座ぐり加工具とが電気的に接続された時点で座ぐり加工の深さを求めてメモリし、キャビティの他の部分を同一深さに座ぐり加工する（特許文献１参照）。
【０００３】
【特許文献１】
特開平１０−２２６４３号公報
【０００４】
【発明が解決しようとする課題】
上記の製造方法では、ＮＣ加工機における厳しいＺ軸（深さ）精度が必要となる。つまり、今後求められる高精度な回路パターン上の座ぐり加工においては、回路パターンを形成している導体厚がますます薄くなり、Ｚ軸方向のコントロールがますます厳しくなる。
【０００５】
しかしながら、上記の製造方法では、一パターンの電気的接続が検出された時点で、その時の深さを一定にして座ぐり加工を行うので、多層プリント配線板において座ぐり加工される層より下層の層間厚や導体厚が変動した場合、回路パターン、もしくは搭載される部品との電気的接続を行うパッド、ランドが露出しなかったり、回路パターン、パッド、ランドを削りすぎてしまうことが起こる。その結果、再加工が必要となったり、回路破損が発生する。
【０００６】
そこで、本発明の課題は、多層プリント配線板に対する座ぐり加工をどのような加工で行っても層間厚や導体厚の変動の悪影響を受けることの無いキャビティ付き多層プリント配線板の製造方法を提供することにある。
【０００７】
【課題を解決するための手段】
本発明によるキャビティ付き多層プリント配線板の製造方法は、多層プリント配線板において内層となるべき層を構成する導体張積層板に、樹脂層を貫通して導体が露出するような第１の座ぐり加工を施す工程と、座ぐりされた部分に前記導体とは異なる金属を充填する工程と、前記導体張積層板の両面に導体めっきを施す工程と、前記導体張積層板の両面の導体層により回路パターンを形成する工程と、前記導体張積層板の両面側に、少なくとも一層の絶縁層を含む積層体を形成する工程と、前記積層体の前記第１の座ぐり加工を施した面側より、前記充填された金属に至る第２の座ぐり加工を施して前記充填された金属の一面を露出させる工程とを含むことを特徴とする。
【０００８】
本製造方法においては、前記導体は銅であり、前記金属は錫、半田、ニッケルのいずれかが用いられる。
【０００９】
本製造方法はまた、前記金属の一面を露出させる工程に続いて前記充填された金属をエッチングにより除去する工程を含む。
【００１０】
なお、前記第１の座ぐり加工による座ぐり部の形状は、環状あるいは角筒状とされても良い。
【００１１】
本製造方法においては、前記第１、第２の座ぐり加工はドリル加工又はレーザ加工で行うことが好ましい。
【００１２】
本発明によればまた、チップ部品を実装するためのキャビティを有するキャビティ付き多層プリント配線板の製造方法であって、多層構成とする前に、基礎となる層を構成する銅張積層板に樹脂層を貫通して銅層が露出するような第１の座ぐり加工を施す工程と、座ぐりされた部分に銅とは異なる金属を充填する工程と、前記銅張積層板の両面に銅めっきを施す工程と、前記銅張積層板の両面における前記銅層を含む銅めっき層により回路パターンを形成する工程と、前記銅張積層板の両面側にそれぞれ少なくとも一層の絶縁層及び回路パターンを形成して多層構成とする工程と、前記銅張積層板の上面側又は下面側から前記充填された金属に至る第２の座ぐり加工を施して前記充填された金属の上面又は下面を露出させる工程と、エッチングにより前記充填された金属を除去する工程とを含むことを特徴とするキャビティ付き多層プリント配線板の製造方法が提供される。
【００１３】
【発明の実施の形態】
本発明によるキャビティ付き多層プリント配線板の製造方法は、半導体素子や抵抗、コンデンサ等のチップ部品を実装するためのキャビティの主要部、つまり層間厚や導体厚の変動の影響を受け易い部分を、多層プリント配線板を構成する前に予め座ぐり加工により形成しておく点に特徴を有する。
【００１４】
図１、図２を参照して、本発明によるキャビティ付き多層プリント配線板の製造方法の第１の実施の形態について説明する。
【００１５】
以下に、第１の実施の形態にかかる製造方法を順をおって説明する。
【００１６】
はじめに、図１（ａ）に示すように、任意の厚みをもつ銅張積層板１に、ＮＣ加工機によるドリル加工やレーザ加工等により上面側の銅層１−３及び樹脂層１−１を貫通して下面側の銅層１−２が露出するような第１の座ぐり加工を行い、所定大のキャビティ２を形成する。なお、銅張積層板１は多層プリント配線板を構成する際にその基礎となる層であり、ここでは、上下両面に銅層１−３、１−２を有する銅張積層板１を用いているが、上面側から座ぐり加工を行うのであれば、下面側にのみ銅層を有する片面銅張積層板を用いても良い。また、キャビティ２の形状は、円形や角形等のいずれの形状でも良い。
【００１７】
いずれにしても、本工程における座ぐり加工では、銅層１−２に厚さのばらつきがあったとしてもそれによる悪影響は無い。これは、後述される工程において銅層１−２の上には銅めっきが施されるので、多少の削り過ぎがあったとしても、銅めっき層による回路パターン、もしくは部品が固定されかつ部品との電気的接続を行うためのパッドやランドの形成には支障が無いからである。これは、本工程における座ぐり加工は、Ｚ軸（深さ）方向の厳しい精度を要求されないことを意味する。
【００１８】
次に、図１（ｂ）に示すように、座ぐり部分に銅と異なる金属３をめっきやペースト等にて充填し、充填後、両面側に通常通りＩＶＨ等の銅めっき層４−１、４−２を施す。金属３の材料としては、錫や半田、ニッケル等が用いられる。
【００１９】
次に、図１（ｃ）に示すように、フォトエッチング等の手法により両面側の銅めっき層４−１、４−２（銅層１−２、１−３を含む）による所望の回路パターン５−１、５−２の形成を行う。なお、金属３の上方に対応する領域には回路パターンは形成されない。
【００２０】
次に、図１（ｄ）に示すように、銅張積層板１の上下両面側に絶縁層６−２、６−１を積層後、レーザ加工等により両面側の予め定められた一箇所以上の位置にビアホール７を形成する。
【００２１】
続いて、図１（ｅ）に示すように、絶縁層６−１、６−２上に銅めっきを施した後、フォトエッチング等の手法により所望の回路パターン８−１、８−２を形成する。なお、ここでは便宜上、銅張積層板１の上下に、それぞれ一層ずつ絶縁層及び回路パターンを形成しているが、二層以上形成されても良い。勿論、一層あるいは二層以上のいずれの場合においても金属３の上方に対応する領域には回路パターンは形成されない。また、上面側から座ぐり加工を行う場合には、下面側には絶縁層６−１のみを形成する場合があり得る。
【００２２】
その後、図２（ｆ）を参照して、ドリル加工やレーザ加工等により絶縁層６−２を貫通して金属３の上面が露出するような第２の座ぐり加工を行い、キャビティ９を形成する。ここでは、キャビティ９の径（あるいは幅）をキャビティ２の径（あるいは幅）より大きくしているが、同じ又は小さくても良い。勿論、キャビティ２と９の平面形状が同じである必要は無い。本工程における座ぐり加工も、Ｚ軸（深さ）方向の厳しい精度を要求されない。
【００２３】
続いて、図２（ｇ）を参照して、銅に対するエッチング量の少ないエッチング剤でエッチングを行い、金属３を除去する。その結果、キャビティ９とキャビティ２とを合わせたキャビティ１０が形成される。なお、充填される金属３の材料が錫、半田等の場合、エッチング剤としては硝酸ベースエッチング剤を用いることができる。
【００２４】
以上のようにして、ＮＣ加工機やレーザ加工機においてＺ軸方向（深さ方向）の高精度な制御を実施しなくても、チップ部品実装のための所望の実装パッド１１を実現することが出来る。これにより、部品との電気的接続の不良が生じることは無くなる。
【００２５】
図３は、本発明によるキャビティ付き多層プリント配線板の製造方法の第２の実施の形態を工程順に示している。この第２の実施の形態は、第１の座ぐり加工により形成するキャビティを環状あるいは角筒状とし、そこに充填される金属の除去を行わないようにした点において第１の実施の形態と異なる。それゆえ、図１、図２と同じ部分には同じ参照番号を付している。
【００２６】
図３（ａ）に示すように、任意の厚みをもつ銅張積層板１に、ＮＣ加工機によるドリル加工やレーザ加工等により上面側の銅層１−３及び樹脂層１−１を貫通して下面側の銅層１−２が露出するような第１の座ぐり加工を行い、環状あるいは角筒状のキャビティ２´を形成する。勿論、本形態においても上面側から座ぐり加工を行うのであれば、下面側にのみ銅層を有する片面銅張積層板を用いても良い。
【００２７】
本工程における座ぐり加工でも、前述したのと同じ理由で銅層１−２に厚さのばらつきがあったとしてもそれによる悪影響は無いし、Ｚ軸方向（深さ方向）の高精度の制御は要求されない。
【００２８】
次に、図３（ｂ）に示すように、座ぐり部分に銅と異なる金属３をめっきやペースト等にて充填し、充填後、両面側に通常通りＩＶＨ等の銅めっき層４−１、４−２を施す。
【００２９】
次に、図３（ｃ）に示すように、エッチング等の手法により両面側の銅めっき層４−１、４−２（銅層１−２、１−３を含む）による所望の回路パターン５−１、５−２の形成を行う。なお、環状あるいは角筒状の金属３及びその内側の上方に対応する領域には回路パターンは形成されない。
【００３０】
次に、図３（ｄ）に示すように、銅張積層板１の上下両面側に絶縁層６−２、６−１を積層後、レーザ加工等により両面側の予め定められた位置にビアホール７を形成する。
【００３１】
続いて、図３（ｅ）に示すように、絶縁層６−１、６−２上に銅めっきを施した後、エッチング等の手法により所望の回路パターン８−１、８−２を形成する。なお、ここでも便宜上、銅張積層板１の上下に、それぞれ一層ずつ絶縁層及び回路パターンを形成しているが、二層以上形成されても良い。勿論、一層あるいは二層以上のいずれの場合においても金属３及びその内側の上方に対応する領域には回路パターンは形成されない。また、前述したように上側から座ぐり加工を行う場合には、下面側には絶縁層６−１のみを形成する場合があり得る。
【００３２】
その後、図３（ｆ）を参照して、ドリル加工やレーザ加工等により絶縁層６−１を貫通して金属３及びその内側の上面が露出するような第２の座ぐり加工を行い、キャビティ９を形成する。ここでも、キャビティ９の径をキャビティ２の径より大きくしているが、同じでも良い。また、この第２の座ぐり加工もＺ軸方向（深さ方向）の高精度の制御は要求されない。
【００３３】
以上のようにして、ＮＣ加工機やレーザ加工機においてＺ軸方向（深さ方向）の高精度な制御を実施しなくても、チップ部品実装のための所望の実装パッド１１´を実現することが出来る。
【００３４】
以上、本発明を２つの実施の形態について説明したが、本発明はこれら２つの実施の形態に限らず、様々な変更が可能である。例えば、第１の座ぐり加工による座ぐり部に充填される金属３に代えて感光性樹脂を充填するようにしても良い。
【００３５】
【発明の効果】
以上説明したように、本発明による製造方法によれば、多層構成とする前にキャビティの主要部となる部分を座ぐり加工により形成しておき、回路パターン形成用の銅とは異種の金属を充填することで、特殊なＺ軸制御を有しない座ぐり加工機においても、実装パッド形成のための所望の回路パターンを露出させることが可能となる。つまり、本発明による製造方法は、多層プリント配線板における層間厚や導体厚の変動の悪影響を受けることが無い。これにより、部品との電気的接続の不良が生じることを無くすことができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態によるキャビティ付き多層プリント配線板の製造方法の流れを順に示した断面図である。
【図２】図１に続く製造方法の流れを順に示した断面図である。
【図３】本発明の第２の実施の形態によるキャビティ付き多層プリント配線板の製造方法の流れを順に示した断面図である。
【符号の説明】
１ 銅張積層板
１−１ 樹脂層
１−２、１−３ 銅層
２、２´、９、１０ キャビティ
３ 金属
４−１、４−２ 銅めっき層
５−１、５−２、８−１、８−２ 回路パターン
１１、１１´ 実装パッド[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a multilayer printed wiring board with a cavity having a cavity for mounting a chip component such as a semiconductor element, a resistor, and a capacitor.
[0002]
[Prior art]
The following manufacturing method has been proposed as a method for manufacturing this type of printed wiring board. This manufacturing method is a method in which a cavity portion is counterbored from one surface side of a multilayer printed wiring board with a drill using an NC processing machine, and is implemented through the following steps. The coordinates of the inner layer circuit pattern and the coordinates of the through hole electrically connected to each other are previously stored in the memory, and the memory is first monitored while monitoring the presence or absence of the electrical connection between the through hole and the counterboring tool. The counterbore processing is performed at the coordinates of the inner layer circuit pattern, and the depth of the counterbore processing is determined and stored when the through hole and the counterbore processing tool are electrically connected, and the other parts of the cavity are made identical. Counterbore processing to a depth (see Patent Document 1).
[0003]
[Patent Document 1]
JP-A-10-22643
[Problems to be solved by the invention]
In the above manufacturing method, strict Z-axis (depth) accuracy in the NC processing machine is required. In other words, in counterbore processing on a high-precision circuit pattern that will be required in the future, the thickness of the conductor forming the circuit pattern will become increasingly thinner, and control in the Z-axis direction will become increasingly strict.
[0005]
However, in the above manufacturing method, at the time when one pattern of electrical connection is detected, the counterbore processing is performed with the depth at that time being constant, so that the lower layer than the layer to be counterbored in the multilayer printed wiring board is used. If the interlayer thickness or the conductor thickness fluctuates, the pads or lands for making an electrical connection with the circuit pattern or the component to be mounted may not be exposed, or the circuit patterns, pads and lands may be excessively shaved. As a result, rework is required or the circuit is damaged.
[0006]
Therefore, an object of the present invention is to provide a method for manufacturing a multilayer printed wiring board with a cavity which is not adversely affected by variations in interlayer thickness or conductor thickness regardless of the counterbore processing performed on the multilayer printed wiring board. Is to do.
[0007]
[Means for Solving the Problems]
The method for manufacturing a multilayer printed wiring board with cavities according to the present invention is directed to a first counterbore in which a conductor is exposed through a resin layer in a conductor-clad laminate constituting a layer to be an inner layer in the multilayer printed wiring board. A step of performing processing, a step of filling the countersunk portion with a metal different from the conductor, a step of performing conductor plating on both surfaces of the conductor-clad laminate, and a conductor layer on both surfaces of the conductor-clad laminate A step of forming a circuit pattern; a step of forming a laminate including at least one insulating layer on both sides of the conductor-clad laminate; and a step of performing the first spot facing process on the laminate. Performing a second counterbore process to the filled metal to expose one surface of the filled metal.
[0008]
In the present manufacturing method, the conductor is copper, and the metal is tin, solder, or nickel.
[0009]
The method also includes the step of exposing one side of the metal and subsequently removing the filled metal by etching.
[0010]
The shape of the spot facing portion formed by the first spot facing may be annular or rectangular.
[0011]
In the present manufacturing method, it is preferable that the first and second counterboring processes are performed by drilling or laser processing.
[0012]
According to the present invention, there is also provided a method of manufacturing a multilayer printed wiring board having a cavity having a cavity for mounting a chip component, wherein a resin is added to a copper-clad laminate constituting a base layer before forming a multilayer structure. Performing a first counterbore process through which the copper layer is exposed, filling the counterbored portion with a metal different from copper, and performing copper plating on both surfaces of the copper-clad laminate And forming a circuit pattern with a copper plating layer including the copper layer on both surfaces of the copper-clad laminate, and forming at least one insulating layer and a circuit pattern on both surfaces of the copper-clad laminate, respectively. Forming a multilayer structure, and performing a second counterboring process from the upper surface side or the lower surface side of the copper-clad laminate to the filled metal to expose the upper surface or the lower surface of the filled metal. And Etchin Method for producing cavity-multilayer printed circuit board which comprises a step of removing the filler metal is provided by.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
The method for manufacturing a multilayer printed wiring board with a cavity according to the present invention includes a semiconductor element, a resistor, and a main part of a cavity for mounting chip parts such as a capacitor, that is, a part that is easily affected by a change in interlayer thickness or conductor thickness. It is characterized in that it is formed by spot facing before forming a multilayer printed wiring board.
[0014]
A first embodiment of a method for manufacturing a multilayer printed wiring board with cavities according to the present invention will be described with reference to FIGS.
[0015]
Hereinafter, the manufacturing method according to the first embodiment will be described step by step.
[0016]
First, as shown in FIG. 1 (a), a copper layer 1-3 and a resin layer 1-1 on the upper surface side are formed on a copper-clad laminate 1 having an arbitrary thickness by drilling, laser processing, or the like using an NC processing machine. A first counterbore process is performed to penetrate and expose the copper layer 1-2 on the lower surface side, thereby forming a cavity 2 having a predetermined size. Note that the copper-clad laminate 1 is a layer serving as a base when forming a multilayer printed wiring board. Here, the copper-clad laminate 1 having copper layers 1-3 and 1-2 on both upper and lower surfaces is used. However, if counterboring is performed from the upper surface side, a single-sided copper-clad laminate having a copper layer only on the lower surface side may be used. Further, the shape of the cavity 2 may be any shape such as a circle or a square.
[0017]
In any case, in the spot facing in this step, even if the thickness of the copper layer 1-2 varies, there is no adverse effect. This is because the copper plating is applied on the copper layer 1-2 in a process to be described later, so that the circuit pattern or the component by the copper plating layer is fixed and the component and This is because there is no problem in the formation of the pads and lands for making the electrical connection. This means that spot facing in this step does not require strict accuracy in the Z-axis (depth) direction.
[0018]
Next, as shown in FIG. 1B, the counterbore portion is filled with a metal 3 different from copper by plating, paste, or the like, and after filling, a copper plating layer 4-1 such as IVH is formed on both sides as usual. 4-2 is performed. As the material of the metal 3, tin, solder, nickel or the like is used.
[0019]
Next, as shown in FIG. 1C, a desired circuit pattern is formed by the copper plating layers 4-1 and 4-2 (including the copper layers 1-2 and 1-3) on both sides by a technique such as photoetching. 5-1 and 5-2 are formed. Note that no circuit pattern is formed in a region corresponding to a region above the metal 3.
[0020]
Next, as shown in FIG. 1D, after laminating the insulating layers 6-2 and 6-1 on the upper and lower surfaces of the copper clad laminate 1, one or more predetermined positions on both surfaces are formed by laser processing or the like. A via hole 7 is formed at the position.
[0021]
Subsequently, as shown in FIG. 1E, after performing copper plating on the insulating layers 6-1 and 6-2, desired circuit patterns 8-1 and 8-2 are formed by a technique such as photoetching. I do. In addition, here, for convenience, the insulating layer and the circuit pattern are formed one by one on the upper and lower sides of the copper clad laminate 1, however, two or more layers may be formed. Of course, no circuit pattern is formed in the region corresponding to the upper part of the metal 3 in either case of one layer or two or more layers. Further, when spot facing is performed from the upper surface side, only the insulating layer 6-1 may be formed on the lower surface side.
[0022]
Thereafter, referring to FIG. 2F, a second counterboring process is performed by drilling, laser processing, or the like so that the upper surface of metal 3 is exposed through insulating layer 6-2 to form cavity 9. I do. Here, the diameter (or width) of the cavity 9 is larger than the diameter (or width) of the cavity 2, but may be the same or smaller. Of course, it is not necessary that the cavities 2 and 9 have the same planar shape. The spot facing in this step also does not require strict accuracy in the Z-axis (depth) direction.
[0023]
Subsequently, referring to FIG. 2G, the metal 3 is removed by etching with an etching agent having a small etching amount with respect to copper. As a result, a cavity 10 in which the cavity 9 and the cavity 2 are combined is formed. When the material of the metal 3 to be filled is tin, solder, or the like, a nitric acid-based etchant can be used as an etchant.
[0024]
As described above, a desired mounting pad 11 for mounting chip components can be realized without performing high-precision control in the Z-axis direction (depth direction) in an NC processing machine or a laser processing machine. I can do it. As a result, a failure in electrical connection with the component does not occur.
[0025]
FIG. 3 shows a second embodiment of a method for manufacturing a multilayer printed wiring board with cavities according to the present invention in the order of steps. The second embodiment is different from the first embodiment in that the cavity formed by the first counterbore processing is formed in an annular or rectangular tube shape, and the metal filled therein is not removed. different. Therefore, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals.
[0026]
As shown in FIG. 3A, a copper-clad laminate 1 having an arbitrary thickness is penetrated through a copper layer 1-3 and a resin layer 1-1 on the upper surface side by drilling, laser processing, or the like using an NC processing machine. First, counterbore processing is performed so that the copper layer 1-2 on the lower surface side is exposed to form an annular or rectangular cylindrical cavity 2 '. Of course, also in this embodiment, a single-sided copper-clad laminate having a copper layer only on the lower surface side may be used if counterboring is performed from the upper surface side.
[0027]
Also in the spot facing in this step, even if the thickness of the copper layer 1-2 varies due to the same reason as described above, there is no adverse effect, and high-precision control in the Z-axis direction (depth direction). Is not required.
[0028]
Next, as shown in FIG. 3B, the spot facing portion is filled with a metal 3 different from copper by plating, paste, or the like. After the filling, the copper plating layers 4-1 such as IVH are formed on both sides as usual. 4-2 is performed.
[0029]
Next, as shown in FIG. 3C, a desired circuit pattern 5 is formed by copper plating layers 4-1 and 4-2 (including copper layers 1-2 and 1-3) on both sides by a technique such as etching. -1, 5-2 are formed. Note that no circuit pattern is formed in the annular or rectangular metal 3 and in the region corresponding to the upper portion inside the metal 3.
[0030]
Next, as shown in FIG. 3D, after the insulating layers 6-2 and 6-1 are laminated on the upper and lower surfaces of the copper-clad laminate 1, via holes are formed at predetermined positions on both surfaces by laser processing or the like. 7 is formed.
[0031]
Subsequently, as shown in FIG. 3E, after performing copper plating on the insulating layers 6-1 and 6-2, desired circuit patterns 8-1 and 8-2 are formed by a technique such as etching. . Here, for convenience, the insulating layer and the circuit pattern are formed one by one on the upper and lower sides of the copper clad laminate 1, respectively, but two or more layers may be formed. Needless to say, no circuit pattern is formed in the metal 3 and the region corresponding to the upper portion inside the metal 3 in any case of one layer or two or more layers. In addition, when the spot facing is performed from the upper side as described above, only the insulating layer 6-1 may be formed on the lower surface side.
[0032]
Thereafter, referring to FIG. 3 (f), a second counterboring process is performed by drilling, laser processing, or the like so that the metal 3 and the upper surface inside the metal 3 are exposed through the insulating layer 6-1. 9 is formed. Here, the diameter of the cavity 9 is larger than the diameter of the cavity 2, but may be the same. Also, the second spot facing does not require high-precision control in the Z-axis direction (depth direction).
[0033]
As described above, it is possible to realize a desired mounting pad 11 ′ for mounting chip components without performing high-precision control in the Z-axis direction (depth direction) in the NC processing machine or the laser processing machine. Can be done.
[0034]
As described above, the present invention has been described with respect to the two embodiments, but the present invention is not limited to these two embodiments, and various modifications can be made. For example, a photosensitive resin may be filled in place of the metal 3 filled in the spot facing portion by the first spot facing process.
[0035]
【The invention's effect】
As described above, according to the manufacturing method of the present invention, a main portion of the cavity is formed by spot facing before forming a multilayer structure, and a metal different from copper for forming a circuit pattern is formed. By filling, a desired circuit pattern for mounting pad formation can be exposed even in a spot facing machine without special Z-axis control. In other words, the manufacturing method according to the present invention does not suffer from the adverse effects of variations in the interlayer thickness and conductor thickness in the multilayer printed wiring board. As a result, it is possible to prevent the occurrence of a failure in the electrical connection with the component.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a flow of a method of manufacturing a multilayer printed wiring board with a cavity according to a first embodiment of the present invention.
FIG. 2 is a sectional view sequentially showing the flow of the manufacturing method following FIG. 1;
FIG. 3 is a sectional view sequentially showing a flow of a method of manufacturing a multilayer printed wiring board with cavities according to a second embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Copper-clad laminated board 1-1 Resin layer 1-2, 1-3 Copper layer 2, 2 ', 9, 10 Cavity 3 Metal 4-1 and 4-2 Copper plating layers 5-1 and 5-2 and 8- 1, 8-2 circuit pattern 11, 11 'mounting pad

Claims (6)

多層プリント配線板において内層となるべき層を構成する導体張積層板に、樹脂層を貫通して導体が露出するような第１の座ぐり加工を施す工程と、
座ぐりされた部分に前記導体とは異なる金属を充填する工程と、
前記導体張積層板の両面に導体めっきを施す工程と、
前記導体張積層板の両面の導体層により回路パターンを形成する工程と、
前記導体張積層板の両面側に、少なくとも一層の絶縁層を含む積層体を形成する工程と、
前記積層体の前記第１の座ぐり加工を施した面側より、前記充填された金属に至る第２の座ぐり加工を施して前記充填された金属の一面を露出させる工程とを含むことを特徴とするキャビティ付き多層プリント配線板の製造方法。A step of subjecting a conductor-clad laminate constituting a layer to be an inner layer in the multilayer printed wiring board to a first counterboring process such that the conductor is exposed through the resin layer;
Filling the spotted portion with a metal different from the conductor;
Applying a conductor plating on both sides of the conductor-clad laminate,
A step of forming a circuit pattern with conductor layers on both surfaces of the conductor-clad laminate,
Forming a laminate including at least one insulating layer on both sides of the conductor-clad laminate,
Performing a second counterboring process from the side of the laminated body on which the first counterboring process is performed to the filled metal to expose one surface of the filled metal. A method for manufacturing a multilayer printed wiring board with a cavity, which is characterized by the following. 請求項１に記載の製造方法において、前記導体は銅であり、前記金属は錫、半田、ニッケルのいずれかであることを特徴とするキャビティ付き多層プリント配線板の製造方法。2. The method according to claim 1, wherein the conductor is copper, and the metal is one of tin, solder, and nickel. 請求項１又は２に記載の製造方法において、前記金属の一面を露出させる工程に続いて前記充填された金属をエッチングにより除去する工程を含むことを特徴とするキャビティ付き多層プリント配線板の製造方法。3. The method according to claim 1, further comprising, after exposing one surface of the metal, removing the filled metal by etching. . 請求項１又は２に記載の製造方法において、前記第１の座ぐり加工による座ぐり部の形状を環状あるいは角筒状としたことを特徴とするキャビティ付き多層プリント配線板の製造方法。3. The method according to claim 1, wherein a shape of the counterbore portion formed by the first counterbore processing is an annular shape or a rectangular tube shape. 4. 請求項１〜４のいずれかに記載の製造方法において、前記第１、第２の座ぐり加工をドリル加工又はレーザ加工で行うことを特徴とするキャビティ付き多層プリント配線板の製造方法。The method according to any one of claims 1 to 4, wherein the first and second counterboring processes are performed by drilling or laser processing. チップ部品を実装するためのキャビティを有するキャビティ付き多層プリント配線板の製造方法において、
多層構成とする前に、基礎となる層を構成する銅張積層板に樹脂層を貫通して銅層が露出するような第１の座ぐり加工を施す工程と、
座ぐりされた部分に銅とは異なる金属を充填する工程と、
前記銅張積層板の両面に銅めっきを施す工程と、
前記銅張積層板の両面における前記銅層を含む銅めっき層により回路パターンを形成する工程と、
前記銅張積層板の両面側にそれぞれ少なくとも一層の絶縁層及び回路パターンを形成して多層構成とする工程と、
前記銅張積層板の上面側又は下面側から前記充填された金属に至る第２の座ぐり加工を施して前記充填された金属の上面又は下面を露出させる工程と、
エッチングにより前記充填された金属を除去する工程とを含むことを特徴とするキャビティ付き多層プリント配線板の製造方法。In a method for manufacturing a multilayer printed wiring board with a cavity having a cavity for mounting a chip component,
A step of subjecting a copper-clad laminate constituting a base layer to a first counterbore process such that the copper layer is exposed through the resin layer before the multilayer structure is formed;
A step of filling the spotted portion with a metal different from copper,
A step of performing copper plating on both surfaces of the copper-clad laminate,
A step of forming a circuit pattern by a copper plating layer including the copper layer on both surfaces of the copper-clad laminate,
Forming a multilayer structure by forming at least one insulating layer and a circuit pattern on both sides of the copper-clad laminate,
A step of subjecting the filled metal to a second counterbore process from the upper surface side or the lower surface side of the copper-clad laminate to the filled metal to expose the upper surface or the lower surface of the filled metal,
Removing the filled metal by etching. A method of manufacturing a multilayer printed wiring board with cavities, the method comprising:
JP2003129332A 2003-05-07 2003-05-07 Manufacturing method of multilayer printed wiring board with cavity Expired - Fee Related JP4117390B2 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008078290A (en) * 2006-09-20 2008-04-03 Nec Corp Printed circuit board and method for manufacturing the same
JP2008112996A (en) * 2006-10-27 2008-05-15 Samsung Electro-Mechanics Co Ltd Method of manufacturing printed-circuit substrate
JP2012049196A (en) * 2010-08-24 2012-03-08 Kinko Denshi Kofun Yugenkoshi Printed wiring board and method of manufacturing the same
KR101233642B1 (en) 2011-11-28 2013-02-15 대덕전자 주식회사 Method of manufacturing a cavity printed circuit board
JP5554868B1 (en) * 2013-07-03 2014-07-23 太陽誘電株式会社 Manufacturing method of substrate with cavity

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008078290A (en) * 2006-09-20 2008-04-03 Nec Corp Printed circuit board and method for manufacturing the same
JP2008112996A (en) * 2006-10-27 2008-05-15 Samsung Electro-Mechanics Co Ltd Method of manufacturing printed-circuit substrate
JP2012049196A (en) * 2010-08-24 2012-03-08 Kinko Denshi Kofun Yugenkoshi Printed wiring board and method of manufacturing the same
KR101233642B1 (en) 2011-11-28 2013-02-15 대덕전자 주식회사 Method of manufacturing a cavity printed circuit board
JP5554868B1 (en) * 2013-07-03 2014-07-23 太陽誘電株式会社 Manufacturing method of substrate with cavity
CN104284522A (en) * 2013-07-03 2015-01-14 太阳诱电株式会社 Method of manufacturing substrate having cavity
KR101555474B1 (en) 2013-07-03 2015-09-24 다이요 유덴 가부시키가이샤 Method for manufacturing substrate with cavity
US9301407B2 (en) 2013-07-03 2016-03-29 Taiyo Yuden Co., Ltd. Method of manufacturing substrate having cavity
TWI552654B (en) * 2013-07-03 2016-10-01 Taiyo Yuden Kk A method for manufacturing a cavity substrate

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