JP2004288892A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2004288892A
JP2004288892A JP2003079385A JP2003079385A JP2004288892A JP 2004288892 A JP2004288892 A JP 2004288892A JP 2003079385 A JP2003079385 A JP 2003079385A JP 2003079385 A JP2003079385 A JP 2003079385A JP 2004288892 A JP2004288892 A JP 2004288892A
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pad
semiconductor device
solder
opening
tape
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Fumihiro Iwami
文宏 岩見
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Toshiba Corp
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Toshiba Corp
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device improved in connecting reliability between solder and pad, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device 20 is formed of a semiconductor element 14, a tape 4 for the supporting substrate of the semiconductor element, a pad 3 for the electrode of the semiconductor element 14, an opening unit 8 provided on the tape 4 with a predetermined size smaller than the diameter of the pad 3, and slits 6 having a gap and formed on the side surface of the opening unit 8 to expose the pad 3 to the outside of the device. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
この発明は、プリント配線基板への実装効率を高め、高密度実装を可能にし、はんだ接続の信頼性の高い実装を実現できるチップ状の半導体装置及びその製造方法に関する。
【０００２】
【従来の技術】
近年、携帯電話に代表されるように、電子機器は、よりコンパクトにより多機能化してきている。これらの電子機器には、多くの半導体装置が使用されている。当該半導体装置のパッケージ化にも軽薄短小の要求に答えるように、ＩＣチップと同程度のサイズでのパッケージであるＣｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ（以下、ＣＳＰと称す。）の方向に進んでいる。
【０００３】
パッケージされた複数個のＩＣモジュールは、多層プリント配線基板等に電気的に接続される。この電気的に接続される手段として、小さなはんだボールを多数配置したパッケージの外部端子に用いるＢａｌｌ Ｇｒｉｄ Ａｒｒａｙ（以下、ＢＧＡと称す。）パッケージの方向に進んでいる。
【０００４】
通常、ＢＧＡパッケージに封止された半導体装置の半導体回路基板には、円形の開口部が２次元アレイ状に形成され、当該開口部から半導体チップに接続された導体の一部を露出してパッドが形成される。吸着器具により、開口部に対応した直径のはんだボールを吸着し、当該はんだボールにフラックスを塗布した後、はんだボールをパッド上に転写する。半導体装置をリフロー炉に入れることにより、所定の大きさの球状の突起電極（以下、はんだ端子と称す。）が形成される。
【０００５】
従来の構造では、リフロー工程時、はんだボールの濡れ性が悪く、半導体装置のパッドと接合強度が弱いはんだ端子が発生する。これは、パッドがはんだボールにより閉塞され、リフロー工程時にパッドに残留したフラックスによってはんだボールの濡れ性が悪化するためである。その結果、半導体装置の歩留まりが低下し、コストアップを招いていた。
【０００６】
この従来の問題を解決する為、半導体回路基板に２次元アレイ状に形成されパッドを露出してはんだ端子を形成する開口部の側面上端に円弧形状の凹部を形成する。凹部上端には、パッド上に搭載されたはんだボールの表面が接触しないように、はんだボールの表面と凹部の間に通路を形成し、リフロー工程時に蒸発したフラックスが、その通路を介して逃げ出す経路を形成した（例えば、特許文献１参照）。
【０００７】
しかしながら、従来の半導体装置では、開口部内でフラックスの充満を防ぐ為、当該半導体回路基板上にはんだボールの表面と凹部の間に形成した通路により、開口部の側面上端にガス抜きのための所定の傾きを設けていた。
【０００８】
従来、開口部の側面上端にガス抜きの用傾きは、半導体装置の製造工程で形成されていたが、半導体装置の基板製造工程や製造時の諸条件に影響され、均一な傾きを達成することができなかった。例えば、凹部の傾きが大きすぎた場合、リフロー工程時、融解したはんだボールが凹部から流れ出す結果を招いていた。また、凹部の傾きが小さい、即ち、急進しすぎた場合、リフロー工程時、フラックのガスが十分に凹部から抜けきらず、接続不良を生じていた。
【０００９】
更に、半導体装置のはんだ端子をプリント配線基板上のパッドに実装する際、半導体装置のはんだ端子とプリント配線基板のパッドにスクリーン印刷されたはんだの融点がそれぞれ異なる。半導体装置のはんだ端子が所定の温度で融解後、プリント配線基板のクリームはんだに含有するフラックス成分が揮散する。その後、プリント配線基板のはんだが融解し、揮散したフラックス成分が半導体装置の開口部内に充満し、半導体装置のはんだとプリント配線基板のはんだとが十分混ざり合うことなく、プリント配線基板上に形成されたパッドとの接合強度を十分には保つことが出来なかった。
【００１０】
【特許文献１】
特開平１０−２５６４１８号公報（第４頁〜第５、第１図、第２図、第１１図）
【００１１】
【発明が解決しようとする課題】
上記した従来技術の半導体装置では、半導体装置のパッド上に形成されるはんだ端子との接続不良、及びプリント配線基板上のパッドとの接続不良の点で問題があった。
【００１２】
そこで、この発明は上記の問題を解決するためになされたものであり、はんだとパッドとの接続信頼性を高めた半導体装置及びその製造方法を提供することを目的とする。
【００１３】
【課題を解決するための手段】
この発明の半導体装置は、半導体素子と、前記半導体素子の支持基板となるテープと、前記半導体素子の電極となるパッドと、前記パッドを外部に露出するため、前記テープに前記パッドの径よりも小さい所定の大きさを有する開口部を設け、前記開口部の側面上に空隙を有するスリットを形成したことを特徴とする。
【００１４】
このような構成によれば、半導体装置のはんだとパッドとの接続信頼性を高めることができる。
【００１５】
また、この発明の半導体装置の製造方法は、半導体素子の支持基板となるテープに所定の大きさのスリットを有する開口部を設けるステップと、前記半導体素子の電極となるパッドやパターンを形成するため、銅箔を前記テープに圧着し、前記銅箔をエッチングするステップと、前記半導体素子を支持基板となるテープ上の所定の位置に搭載し、半導体素子の電極と前記パッドとを電気的に接続するステップと、前記半導体素子が搭載されたテープに所定の樹脂を用いて封止し、前記開口部にフラックス成分を含有したクリームはんだを印刷するステップと、前記クリームはんだを融解し、凝固することによりはんだ端子をパッド上に形成するステップとを有し、前記クリームはんだが融解する際、前記フラックスが前記スリットを介して蒸発することを特徴とする。
【００１６】
このような構成によれば、半導体装置の製造方法に於いて、はんだとパッドとの接続信頼性を高めることができる。
【００１７】
【発明の実施の形態】
以下、図面を参照してこの発明の実施形態を説明する。
【００１８】
図１は、この発明の一実施形態に係わるＣＳＰ型半導体装置の接合部を示す概略平面図である。図２は、同実施形態に係わり、ＣＳＰ型半導体装置の接合部がプリント配線基板上のパッドに接合された状態を示すラインＡに沿った断面図である。図３は、同実施形態に係わり、ＣＳＰ型半導体装置の接合部がプリント配線基板上のパッドに接合された状態を示すラインＢに沿った断面図である。
【００１９】
図１〜図３を参照して、この発明の第一の実施形態を以下の通り説明する。この半導体装置２０には、絶縁層を介して半導体素子１４及び配線パターン２の一部には、信号入出力端子の一部を成すパッド３が設けられている。テープ４は、この半導体装置２０のサブストレート（インターポーザ）として使用され、そのテープ４を上下方向に貫通する開口部８が所定の位置に形成される。半導体装置２０の開口部８が図１に例示される。
【００２０】
このテープ４は、例えば、ポリミド系樹脂から構成され、前記パッド３の中央部を除いて当該パッド３の中央周辺部および半導体回路基板１の底面全体を覆うようにして当該半導体回路基板１上に接着されている。そして、テープ４と半導体回路基板１により挟まったパッド３の下面一部が開口部８から下方向に露出されている。パッド３の直径は、開口部８の直径よりも大きい。従って、パッド３の外周は、テープ４により押さえ込まれている為、半導体回路基板１からのパッド３の剥離を防止することができる。
【００２１】
テープ４により囲まれた領域内のパッド３の中央部には、プリント配線基板１０上のパッド９に印刷された印刷はんだ７と電気的結合を行うべく、所定の径を有する球状に形成されたはんだボールにより、はんだ端子５が装備されており、当該はんだ端子５はパッド３に結合されている。この場合、はんだ端子５は、図２及び図３に示された通りテープ４から一部露出した状態でパッド３の中央部に装備され、はんだボールが当該パッド３に、リフローなどの加熱溶着によって固着装備されている。
【００２２】
この発明の一実施形態の構成によれば、図１に示す通り、この開口部８の側面に４つのスリット６が対角線上に等間隔で形成されている。このスリット６は、パッド３上に覆い被さった開口部８の側面を半径方向に向かって短冊状に形成されている。従って、はんだ端子５の外表面は、開口部８のスリット６に対して、所定の空隙を形成する。この空隙の長さは、図１に示す通り、半導体置のパッドの半径と開口部８の半径の差分である。
【００２３】
図３に示す通り、リフロー工程時に印刷はんだ７に塗布されたフラックス１１が蒸発するが、蒸発したフラックス１１はスロット６を通って抜けて開口部８の外に逃げて行く。その結果、蒸発したフラックス１１の余剰分や残留分が開口部８の内に充満することはく適度な濡れ性となり、リフロー工程時、はんだ端子５は印刷はんだ７と共に順次融解し、凝固して接合強度を向上することができる。同様に、半導体回路基板１のパッド３上にフラックス成分を塗布したはんだボールをスクリーン印刷し、リフロー工程時、塗布されたフラックス成分が当該スリットから効率よく蒸発してくれるので、パッド３上にはんだ端子５を装着することできる。
【００２４】
この発明の構成によれば、半導体回路基板１のパッド３上に接続信頼性を高めたはんだ端子５を装着することができ、更に、はんだ端子５を形成するはんだボールは、融解した際、開口部８に設けられたスリット６からははみ出されず、蒸発したフラックス１１の余剰分や残留分を当該スリット６を通って外部に自然に排出される。接着剤の残留フラックスが、開口部８の内に閉じ込められることがなくなるので、開口部８の内に残留フラックスにより生じる気泡等が閉じ込められて接合強度を低下するという不具合をほぼ確実に改善できる。
【００２５】
次に、図４〜図６を参照して、この発明の一実施形態に係わる半導体装置２０の製造方法を説明する。
【００２６】
まず、図４（ａ）に示す通り、インターポーザの樹脂基材（支持基板）として約５０〜７０マイクロ厚の高耐熱ポリミド樹脂、または、ガラスエポキシ樹脂のテープ４を用意し、半導体回路基板１上に、例えば、０．５ｍｍ間隔でアレイ形状に配置される０．３ｍｍφのパッド３の位置にあわせて、０．２８ｍｍφのテープ開口部８として穿孔する。
【００２７】
ここでの穿孔の方法は、レーザによる穴あけ、まるいは、金型による打ち抜きである。特に、レーザによる穴あけは、炭酸ガスレーザトレーパニング加工により２〜３層のガラスエポキシテープやポリミドテープに０．２８ｍｍφの穴をスリット付で順次穴をあけることができる。スリットの位置、間隔や幅（長さ）は、事前にレーザ加工機にプログラミングされている。
【００２８】
金型による打ち抜き加工の場合、クリアランスを５マイクロに設計して、超硬ピン型と焼き入れ受け型によるスリット同時形成の金型で、０．２８ｍｍφのテープ開口部８を２〜３層のガラスエポキシテープやポリミドテープに打ち抜き加工する。
【００２９】
ポリミド樹脂テープ４の片面に絶縁接着剤を介して、図４（ｂ）に示す通り、約１８マイクロ厚の銅箔１２を圧着する。穿孔されたテープ開口部８上に銅箔１２が覆い被さった状態となる。
【００３０】
続いて、各パターン２やパッド３に対応する銅箔１２に耐エッチング性のレジスト（図示せず）を被覆し、銅箔１２をパターニングする。図５（ａ）に示す通り、パッド３は、テープ開口部８の直径より僅かに大きな直径（０．３ｍｍφ）でパターニングされる。
【００３１】
次に、図面では省略しているが、パッドの電極部分にメッキを施し、テープ４の略中央に半導体素子チップ１４をダイボンデイングする。ここでのメッキは、ニッケルを用い電解メッキ法、無電解メッキ法、又は、ディプ法で形成され、例えば、１〜２０μｍ程度の薄い膜厚で形成される。
図５（ｂ）に示される通り、半導体素子１４の各電極と所定のパッドの電極をボインディングワイヤ１３を介して接続する。ここでのボンディングワイヤ４には金線、アルミニウム線、銅線等が使用される。
【００３２】
ボインディングワイヤ１３が半導体素子１４に接続後、図６（ａ）に示す通り、封止樹脂１５で被覆する。この時点では、はんだ端子５ははんだ開口部８には形成されていない。
【００３３】
はんだ端子５をはんだ開口部８に形成するため、クリームはんだ１８が図６（ｂ）のスクリーン印刷により半導体回路基板１上の所定の接続パッド３上に形成される。まず、半導体回路基板１上に形成されたテープ開口部８のパッド３にメタルマスク１６の開口部１７を位置あわせし、スキージ１９を所定の方向に押圧操作する。メタルマスク１６の開口部１７にクリームはんだ１８が充填され、メタルマスク４０とテープ４の厚さ分、クリームはんだ１８がパッド３上に堆積される。クリームはんだ１８の充填後、メタルマスク１６を取り去るとパッド３上にはんだの表面張力によりはんだがボール状、又は、バンプ状に形成される。はんだボールの厚みは、狭ピッチの接続信頼性を基準として設定されている。ここで使用するクリームはんだ１８は、例えば、鉛入り共晶はんだの場合、スズ６３重量％、鉛３７重量％で組成されている。このクリームはんだには、更に、フラックス成分が含有される。
【００３４】
その後、図６（ｃ）に示す通り、半導体回路基板１をリフロー炉２１に搬入し、約１８３度で共晶はんだを溶解し、凝固させることにより所定のパッド３上にはんだ端子５を形成することができる。このリフロー工程時、印刷されたクリームはんだから揮散したフラックス成分は、効率よく、スリット６を介して外に排出される。
【００３５】
次に、図７を参照して、この発明の一実施形態に係わる半導体装置２０をプリント配線基板に接続実装する方法を説明する。
【００３６】
図６（ｂ）と同様な印刷工程で、プリント配線基板１０上の０．２８ｍｍφの開口部８にメタルマスクの開口部を位置あわせし、スキージを所定の方向に押圧操作する。メタルマスクの開口部にクリームはんだが充填され、メタルマスクの厚さ分、クリームはんだがパッド９上に堆積される。クリームはんだ７の充填後、メタルマスクを取り去るとパッド９上にペースト状のクリームはんだ層が形成される。ここでのクリームはんだ７は、例えば、無鉛はんだの場合、スズ９３．５重量％、銀３重量％、銅０．５重量％で組成される。このクリームはんだ７には、更に、フラックス成分が含有される。
【００３７】
次に、図６で製造された半導体装置２０を準備し、図７（ａ）に示す通り、プリント配線基板１０のパッド９上に、半導体装置２０のはんだ端子５を精度よく位置合わせして載置する。半導体装置２０のはんだ端子５とプリント配線基板１０のパッド９とはクリームはんだ７の層を介して仮接着状態となる。
【００３８】
図７（ｂ）に示すリフロー炉２１において、プリント配線基板１０上に仮接着状態の半導体装置２０を加熱する。まず、共晶はんだで形成されたはんだ端子５が、約１８３度で溶解すると共に、鉛フリーで形成されたクリームはんだ７からフラックス成分がテープ開口部８内に向け揮散する。更に、リフロー炉２１を加熱し、約２１９度でクリームはんだが溶解し、融解していたはんだ端子５と混ざり合う。半導体装置２０のテープ開口部端子５ではんだが混ざり合う際、この発明の構成によれば、図３に示す通り、フラックスのガスが充満することなく、スリット６を経由して効率よく吐き出すことができる。クリームはんだ７のフラックス成分が蒸発後、それぞれのはんだ合金が熔融して半導体装置２０の自重で下方に沈んだ状態で再凝固させることにより、図７（ｃ）に示す通り、良好な接続端子２２を形成する。この接続端子２２の形成によりプリント配線基板１９のパッド９と半導体装置２０のパッド３との間が電気的に接続されかつ機械的に接合される。
【００３９】
尚、この発明の実施形態では、半導体装置２０のパッド３は、図１に示した通り、円形であるが、これに限らず、例えば、図８に示す通り、多角形で構成しても良い。この場合、フラックス成分を抜くためのスリット６は、多角形の頂点に全て、又は、少なくとも１個以上設ける。
【００４０】
【発明の効果】
以上説明したように、この発明によれば、はんだとパッドとの接続信頼性を高めることができる。
【図面の簡単な説明】
【図１】この発明の一実施形態に係わるＣＳＰ型半導体装置の接合部を示す概略平面図。
【図２】同実施形態に係わり、ＣＳＰ型半導体装置の接合部がプリント配線基板上のパッドに接合された状態を示すラインＡに沿った断面図。
【図３】同実施形態に係わり、ＣＳＰ型半導体装置の接合部がプリント配線基板上のパッドに接合された状態を示すラインＢに沿った断面図。
【図４】この発明の一実施形態に係わる半導体装置の製造方法を説明する図。
【図５】この発明の一実施形態に係わる半導体装置の製造方法を説明する図。
【図６】この発明の一実施形態に係わる半導体装置の製造方法を説明する図。
【図７】この発明の一実施形態に係わる半導体装置をプリント配線基板に実装する方法を説明する。
【図８】この発明の別の実施形態に係わるＣＳＰ型半導体装置の接合部を示す概略平面図。
【符号の説明】
１・・・半導体回路基板、２・・・パターン、３・９・・・パッド、４・・・テープ、
５・・・はんだ端子、６・・・スリット、７・１８・・・クリームはんだ、
８・・・テープ開口部、１０・・・プリント配線基板、１１・・・フラックス揮散、
１２・・・銅箔、１３・・・ボンディングワイヤー、１４・・・半導体素子、
１５・・・封止樹脂、１６・・・スクリーンマスク、１７・・・開口部、１９・・・スキージ
２０・・・半導体装置、２１・・・リフロー炉、２２・・・接続端子[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a chip-shaped semiconductor device capable of improving mounting efficiency on a printed wiring board, enabling high-density mounting, and realizing mounting with high reliability of solder connection, and a method of manufacturing the same.
[0002]
[Prior art]
In recent years, as represented by mobile phones, electronic devices have become more compact and multifunctional. Many electronic devices are used in these electronic devices. In order to respond to the demand for lightness, small size and small size in packaging of the semiconductor device, a chip size package (hereinafter, referred to as a CSP), which is a package having a size similar to that of an IC chip, is being developed.
[0003]
The plurality of packaged IC modules are electrically connected to a multilayer printed wiring board or the like. As a means for the electrical connection, a ball grid array (hereinafter, referred to as BGA) package is used which is used as an external terminal of a package in which a large number of small solder balls are arranged.
[0004]
Normally, a circular opening is formed in a two-dimensional array on a semiconductor circuit board of a semiconductor device sealed in a BGA package, and a part of a conductor connected to a semiconductor chip is exposed from the opening to form a pad. Is formed. A solder ball having a diameter corresponding to the opening is sucked by a suction device, a flux is applied to the solder ball, and then the solder ball is transferred onto a pad. By placing the semiconductor device in a reflow furnace, a spherical projecting electrode (hereinafter, referred to as a solder terminal) having a predetermined size is formed.
[0005]
In the conventional structure, during the reflow process, the solder balls have poor wettability, and solder terminals having low bonding strength with pads of the semiconductor device are generated. This is because the pad is closed by the solder ball, and the flux remaining on the pad during the reflow process deteriorates the wettability of the solder ball. As a result, the yield of semiconductor devices has been reduced, leading to an increase in cost.
[0006]
In order to solve this conventional problem, an arc-shaped concave portion is formed at the upper end of the side surface of an opening formed in a two-dimensional array on a semiconductor circuit board to expose pads and form solder terminals. A path is formed between the surface of the solder ball and the concave portion so that the surface of the solder ball mounted on the pad does not contact the upper end of the concave portion, and a path through which the flux evaporated during the reflow process escapes through the path. (See, for example, Patent Document 1).
[0007]
However, in the conventional semiconductor device, in order to prevent the filling of the flux in the opening, a passage formed between the surface of the solder ball and the concave portion on the semiconductor circuit board has a predetermined upper side edge of the opening for venting. The inclination of was provided.
[0008]
Conventionally, the inclination for degassing is formed at the upper end of the side surface of the opening in the manufacturing process of the semiconductor device, but it is affected by various conditions during the manufacturing process of the substrate and the manufacturing process of the semiconductor device, and a uniform inclination is achieved. Could not. For example, when the inclination of the concave portion is too large, the result that the molten solder ball flows out of the concave portion during the reflow process has been caused. In addition, when the inclination of the concave portion is small, that is, when the concave portion is too abrupt, during the reflow step, the gas of the flux cannot be sufficiently removed from the concave portion, and a connection failure has occurred.
[0009]
Further, when mounting the solder terminals of the semiconductor device on the pads on the printed wiring board, the solder terminals of the semiconductor device and the solder printed on the pads of the printed wiring board have different melting points. After the solder terminals of the semiconductor device are melted at a predetermined temperature, the flux component contained in the cream solder on the printed wiring board volatilizes. Thereafter, the solder of the printed wiring board is melted, and the volatilized flux component fills the opening of the semiconductor device, and the solder of the semiconductor device and the solder of the printed wiring board are formed on the printed wiring board without being sufficiently mixed. It was not possible to maintain sufficient bonding strength with the pad.
[0010]
[Patent Document 1]
JP-A-10-256418 (pages 4 to 5, FIG. 1, FIG. 2, FIG. 11)
[0011]
[Problems to be solved by the invention]
The above-described prior art semiconductor device has a problem in terms of poor connection with a solder terminal formed on a pad of the semiconductor device and poor connection with a pad on a printed wiring board.
[0012]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device with improved connection reliability between a solder and a pad and a method of manufacturing the same.
[0013]
[Means for Solving the Problems]
The semiconductor device of the present invention includes a semiconductor element, a tape serving as a support substrate of the semiconductor element, a pad serving as an electrode of the semiconductor element, and the pad being exposed to the outside. An opening having a small predetermined size is provided, and a slit having a gap is formed on a side surface of the opening.
[0014]
According to such a configuration, the connection reliability between the solder and the pad of the semiconductor device can be improved.
[0015]
Further, according to a method of manufacturing a semiconductor device of the present invention, a step of providing an opening having a slit of a predetermined size in a tape serving as a support substrate of a semiconductor element, and forming pads and patterns serving as electrodes of the semiconductor element are provided. Pressing a copper foil on the tape and etching the copper foil, mounting the semiconductor element at a predetermined position on the tape serving as a support substrate, and electrically connecting an electrode of the semiconductor element to the pad. And sealing the tape on which the semiconductor element is mounted with a predetermined resin, printing cream solder containing a flux component in the opening, and melting and solidifying the cream solder. Forming a solder terminal on the pad by melting the cream solder through the slit when the cream solder is melted. Characterized in that it.
[0016]
According to such a configuration, the connection reliability between the solder and the pad can be improved in the method of manufacturing a semiconductor device.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0018]
FIG. 1 is a schematic plan view showing a joint of a CSP type semiconductor device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view taken along a line A showing a state in which a bonding portion of the CSP type semiconductor device is bonded to a pad on a printed wiring board according to the first embodiment. FIG. 3 is a cross-sectional view taken along a line B showing a state in which a bonding portion of the CSP type semiconductor device is bonded to a pad on a printed wiring board according to the first embodiment.
[0019]
A first embodiment of the present invention will be described below with reference to FIGS. In this semiconductor device 20, pads 3 forming a part of signal input / output terminals are provided on a part of the semiconductor element 14 and the wiring pattern 2 via an insulating layer. The tape 4 is used as a substrate (interposer) of the semiconductor device 20, and an opening 8 penetrating the tape 4 in a vertical direction is formed at a predetermined position. The opening 8 of the semiconductor device 20 is illustrated in FIG.
[0020]
The tape 4 is made of, for example, a polyimide resin, and is formed on the semiconductor circuit board 1 so as to cover the central periphery of the pad 3 and the entire bottom surface of the semiconductor circuit board 1 except for the center of the pad 3. Glued. Then, a part of the lower surface of the pad 3 sandwiched between the tape 4 and the semiconductor circuit board 1 is exposed downward from the opening 8. The diameter of the pad 3 is larger than the diameter of the opening 8. Therefore, since the outer periphery of the pad 3 is held down by the tape 4, the separation of the pad 3 from the semiconductor circuit board 1 can be prevented.
[0021]
A spherical portion having a predetermined diameter is formed at a central portion of the pad 3 in an area surrounded by the tape 4 so as to electrically couple with the printed solder 7 printed on the pad 9 on the printed wiring board 10. Solder terminals 5 are provided by solder balls, and the solder terminals 5 are connected to the pads 3. In this case, the solder terminal 5 is provided at the center of the pad 3 in a state where it is partially exposed from the tape 4 as shown in FIGS. 2 and 3, and the solder ball is attached to the pad 3 by heat welding such as reflow. Equipped with anchorage.
[0022]
According to the configuration of the embodiment of the present invention, as shown in FIG. 1, four slits 6 are formed on the side surface of the opening 8 at equal intervals on a diagonal line. The slit 6 is formed in a rectangular shape in the radial direction on the side surface of the opening 8 covering the pad 3. Therefore, the outer surface of the solder terminal 5 forms a predetermined gap with respect to the slit 6 of the opening 8. The length of the gap is a difference between the radius of the pad of the semiconductor device and the radius of the opening 8 as shown in FIG.
[0023]
As shown in FIG. 3, the flux 11 applied to the printed solder 7 during the reflow process evaporates, and the evaporated flux 11 escapes through the slot 6 and out of the opening 8. As a result, the excess or residual portion of the evaporated flux 11 does not fill the opening 8 but has an appropriate wettability. During the reflow process, the solder terminal 5 is sequentially melted and solidified together with the printed solder 7. The joining strength can be improved. Similarly, a solder ball coated with a flux component is screen-printed on the pad 3 of the semiconductor circuit board 1, and the applied flux component evaporates efficiently from the slit during the reflow process. Terminal 5 can be attached.
[0024]
According to the configuration of the present invention, the solder terminals 5 with improved connection reliability can be mounted on the pads 3 of the semiconductor circuit board 1. Further, when the solder balls forming the solder terminals 5 are melted, the solder balls 5 The excess or residual portion of the evaporated flux 11 does not protrude from the slit 6 provided in the portion 8, and is naturally discharged to the outside through the slit 6. Since the residual flux of the adhesive is not confined in the opening 8, it is possible to almost certainly remedy the problem that bubbles and the like generated by the residual flux are confined in the opening 8 and the bonding strength is reduced.
[0025]
Next, a method for manufacturing the semiconductor device 20 according to one embodiment of the present invention will be described with reference to FIGS.
[0026]
First, as shown in FIG. 4A, a tape 4 of a high heat-resistant polyamide resin or a glass epoxy resin having a thickness of about 50 to 70 μm is prepared as a resin base material (supporting substrate) of the interposer. Then, for example, holes are punched as 0.28 mmφ tape openings 8 in accordance with the positions of the 0.3 mmφ pads 3 arranged in an array at 0.5 mm intervals.
[0027]
The method of perforation here is to make a hole by a laser, or to punch by a mold. In particular, when drilling with a laser, a 0.28 mmφ hole can be sequentially drilled with a slit in a glass epoxy tape or a polyimide tape having two or three layers by carbon dioxide laser tray panning. The position, interval and width (length) of the slit are programmed in the laser processing machine in advance.
[0028]
In the case of punching using a die, the clearance is designed to be 5 micron, and a slit is simultaneously formed by a carbide pin type and a quenching receiving type, and a tape opening 8 of 0.28 mmφ is formed by two to three layers of glass. Punched into epoxy tape or polyimide tape.
[0029]
As shown in FIG. 4B, a copper foil 12 having a thickness of about 18 μm is pressure-bonded to one side of the polyimide resin tape 4 via an insulating adhesive. The copper foil 12 covers the perforated tape opening 8.
[0030]
Subsequently, the copper foil 12 corresponding to each pattern 2 and the pad 3 is coated with an etching resistant resist (not shown), and the copper foil 12 is patterned. As shown in FIG. 5A, the pad 3 is patterned with a diameter (0.3 mmφ) slightly larger than the diameter of the tape opening 8.
[0031]
Next, although not shown in the drawing, plating is applied to the electrode portion of the pad, and the semiconductor element chip 14 is die-bonded to substantially the center of the tape 4. The plating here is formed by nickel using an electrolytic plating method, an electroless plating method, or a dip method, for example, with a thin film thickness of about 1 to 20 μm.
As shown in FIG. 5B, each electrode of the semiconductor element 14 is connected to an electrode of a predetermined pad via a binding wire 13. Here, a gold wire, an aluminum wire, a copper wire, or the like is used as the bonding wire 4.
[0032]
After the binding wire 13 is connected to the semiconductor element 14, it is covered with a sealing resin 15 as shown in FIG. At this time, the solder terminal 5 has not been formed in the solder opening 8.
[0033]
In order to form the solder terminals 5 in the solder openings 8, cream solder 18 is formed on predetermined connection pads 3 on the semiconductor circuit board 1 by screen printing of FIG. 6B. First, the opening 17 of the metal mask 16 is aligned with the pad 3 of the tape opening 8 formed on the semiconductor circuit board 1, and the squeegee 19 is pressed in a predetermined direction. The opening 17 of the metal mask 16 is filled with the cream solder 18, and the cream solder 18 is deposited on the pad 3 by the thickness of the metal mask 40 and the tape 4. When the metal mask 16 is removed after the filling of the cream solder 18, the solder is formed in a ball shape or a bump shape on the pad 3 due to the surface tension of the solder. The thickness of the solder ball is set based on the connection reliability at a narrow pitch. The cream solder 18 used here is composed of, for example, 63% by weight of tin and 37% by weight of lead in the case of a eutectic solder containing lead. This cream solder further contains a flux component.
[0034]
After that, as shown in FIG. 6C, the semiconductor circuit board 1 is carried into the reflow furnace 21 and the eutectic solder is melted at about 183 degrees and solidified to form the solder terminals 5 on the predetermined pads 3. be able to. During this reflow process, the flux component volatilized from the printed cream solder is efficiently discharged to the outside through the slit 6.
[0035]
Next, a method of connecting and mounting the semiconductor device 20 according to one embodiment of the present invention on a printed wiring board will be described with reference to FIG.
[0036]
6B, the opening of the metal mask is aligned with the opening 8 of 0.28 mmφ on the printed wiring board 10, and the squeegee is pressed in a predetermined direction. The opening of the metal mask is filled with cream solder, and the cream solder is deposited on the pad 9 by the thickness of the metal mask. When the metal mask is removed after the filling of the cream solder 7, a paste-like cream solder layer is formed on the pad 9. The cream solder 7 here is composed of, for example, 93.5% by weight of tin, 3% by weight of silver, and 0.5% by weight of copper in the case of a lead-free solder. The cream solder 7 further contains a flux component.
[0037]
Next, the semiconductor device 20 manufactured in FIG. 6 is prepared, and as shown in FIG. 7A, the solder terminals 5 of the semiconductor device 20 are accurately positioned and mounted on the pads 9 of the printed wiring board 10. Place. The solder terminals 5 of the semiconductor device 20 and the pads 9 of the printed wiring board 10 are temporarily bonded via the cream solder 7 layer.
[0038]
In a reflow furnace 21 shown in FIG. 7B, the semiconductor device 20 in a temporarily bonded state on the printed wiring board 10 is heated. First, the solder terminal 5 formed of the eutectic solder is melted at about 183 degrees, and the flux component volatilizes from the lead-free cream solder 7 into the tape opening 8. Further, the reflow furnace 21 is heated to melt the cream solder at about 219 degrees and mix with the solder terminal 5 that has been melted. When the solder is mixed at the tape opening terminal 5 of the semiconductor device 20, according to the configuration of the present invention, as shown in FIG. 3, the gas of the flux can be efficiently discharged through the slit 6 without being filled with the gas of the flux. it can. After the flux components of the cream solder 7 evaporate, the respective solder alloys are melted and re-solidified in a state of sinking downward by the weight of the semiconductor device 20, so that, as shown in FIG. To form By forming the connection terminals 22, the pads 9 of the printed wiring board 19 and the pads 3 of the semiconductor device 20 are electrically connected and mechanically joined.
[0039]
In the embodiment of the present invention, the pad 3 of the semiconductor device 20 has a circular shape as shown in FIG. 1, but is not limited to this, and may have a polygonal shape as shown in FIG. . In this case, all or at least one slit 6 for extracting the flux component is provided at the vertex of the polygon.
[0040]
【The invention's effect】
As described above, according to the present invention, the connection reliability between the solder and the pad can be improved.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing a junction of a CSP type semiconductor device according to one embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along a line A showing a state in which a bonding portion of the CSP type semiconductor device is bonded to a pad on a printed wiring board according to the embodiment;
FIG. 3 is an exemplary cross-sectional view of the CSP type semiconductor device according to the embodiment, taken along line B, showing a state in which a bonding portion of the CSP type semiconductor device is bonded to a pad on a printed wiring board;
FIG. 4 is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 5 is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 6 is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
FIG. 7 illustrates a method for mounting a semiconductor device according to an embodiment of the present invention on a printed wiring board.
FIG. 8 is a schematic plan view showing a junction of a CSP type semiconductor device according to another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor circuit board, 2 ... Pattern, 3/9 ... Pad, 4 ... Tape,
5: solder terminal, 6: slit, 7.18: cream solder,
8: tape opening, 10: printed wiring board, 11: flux evaporation,
12: copper foil, 13: bonding wire, 14: semiconductor element,
15 sealing resin, 16 screen mask, 17 opening, 19 squeegee 20 semiconductor device, 21 reflow furnace, 22 connection terminal

Claims (7)

半導体素子と、前記半導体素子の支持基板となるテープと、前記半導体素子の電極となるパッドと、前記パッドを外部に露出するため、前記テープに前記パッドの径よりも小さい所定の大きさを有する開口部を設け、前記開口部の側面上に空隙を有するスリットを形成したことを特徴とする半導体装置。A semiconductor element, a tape serving as a support substrate of the semiconductor element, a pad serving as an electrode of the semiconductor element, and a tape having a predetermined size smaller than a diameter of the pad in order to expose the pad to the outside. An opening is provided, and a slit having a gap is formed on a side surface of the opening. 前記スリットは、前記開口部に対して対角線上に形成されたことを特徴とする特許請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the slit is formed diagonally with respect to the opening. 前記スリットの空隙は、前記パッド上に設けられることを特徴とする特許請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the gap of the slit is provided on the pad. 前記開口部は、前記パッドの形状に合わせて形成されることを特徴とする特許請求項３記載の半導体装置。4. The semiconductor device according to claim 3, wherein the opening is formed in accordance with a shape of the pad. 半導体素子の支持基板となるテープに所定の大きさのスリットを有する開口部を設けるステップと、前記半導体素子の電極となるパッドやパターンを形成するため、銅箔を前記テープに圧着し、前記銅箔をエッチングするステップと、前記半導体素子を支持基板となるテープ上の所定の位置に搭載し、半導体素子の電極と前記パッドとを電気的に接続するステップと、前記半導体素子が搭載されたテープに所定の樹脂を用いて封止し、前記開口部にフラックス成分を含有したクリームはんだを印刷するステップと、前記クリームはんだを融解し、凝固することによりはんだ端子をパッド上に形成するステップとを有し、前記クリームはんだが融解する際、前記フラックスが前記スリットを介して蒸発することを特徴とする半導体装置の製造方法。Providing an opening having a slit of a predetermined size in a tape serving as a support substrate of a semiconductor element, and forming a pad or a pattern serving as an electrode of the semiconductor element by pressing a copper foil on the tape, Etching a foil, mounting the semiconductor element at a predetermined position on a tape serving as a support substrate, and electrically connecting an electrode of the semiconductor element and the pad, and a tape on which the semiconductor element is mounted. Sealing with a predetermined resin, and printing a cream solder containing a flux component in the opening, melting the cream solder, and forming a solder terminal on the pad by solidification, Wherein the flux evaporates through the slit when the cream solder is melted. . 前記パッド上にはんだ端子が形成された半導体装置をプリント配線基板上のパッドに実装接続するため、前記プリント配線基板上のパッドにフラックス成分を含有したクリームはんだを印刷するステップと、前記はんだ端子とクリームはんだを順次融解し、凝固することにより、前記半導体装置のパッドと前記プリント配線基板上のパッド上に接続端子を形成するステップとを有し、前記クリームはんだが融解する際、前記フラックスが前記スリットを介して蒸発することを特徴とする特許請求項５記載の半導体装置の製造方法。In order to mount and connect a semiconductor device having a solder terminal formed on the pad to a pad on a printed wiring board, printing cream solder containing a flux component on the pad on the printed wiring board; and Forming a connection terminal on a pad of the semiconductor device and a pad on the printed wiring board by sequentially melting and solidifying the cream solder, and when the cream solder melts, the flux 6. The method for manufacturing a semiconductor device according to claim 5, wherein the evaporation is performed through a slit. レーザによる穴あけと、又は、金型による打ち抜きの何れかにより、前記開口部を穿孔すると共にスリットを形成することを特徴とする特許請求項５記載の半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 5, wherein the opening is pierced and a slit is formed by either drilling using a laser or punching using a die.
JP2003079385A 2003-03-24 2003-03-24 Semiconductor device and its manufacturing method Abandoned JP2004288892A (en)

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