EP1766673A1 - Methods of forming lead free solder bumps and related structures - Google Patents
Methods of forming lead free solder bumps and related structuresInfo
- Publication number
- EP1766673A1 EP1766673A1 EP05766874A EP05766874A EP1766673A1 EP 1766673 A1 EP1766673 A1 EP 1766673A1 EP 05766874 A EP05766874 A EP 05766874A EP 05766874 A EP05766874 A EP 05766874A EP 1766673 A1 EP1766673 A1 EP 1766673A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- solder
- plating
- under bump
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 316
- 238000000034 method Methods 0.000 title claims abstract description 60
- 238000005272 metallurgy Methods 0.000 claims abstract description 188
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 170
- 239000010949 copper Substances 0.000 claims abstract description 96
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 85
- 229910052802 copper Inorganic materials 0.000 claims abstract description 85
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000007747 plating Methods 0.000 claims description 194
- 229910052718 tin Inorganic materials 0.000 claims description 132
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 131
- 229910052751 metal Inorganic materials 0.000 claims description 113
- 239000002184 metal Substances 0.000 claims description 113
- 229910052709 silver Inorganic materials 0.000 claims description 110
- 239000004332 silver Substances 0.000 claims description 108
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 104
- 229910045601 alloy Inorganic materials 0.000 claims description 57
- 239000000956 alloy Substances 0.000 claims description 57
- 150000002739 metals Chemical class 0.000 claims description 56
- 238000002844 melting Methods 0.000 claims description 43
- 230000008018 melting Effects 0.000 claims description 43
- 238000010438 heat treatment Methods 0.000 claims description 27
- 239000010931 gold Substances 0.000 claims description 26
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 20
- 229910052737 gold Inorganic materials 0.000 claims description 20
- 239000000203 mixture Substances 0.000 claims description 16
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 14
- 229910052787 antimony Inorganic materials 0.000 claims description 14
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 14
- 229910052797 bismuth Inorganic materials 0.000 claims description 14
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 14
- 239000011651 chromium Substances 0.000 claims description 14
- 229910052738 indium Inorganic materials 0.000 claims description 14
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 14
- 229910052725 zinc Inorganic materials 0.000 claims description 14
- 239000011701 zinc Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 12
- 239000010936 titanium Substances 0.000 claims description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 10
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052804 chromium Inorganic materials 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 6
- 238000002156 mixing Methods 0.000 claims description 4
- 240000007472 Leucaena leucocephala Species 0.000 claims 1
- 235000010643 Leucaena leucocephala Nutrition 0.000 claims 1
- 239000011135 tin Substances 0.000 description 121
- 230000004888 barrier function Effects 0.000 description 43
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 11
- 238000002161 passivation Methods 0.000 description 8
- 229910007637 SnAg Inorganic materials 0.000 description 6
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 6
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 6
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 229910020836 Sn-Ag Inorganic materials 0.000 description 3
- 229910020988 Sn—Ag Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005275 alloying Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000113 differential scanning calorimetry Methods 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000002244 precipitate Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000009987 spinning Methods 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 229910000597 tin-copper alloy Inorganic materials 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
Classifications
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Definitions
- a 2 ⁇ m Ag/ 50 ⁇ m Sn electroplated metal stack may provide the Sn-Ag solder alloy with a composition of Sn-3.5wt.%Ag, with a melting temperature of 227 0 C, determined using a single peak of DSC analysis.
- the single peak temperature may decrease to 222 0 C.
- metal stacks formed by multi-step electroplating can be successfully transformed to solder alloys by reflow annealing. The disclosure of the Esawa reference is hereby incorporated herein in its entirety by reference.
- a method of forming an electronic device may include forming an under bump seed metallurgy layer on an electronic substrate.
- a nickel layer may be formed on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the nickel layer and the electronic substrate, and portions of the under bump seed metallurgy layer may be free of the nickel layer.
- a lead free solder layer may be formed on the nickel layer so that the nickel layer is between the solder layer and the under bump seed metallurgy layer.
- a copper layer may be formed on the under bump seed metallurgy layer before forming the nickel layer so that the under bump seed metallurgy layer is between the copper layer and the electronic substrate, and so that the copper layer is between the nickel layer and the under bump seed metallurgy layer.
- portions of the under bump seed metallurgy layer may be free of the copper layer.
- a plating mask may be formed on the under bump seed metallurgy layer before forming the copper layer, and portions of the under bump seed metallurgy layer may be exposed through the plating mask.
- the copper layer may be formed by plating the copper layer on the portions of the under bump seed metallurgy layer exposed through the plating mask
- the nickel layer may be formed by plating the nickel layer on the copper layer
- the solder layer may be formed by plating the solder layer on the nickel layer.
- the plating mask may then be removed after forming the solder layer, and portions of the under bump seed metallurgy layer free of the copper and/or nickel layers may be removed after removing the plating mask.
- the nickel layer may have a thickness in .
- the solder layer may comprise a lead-free solder layer, for example, including tin and at least one of silver, bismuth, copper, indium, antimony, gold, and/or zinc, and a weight percent of tin in the solder may be greater than about 95 weight percent. More particularly, a weight percent of tin in the solder layer may be in the range of about 97 weight percent and about 99.5 weight percent.
- Forming the solder layer may include forming a first layer of tin and forming a second layer of silver, bismuth, copper, indium, antimony, gold, and/or zinc, and the first layer may be between the second layer and the nickel layer.
- the first layer of tin may be greater than about 95 weight percent of the solder layer. More particularly, the first layer of tin may be in the range of about 97 weight percent and about 99.5 weight percent of the solder layer, and the first and second layers may be heated to provide an alloy thereof after forming the solder layer. More particularly, heating the first and second layers may include heating the first and second layers to a temperature that is less than a melting temperature of the first and/or second layers.
- heating the first and second layers may include heating the first and second layers to a temperature that is less than a melting temperature of one of the first or second layers and greater than a melting temperature of the other of the first or second layers.
- heating the first and second layers may include heating the first and second layers to a temperature that is less than a melting temperature of either of the first and second layers and above a melting temperature of the alloy thereof.
- forming the under bump seed metallurgy layer may include forming an adhesion layer on the electronic substrate, and forming a conduction layer on the adhesion layer such that the adhesion layer is between the conduction layer and the electronic substrate.
- the adhesion layer and the conduction layer may include different materials.
- the adhesion layer may include Ti (titanium), TiW (titanium-tungsten), TiN (titanium nitride), and/or Cr (chromium), and the conduction layer may include Cu (copper), Ag (silver), and/or Au (gold).
- forming the solder layer may include plating first and second portions of the solder layer using a same plating bath including first and second plating metals.
- the first portion of the solder layer may be plated in the plating bath using a first plating voltage and/or current so that the first portion of the solder layer has a first concentration of the first plating metal.
- the second portion of the solder layer may be plated in the plating bath using a second plating voltage and/or current so that the second portion of the solder layer has a second concentration of the first plating metal different than the first concentration.
- a method of forming an electronic device may include forming an under bump seed metallurgy layer on an electronic substrate.
- a first solder layer including a first metal may be formed on portions of the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the first solder layer and the electronic substrate.
- a second solder layer including a second metal may be formed on the first solder layer so that the first solder layer is between the second solder layer and the under bump seed metallurgy layer.
- the first and second solder layers may then be heated to a temperature that is less than a melting temperature of the first and/or second metals to provide an alloy of the first and second metals.
- the first metal may include one of silver or tin
- the second metal may include the other of silver or tin.
- the first solder layer may be a layer of tin
- the second solder layer may be a layer of silver.
- heating the first and second solder layers may include heating the first and second solder layers to a temperature that is less than a melting temperature of either of the first and second metals and that is greater than a melting temperature of the alloy of the first and second metals.
- Forming the first solder layer may include forming a layer of the first metal
- forming the second solder layer may include forming a layer of the second metal.
- the first and second solder layers may be formed using a same plating bath including the first and second metals. Accordingly, forming the first solder layer may include plating the first solder layer using the plating bath and using a first plating voltage and/or plating current so that the first solder layer has a first concentration of the first metal. Similarly, forming the second solder layer may include plating the second solder layer using the plating bath and using a second plating voltage and/or plating current so that the second solder layer has a second concentration of the first metal different than the first concentration of the first metal.
- a plating mask may be formed on the under bump seed metallurgy layer before forming the first and second solder layers, and portions of the under bump seed metallurgy layer may be exposed through the plating mask. Accordingly, forming the first solder layer may include plating the first solder layer on the portions of the under bump seed metallurgy layer exposed through the plating mask, and forming the second solder layer may include plating the second solder layer on the first solder layer.
- a copper layer may be plated on the portions of the under bump seed metallurgy layer exposed through the plating mask before forming the first and second solder layers.
- a nickel layer may be formed on the copper layer before forming the first and second solder layers. Accordingly, the copper layer may be between the nickel layer and the under bump seed metallurgy layer, the nickel layer may be between the first solder layer and the copper layer, and the first solder layer may be between the second solder layer and the nickel layer.
- the alloy of the first and second metals may be lead free.
- the first metal may include tin and the second metal may include silver, bismuth, copper, indium, antimony, gold, and/or zinc, and a weight percent of tin in the solder may be greater than about 95 weight percent. More particularly, a weight percent of tin in the alloy of the first and second metals may be in the range of about 97 weight percent to about 99.5 weight percent.
- forming the under bump seed metallurgy layer may include forming an adhesion layer on the electronic substrate, and forming a conduction layer on the adhesion layer.
- the adhesion layer may be between the conduction layer and the electronic substrate, and the adhesion layer and the conduction layer may include different materials. More particularly, the adhesion layer may include Ti (titanium), TiW (titanium-tungsten), TiN (titanium nitride), and/or Cr (chromium), and the conduction layer may include Cu (copper), Ag (silver), and/or Au (gold).
- a method of forming an electronic device may include forming an under bump seed metallurgy layer on an electronic substrate, and first and second solder layers may be plated using a same plating bath including first and second plating metals. More particularly, the first solder layer may be plated on portions of the under bump seed metallurgy layer using the plating bath and using a first plating voltage and/or plating current so that the first solder layer has a first concentration of the first plating metal.
- the second solder layer may be plated on the first solder layer using the plating bath and using a second plating voltage and/or plating current so that the second solder layer has a second concentration of the first plating metal different than the first concentration of the first plating metal.
- the first and second solder layers may be heated to a temperature that is less than a melting temperature of the first and/or second metals to provide at least partial mixing of the first and second solder layers.
- the first metal may be tin, and a weight percent of tin in the mixture of the first and second solder layers may be greater than about 95 weight percent. More particularly, a weight percent of tin in the mixture of the first and second solder layers may be in the range of about 97 weight percent to about 99.5 weight percent.
- the first metal may include tin
- the second metal may include silver, bismuth, copper, indium, antimony, gold, and/or zinc.
- the first solder layer may have a third concentration of the second metal, the second solder layer may have a fourth concentration of the second metal, and the third and fourth concentrations may be different. More particularly, the first concentration may be greater than the second concentration, and the fourth concentration may be greater than the third concentration.
- a plating mask may be formed on the under bump seed metallurgy layer before plating the first and second solder layers such that portions of the under bump seed metallurgy layer are exposed through the plating mask.
- plating the first solder layer may include plating the first solder layer on portions of the under bump seed metallurgy layer exposed through the plating mask
- plating the second solder layer may include plating the second solder layer on the first solder layer
- the first solder layer may be between the second solder layer and the under bump seed metallurgy layer.
- a copper layer may be plated on portions of the under bump seed metallurgy layer exposed through the plating mask, and a nickel layer may be plated on the copper layer. Accordingly, the copper layer may be between the nickel layer and the under bump seed metallurgy layer, and the nickel layer may be between the first solder layer and the copper layer. In addition, the first and second solder layers may be lead free.
- an electronic device may include an electronic substrate and an under bump seed metallurgy layer on the electronic substrate.
- a nickel layer may be provided on the under bump seed metallurgy layer so that the under bump seed metallurgy layer is between the nickel layer and the electronic substrate, and portions of the under bump seed metallurgy layer may be free of the nickel layer.
- a lead free solder layer may be provided on the nickel layer so that the nickel layer is between the solder layer and the under bump seed metallurgy layer.
- a copper layer may be on the under bump seed metallurgy layer before forming the nickel layer so that the under bump seed metallurgy layer is between the copper layer and the electronic substrate, and so that the copper layer is between the nickel layer and the under bump seed metallurgy layer.
- portions of the under bump seed metallurgy layer may be free of the copper layer.
- the nickel layer may have a thickness in the range of about 1 ⁇ m (micrometer) to about 5 ⁇ m (micrometer), and more particularly, in the range of about 1.5 ⁇ m (micrometer) to about 5 ⁇ m (micrometer).
- the copper layer may have a thickness greater than about 5 ⁇ m (micrometer).
- the solder layer may be a lead-free solder layer, for example, including tin and at least one of silver, bismuth, copper, indium, antimony, gold, and/or zinc, and a weight percent of tin in the solder may be greater than about 95 weight percent.
- a weight percent of tin in the solder layer may be in the range of about 97 weight percent and about 99.5 weight percent.
- the solder layer may include a first layer of tin and a second layer of silver, bismuth, copper, indium, antimony, gold, and/or zinc, and the first layer of tin may be between the second layer and the nickel layer.
- the first layer of tin may be greater than about 95 weight percent of the solder layer. More particularly, the first layer of tin may be in the range of about 97 weight percent and about 99.5 weight percent of the solder layer.
- Figures 1-4 are cross-sectional views illustrating steps of forming solder bumps according to embodiments of the present invention.
- Figures 5-8 are cross-sectional views illustrating steps of forming solder bumps according to additional embodiments of the present invention.
- relative terms such as beneath, upper, lower, top, and/or bottom may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as below other elements would then be oriented above the other elements. The exemplary term below, can therefore, encompasses both an orientation of above and below.
- first and second are used herein to describe various regions, layers- and/or sections, these regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer or section from another region, layer or section. Thus, a first region, layer or section discussed below could be termed a second region, layer or section, and similarly, a second region, layer or section could be termed a first region, layer or section without departing from the teachings of the present invention. Like numbers refer to like elements throughout.
- a potential difficulty faced by binary lead free structures is the ability to control the process in a manufacturing environment while allowing for a process window large enough for assembly.
- tin may plate significantly more easily than silver due to differences in electrochemical potentials, and a desired concentration of tin in the resulting binary solder may be significantly greater than that of silver.
- a concentration of silver in the plating solution may be much greater than that of tin in the plating solution to provide the desired concentrations in the plated solder. Because the concentration of tin in the plating solution is relatively low but the concentration of tin in the resulting plated solder is relatively high, the tin may be depleted from the solder relatively quickly, and a process control may be difficult to maintain.
- an integrated circuit substrate 101 may include a semiconductor substrate having electronic circuits (such as one or more resistors, transistors, diodes, capacitors, inductors, etc.) therein, and a conductive input/output pad 103 (such as an aluminum and/or copper pad) on the substrate 101 may provide electrical connection with one or more circuits of the substrate 101.
- an insulating passivation layer 105 may be provided on the substrate 101 and input/output pad 103, and a via hole in the passivation layer 105 may expose at least portions of the input/output pad 103.
- the term substrate may also be defined to include the input/output pad and the passivation layer.
- the term substrate may also include interconnection wiring therein.
- an under bump seed metallurgy layer 107 may be deposited on the passivation layer 105 and on exposed portions of the input/output pad 103, and the under bump seed metallurgy layer 107 may include an adhesion layer 107a, such as a layer including titanium (Ti), titanium-tungsten (TiW), titanium nitride (TiN), and/or chromium (Cr), and a conduction layer 107b, such as a layer including copper (Cu), silver (Ag), and/or gold (Au).
- a plating stencil 108 of an organic and/or an inorganic material can then be formed on the under bump seed metallurgy layer 107.
- the plating stencil 108 may be formed by spinning or laminating a photosensitive material on the under bump seed metallurgy layer 107, baking the photosensitive material, selectively exposing the photosensitive material to light, and developing the photosensitive material to form a via hole exposing at least portions of the input/output pad 103.
- An under bump barrier metallurgy layer 109 may then be plated on portions of the under bump seed metallurgy layer 107 exposed through the plating stencil 108, and the under bump barrier metallurgy layer 109 may include nickel (Ni) and/or copper (Cu).
- the under bump barrier metallurgy layer 109 may be a layer of nickel having a thickness in the range of about 1 ⁇ m (micrometers) to about 5 ⁇ m (micrometers), and more particularly, in the range of about 1.5 ⁇ m (micrometers) to about 5 ⁇ m (micrometers). Seed layers and m ' ckel barrier layers are discussed, for example, in U.S. Patent Publication No.
- the under bump barrier metallurgy layer 109 may be a layer of copper having a thickness greater than about 5 ⁇ m (micrometers).
- the under bump barrier metallurgy layer 109 may include a copper layer (for example, having a thickness greater than about 5 ⁇ m) and a nickel layer (for example, having a thickness in the range of about 1 ⁇ m to about 5 ⁇ m) such that the copper layer is between the nickel layer and the under bump seed metallurgy layer 107.
- under bump barrier metallurgy layer 109 may include a nickel layer plated directly on the under bump seed metallurgy layer 107 without an intervening layer of plated copper.
- a lead free solder bump 111 may be plated on the under bump barrier metallurgy layer 109, and the lead free solder bump 111 may be a binary lead free alloy solder bump such as a tin-silver (SnAg) alloy solder bump, a tin-silver-copper alloy solder bump, and/or a tin-copper alloy solder bump.
- a binary lead free alloy solder bump such as a tin-silver (SnAg) alloy solder bump, a tin-silver-copper alloy solder bump, and/or a tin-copper alloy solder bump.
- the lead free solder bump 111 may be plated as separate layers of tin and silver (or separate layers of tin, silver, and copper; separate layers of tin and copper; etc.), and a subsequent reflow (in some embodiments after removing the plating stencil) can be used to form the alloy thereof.
- the tin and silver may be plated together.
- the tin and silver may be provided such that a concentration of silver in the resulting solder alloy is sufficiently low to suppress formation of SnAg platelets, precipitates, and/or needles that may otherwise occur as a result of temperature excursions.
- a concentration of tin in the resulting solder alloy may be greater than about 95 weight percent.
- a concentration of silver in the resulting solder alloy may be in the range of about 1 weight percent to about 3 weight percent, and/or a concentration of tin in the resulting solder alloy may be in the range of about 97 weight percent to about 99 weight percent.
- the lead free solder bump 111 may include tin and at least one of bismuth, copper, indium, antimony, gold, zinc, and/or silver.
- the lead-free solder bump 111 may include a tin-silver-copper solder.
- the lead free solder bump may include a tin-copper solder having a concentration of tin of about 99.5 weight percent.
- a first layer of tin can be plated followed by a second layer of silver, or a first layer of silver can be plated followed by a second layer of tin, and thicknesses of the layers of tin and silver can be determined to provide an average concentration of silver in the resulting SnAg solder alloy (after reflow) in the range of about 1 weight percent to about 3 weight percent, and/or to provide an average concentration of tin in the range of about 97 weight percent to about 99 weight percent.
- the thicker layer of tin may be plated before plating the thinner layer of silver, for example, because the thicker layer of tin may be easier to plate on the under bump barrier metallurgy layer 109 within the hole defined by the plating stencil 108. Stated in other words, the thinner layer of silver may be plated with better uniformity and/or control after plating the thicker tin layer.
- the layers of tin and silver may be heated to a temperature that is less than a melting temperature of at least one of the metals to provide an alloy of the two metals (e.g., tin and silver).
- the layers of the two metals may be heated to a temperature that is less than a melting temperature of either of the two metals (e.g., less than about 232 degrees C for tin and less than about 962 degrees C for silver), but that is greater than a melting temperature of the alloy of the two metals (e.g., greater than about 220 degrees C for tin-silver).
- the layers of the two metals may be heated to a temperature that is greater than the melting temperature of one of the metals (e.g., greater than about 232 degrees C for tin) but less than a melting temperature of the other metal (e.g., less than about 962 degrees C for silver).
- tin and silver can be plated together (simultaneously) to provide a plated alloy having an average concentration of silver in the range of about 1 weight percent to about 3 weight percent, and/or to provide an average concentration of tin in the range of about 97 weight percent to about 99 weight percent.
- a composition of the plated alloy may be controlled by adjusting an electroplating current density while plating the tin and silver using a plating solution including both tin and silver.
- a first relatively tin rich layer may be plated, and then a second relatively silver rich layer may be plated using a same plating bath including both tin and silver. More particularly, the first relatively tin rich layer may be plated using the plating bath and using a first plating voltage and/or plating current, and the second relatively silver rich layer may be plated using the same plating bath and a second plating voltage and/or plating current (different than the first plating voltage and/or plating current) so that a concentration of tin in the first relatively tin rich layer is greater than a concentration of tin in the second relatively silver rich layer and so that a concentration of silver in the first relatively tin rich layer is less than a concentration of silver in the second relatively silver rich layer.
- the first plating voltage and the first plating current may be less than the second plating voltage and the second plating current.
- the plating bath may be relatively depleted of tin in the vicinity of plating so that a plating rate of tin is reduced while plating the second relatively silver rich layer.
- silver rich means that the concentration of silver is greater in the second layer than in the first layer, but does not necessarily mean that the concentration of silver in the second layer is greater than the concentration of tin in the second layer.
- the layers may be heated to provide at least partial mixing of the layers. More particularly, the layers may be heated to a temperature that is less than a melting temperature of at least one of silver and/or tin.
- portions of the under bump metallurgy seed layer 107 may be free of one or more layers making up the under bump barrier metallurgy layer 109.
- portions of the under bump metallurgy seed layer 107 may be free of plated copper and nickel layers making up the under bump barrier metallurgy layer 109.
- portions of the under bump metallurgy seed layer 107 may be free of one or more layers making up the solder bump 111.
- portions of the under bump metallurgy seed layer 107 may be free of plated tin and silver layers making up the solder bump 111.
- the plating stencil 108 may be removed thereby exposing portions of the under bump seed metallurgy layer 107 surrounding the plated layers (i.e. solder bump 111 and/or under bump barrier metallurgy layer 109).
- exposed portions of the under bump seed metallurgy layer 107 may be etched using the under bump barrier metallurgy layer 109 and/or the solder bump 111 as an etch mask. More particularly, a wet etchant may be selected that selectively etches the under bump seed metallurgy layer 107 with respect to the under bump barrier metallurgy layer 109.
- the under bump seed metallurgy layer 107 may be undercut with respect to the under bump barrier metallurgy layer 109, as shown in Figure 3. While not shown in Figure 3, the etchant used to etch the under bump seed metallurgy layer 107 may etch the solder bump 111 (or portions thereof) selectively with respect to the under bump barrier metallurgy layer 109 so that the solder bump 111 of Figure 3 (or portions thereof) may be set back relative to the under bump barrier metallurgy layer 109. Stated in other words, the under bump barrier metallurgy layer 109 of Figure 3 may include a lip portion extending laterally beyond the under bump seed metallurgy layer 107 and the solder bump 111 (or portions thereof). In an alternative, the etchant used to remove exposed portions of the under bump seed metallurgy layer 107 may be selective with respect to the solder bump or portions thereof.
- solder bump 111 After removing exposed portions of the under bump seed metallurgy layer 107 to provide the structure illustrated in Figure 3, the solder bump 111 can be subjected to a reflow operation to provide the structure illustrated in Figure 4. If the solder bump 111 is plated as separate layers of different metals, the reflow operation may serve to at least partially mix the separate layers into a solder alloy.
- a reflow operation may serve to at least partially mix the tin and silver into a tin-silver solder alloy having an average concentration of silver in the range of about 1 weight percent to about 3 weight percent, and/or having an average concentration of tin in the range of about 97 weight percent to about 99 weight percent.
- the reflow operation may be performed by heating the solder bump 111 to at least a liquidus temperature of a metal of the solder bump having the highest liquidus temperature.
- the solder bump may be heated to a temperature not exceeding the liquidus temperature of the metal having the highest liquidus temperature.
- a reflow operation may be omitted, solid state diffusion at a temperature below the melting temperature of either metal may be used to at least partially mix metals of different layers, and/or the metals may be heated to a temperature greater than a melting temperature of the alloy and less than a melting temperature of either of the metals.
- a reflow operation may be performed to provide the rounded shape of Figure 4, and/or to more evenly distribute metals of the solder alloy.
- a reflow operation may serve to more evenly distribute the tin and silver in the tin- silver solder alloy so that an average concentration of silver is in the range of about 1 weight percent to about 3 weight percent, and/or an average concentration of tin is in the range of about 97 weight percent to about 99 weight percent.
- the reflow operation may be performed by heating the solder bump 111 to at least a liquidus temperature of the solder alloy.
- the solder bump may be heated to a temperature not exceeding the liquidus temperature of the solder alloy.
- a reflow operation may be omitted, solid state diffusion at a temperature below the melting temperature of either metal may be used to at least partially mix metals of the solder bump, and/or the metals may be heated to a temperature greater than a melting temperature of the alloy and less than a melting temperature of either of the metals.
- a solder reflow operation may be performed before removing exposed portions of the under bump seed metallurgy layer 107 and/or before removing the plating stencil 108. If the solder reflow operation is performed before removing exposed portions of the under bump seed metallurgy layer 107, an additional solder non-wettable layer (such as a layer of chromium) may be provided on portions of the under bump seed metallurgy layer 107 surrounding the plated layers (i.e. under bump barrier metallurgy layer 109 and solder bump 111). In addition or in an alternative, an oxide layer may be maintained on the solder to prevent spreading across the under bump seed metallurgy layer during reflow.
- an additional solder non-wettable layer such as a layer of chromium
- an integrated circuit substrate 201 may include a semiconductor substrate having electronic circuits (such as one or more resistors, transistors, diodes, capacitors, inductors, etc.) therein, and a conductive input/output pad 203 (such as an aluminum and/or copper pad) on the substrate 201 may provide electrical connection with one or more circuits of the substrate 201.
- electronic circuits such as one or more resistors, transistors, diodes, capacitors, inductors, etc.
- a conductive input/output pad 203 such as an aluminum and/or copper pad
- an insulating passivation layer 205 may be provided on the substrate 201 and input/output pad 203, and a via hole in the passivation layer 205 may expose at least portions of the input/output pad 203.
- the term substrate may also be defined to include the input/output pad and the passivation layer.
- the term substrate may also include interconnection wiring therein.
- an under bump seed metallurgy layer 207 may be deposited on the passivation layer 205 and on exposed portions of the input/output pad 203, and the under bump seed metallurgy layer 207 may include an adhesion layer 207a, such as a layer including titanium (Ti), titanium-tungsten (TiW), titanium nitride (TiN), and/or chromium (Cr), and a conduction layer 207b, such as a layer including copper (Cu), silver (Ag), and/or gold (Au).
- a plating stencil 208 of an organic and/or an inorganic material can then be formed on the under bump seed metallurgy layer 207.
- the plating stencil 208 may be formed by spinning or laminating a photosensitive material on the under bump seed metallurgy layer 207, baking the photosensitive material, selectively exposing the photosensitive material to light, and developing the photosensitive material to form the via hole exposing at least portions of the input/output pad 203.
- the plating stencil may expose an elongate portion of the under bump seed metallurgy layer 207 extending away from the input/output pad 203 having a relatively narrow width and an enlarged width portion of the under bump seed metallurgy layer 207 laterally spaced from the input/output pad 203.
- a relatively wide solder structure may result to provide a relatively thick solder bump laterally spaced apart from the input/output pad 207, and a relatively narrow solder structure may result to provide a relatively thin solder redistribution line between the solder bump and the input/output pad 207. Redistribution routing conductors are discussed, for example, in U.S.
- Patent No. 6,392,163 entitled Controlled-Shaped Solder Reservoirs For Increasing The Volume Of Solder Bumps
- U.S. Patent No. 6,389,691 entitled Methods For Forming Integrated Redistribution Routing Conductors And Solder Bumps
- U.S. Patent No. 6,388,203 entitled Controlled-Shaped Solder Reservoirs For Increasing The Volume Of Solder Bumps, And Structures Formed Thereby
- U.S. Patent No. 6,329,608 entitled Key-Shaped Solder Bumps And Under Bump Metallurgy.
- the disclosures of these patents are hereby incorporated herein in their entirety by reference.
- An under bump barrier metallurgy layer 209 may then be plated on portions of the under bump seed metallurgy layer 207 exposed through the plating stencil 208, and the under bump barrier metallurgy layer 209 may include nickel (Ni) and/or copper (Cu).
- the under bump barrier metallurgy layer 209 may be a layer of nickel having a thickness in the range of about 1 ⁇ m (micrometers) to 5 ⁇ m (micrometers), and more particularly, in the range of about 1.5 ⁇ m (micrometers) to about 5 ⁇ m (micrometers).
- the under bump barrier metallurgy layer 209 may be a layer of copper having a thickness greater than about 5 ⁇ m (micrometers).
- the under bump barrier metallurgy layer 209 may include a copper layer (for example, having a thickness greater than about 5 ⁇ m) and a nickel layer (for example, having a thickness in the range of about 1 ⁇ m to about 5 ⁇ m) such that the copper layer is between the nickel layer and the under bump seed metallurgy layer 207. Because the under bump barrier metallurgy layer 209 is plated using the plating stencil 208, the under bump barrier metallurgy layer 209 may include an enlarged width portion laterally spaced apart from the input/output pad 203 and a elongate portion between the enlarged width portion and the input/output pad 203. In some embodiments of the present invention, the under bump barrier metallurgy layer 209 may include a nickel layer plated directly on the under bump seed metallurgy layer 207 without an intervening layer of plated copper.
- a lead free solder structure 211 may be plated on the under bump barrier metallurgy layer 209, and the lead free solder structure 211 may be a binary lead free alloy solder structure such as a tin-silver (SnAg) alloy solder structure, a tin-silver- copper alloy solder structure, and/or a tin-copper alloy solder structure.
- a binary lead free alloy solder structure such as a tin-silver (SnAg) alloy solder structure, a tin-silver- copper alloy solder structure, and/or a tin-copper alloy solder structure.
- the lead free solder structure 211 may be plated as separate layers of tin and silver (or separate layers of tin, silver, and copper; separate layers of tin and copper; etc.), and a subsequent reflow (and in some embodiments after removing the plating stencil) can be used to form the alloy thereof.
- the tin and silver may be plated together.
- the tin and silver may be provided such that a concentration of silver in the resulting solder alloy is sufficiently low to suppress formation of SnAg platelets, precipitates, and/or needles that may otherwise occur as a result of temperature excursions.
- a concentration of tin in the resulting solder alloy may be greater than about 95 weight percent.
- a concentration of silver in the resulting solder alloy may be in the range of about 1 weight percent to about 3 weight percent, and/or a concentration of tin in the resulting solder alloy may be in the range of about 97 weight percent to about 99 weight percent.
- the lead free solder structure 211 may include tin and at least one of bismuth, copper, indium, antimony, gold, zinc, and/or silver.
- the lead-free solder structure 211 may include a tin- silver-copper solder.
- the lead-free solder structure may include a tin-copper solder having a concentration of tin of about 99.5 weight percent.
- the solder structure 211 may include an enlarged width portion 211a laterally spaced apart from the input/output pad 203 and a elongate portion 211b between the enlarged width portion and the input/output pad 203. As shown, a plated thickness of the solder structure 211 may be relatively uniform. Differences in widths of the solder structure and underlying under bump barrier metallurgy layer 209 may provide differences in internal solder pressures due to surface tension during a subsequent reflow operation so that solder flows from elongate portion 211b to enlarged width portion 211a thereby increasing a size of a resulting solder bump.
- a first layer of tin can be plated followed by a second layer of silver, or a first layer of silver can be plated followed by a second layer of tin, and thicknesses of the layers of tin and silver can be determined to provide an average concentration of silver in the resulting SnAg solder alloy (after reflow) in the range of about 1 weight percent to about 3 weight percent, and/or to provide an average concentration of tin in the range of about 97 weight percent to about 99 weight percent.
- the thicker layer of tin may be plated before plating the thinner layer of silver, for example, because the thicker layer of tin may be easier to plate on the under bump barrier metallurgy layer 209 within the hole defined by the plating stencil 208. Stated in other words, the thinner layer of silver may be plated with better uniformity and/or control after plating the thicker tin layer.
- the layers of tin and silver may be heated to a temperature that is less than a melting temperature of at least one of the metals to provide an alloy of the two metals (e.g., tin and silver).
- the layers of the two metals may be heated to a temperature that is less than a melting temperature of either of the two metals (e.g., less than about 232 degrees C for tin and less than about 962 degrees C for silver), but that is greater than a melting temperature of the alloy of the two metals (e.g., greater than about 220 degrees C for tin-silver).
- the layers of the two metals may be heated to a temperature that is greater than the melting temperature of one of the metals (e.g., greater than about 232 degrees C for tin) but less than a melting temperature of the other metal (e.g. , less than about 962 degrees C for silver).
- tin and silver can be plated together (simultaneously) to provide a plated alloy having an average concentration of silver in the range of about 1 weight percent to about 3 weight percent, and/or having an average concentration of tin in the range of about 97 weight percent to about 99 weight percent.
- a composition of the plated alloy may be controlled by adjusting an electroplating current density while plating the tin and silver using a plating solution including both tin and silver.
- a first relatively tin rich layer may be plated, and then a second relatively silver rich layer may be plated using a same plating bath including both tin and silver. More particularly, the first relatively tin rich layer may be plated using the plating bath and using a first plating voltage and/or plating current, and the second relatively silver rich layer may be plated using the same plating bath and a second plating voltage and/or plating current (different than the first plating voltage and/or plating current) so that a concentration of tin in the first relatively tin rich layer is greater than a concentration of tin in the second relatively silver rich layer and so that a concentration of silver in the first relatively tin rich layer is less than a concentration of silver in the second relatively silver rich layer.
- the first plating voltage and the first plating current may be less than the second plating voltage and the second plating current.
- the plating bath may be relatively depleted of tin in the vicinity of plating so that a plating rate of tin is reduced while plating the second relatively silver rich layer.
- silver rich means that the concentration of silver is greater in the second layer than in the first layer, but does not necessarily mean that the concentration of silver in the second layer is greater than the concentration of tin in the second layer.
- the layers may be heated to provide at least partial mixing of the layers. More particularly, the layers may be heated to a temperature that is less than a melting temperature of at least one of silver and/or tin.
- portions of the under bump metallurgy seed layer 207 may be free of one or more layers making up the under bump barrier metallurgy layer 209.
- portions of the under bump metallurgy seed layer 207 may be free of plated copper and nickel layers making up the under bump barrier metallurgy layer 209.
- portions of the under bump metallurgy seed layer 207 may be free of one or more layers making up the solder structure 211.
- portions of the under bump metallurgy seed layer 207 may be free of plated tin and silver layers making up the solder structure 211.
- the plating stencil 208 may be removed thereby exposing portions of the under bump seed metallurgy layer 207 surrounding the plated layers (i.e. solder structure 211 and/or under bump barrier metallurgy layer 209).
- exposed portions of the under bump seed metallurgy layer 207 may be etched using the under bump barrier metallurgy layer 209 and/or the solder structure 211 as an etch mask. More particularly, a wet etchant may be selected that selectively etches the under bump seed metallurgy layer 207 with respect to the under bump barrier metallurgy layer 209.
- the under bump seed metallurgy layer 207 may be undercut with respect to the under bump barrier metallurgy layer 209, as shown in Figure 7. While not shown in Figure 7, the etchant used to etch the under bump seed metallurgy layer 207 may etch the solder structure 211 (or portions thereof) selectively with respect to the under bump barrier metallurgy layer 209 so that the solder structure 211 of Figure 7 (or portions thereof) may be set back relative to the under bump barrier metallurgy layer 209. Stated in other words, the under bump barrier metallurgy layer 209 of Figure 7 may include a lip portion extending laterally beyond the under bump seed metallurgy layer 207 and the solder structure 211 (or portions thereof). In an alternative, the etchant used to remove exposed portions of the under bump seed metallurgy layer 207 may be selective with respect to the solder structure or portions thereof.
- the solder structure 211 can be subjected to a reflow operation to provide the structure illustrated in Figure 8.
- differences in internal pressures of the solder due to surface tension may result in a flow of solder from the elongate portion 211b of the solder structure 211 to the enlarged width portion 211a of the solder structure 211 so that a thickness and a volume of the resulting solder bump can be increased.
- a thickness of the elongate portion 211b of the solder structure 211 can be reduced over a conductive redistribution structure.
- the reflow operation may serve to at least partially mix the separate layers into a solder alloy.
- a reflow operation may serve to at least partially mix the tin and silver into a tin-silver solder alloy having an average concentration of silver in the range of about 1 weight percent to about 3 weight percent, and/or having an average concentration of tin in the range of about 97 weight percent to about 99 weight percent.
- the reflow operation may be performed by heating the solder structure 211 to at least a liquidus temperature of a metal of the solder bump having the highest liquidus temperature.
- the solder bump may be heated to a temperature not exceeding the liquidus temperature of the metal having the highest liquidus temperature.
- a reflow operation may be omitted, solid state diffusion at a temperature below the melting temperature of either metal may be used to at least partially mix metals of different layers, and/or the metals may be heated to a temperature greater than a melting temperature of the alloy and less than a melting temperature of either of the metals.
- a reflow operation may be performed to provide the relatively thick raised solder bump 211a and the relatively thin redistribution solder layer 211b of Figure 8, and/or to more evenly distribute metals of the solder alloy.
- a reflow operation may serve to more evenly distribute the tin and silver in the tin-silver solder alloy so that an average concentration of silver is in the range of about 1 weight percent to about 3 weight percent, and/or an average concentration of tin is in the range of about 97 weight percent to about 99 weight percent.
- the reflow operation may be performed by heating the solder structure 211 to at least a liquidus temperature of the solder alloy.
- the solder bump may be heated to a temperature not exceeding the liquidus temperature of the solder alloy.
- a reflow operation may be omitted, solid state diffusion at a temperature below the melting temperature of either metal may be used to at least partially mix metals of the solder bump, and/or the metals may be heated to a temperature greater than a melting temperature of the alloy and less than a melting temperature of either of the metals.
- a solder reflow operation may be performed before removing exposed portions of the under bump seed metallurgy layer 207. If the solder reflow operation is performed before removing exposed portions of the under bump seed metallurgy layer 207, an additional solder non-wettable layer (such as a layer of chromium) may be provided on portions of the under bump seed metallurgy layer 207 surrounding the plated layers (i.e. under bump barrier metallurgy layer 209 and solder structure 211). In addition or in an alternative, an oxide layer may be maintained on the solder to prevent spreading across the under bump seed metallurgy layer during reflow.
- an additional solder non-wettable layer such as a layer of chromium
- binary solders such as tin-silver solder
- ternary solders may be used according to some embodiments of the present invention.
- a ternary solder such as a tin-silver-copper solder
- binary solders such as tin-copper solders may be used with a concentration of tin in the tin-copper solder of about 99.5 weight percent.
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Abstract
Description
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US58401604P | 2004-06-30 | 2004-06-30 | |
PCT/US2005/023041 WO2006004809A1 (en) | 2004-06-30 | 2005-06-29 | Methods of forming lead free solder bumps and related structures |
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EP05766874A Withdrawn EP1766673A1 (en) | 2004-06-30 | 2005-06-29 | Methods of forming lead free solder bumps and related structures |
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EP (1) | EP1766673A1 (en) |
CN (1) | CN101044609A (en) |
TW (1) | TW200616126A (en) |
WO (1) | WO2006004809A1 (en) |
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KR20090075883A (en) * | 2006-10-31 | 2009-07-09 | 어드밴스드 마이크로 디바이시즈, 인코포레이티드 | A metallization layer stack without a terminal aluminum metal layer |
DE102006051491A1 (en) * | 2006-10-31 | 2008-05-15 | Advanced Micro Devices, Inc., Sunnyvale | Metallization layer stack with an aluminum termination metal layer |
DE102007057689A1 (en) * | 2007-11-30 | 2009-06-04 | Advanced Micro Devices, Inc., Sunnyvale | Semiconductor device having a chip area, which is designed for an aluminum-free solder bump connection, and a test structure, which is designed for an aluminum-free wire connection |
CN101740420B (en) * | 2008-11-05 | 2011-11-09 | 中芯国际集成电路制造(上海)有限公司 | Process for manufacturing copper strut |
US8637983B2 (en) * | 2008-12-19 | 2014-01-28 | Ati Technologies Ulc | Face-to-face (F2F) hybrid structure for an integrated circuit |
JP5659821B2 (en) * | 2011-01-26 | 2015-01-28 | 三菱マテリアル株式会社 | Manufacturing method of Sn alloy bump |
US20130099371A1 (en) * | 2011-10-21 | 2013-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package having solder jointed region with controlled ag content |
KR20150109213A (en) * | 2014-03-19 | 2015-10-01 | 에스케이하이닉스 주식회사 | Semiconductor device having through silicon via and the method for manufacturing of the same |
KR102206113B1 (en) * | 2014-03-28 | 2021-01-25 | 에스케이하이닉스 주식회사 | Semiconductor device having through silicon via, semiconductor packages including the same and the method for manufacturing semiconductor device |
JP6217836B1 (en) | 2016-12-07 | 2017-10-25 | 千住金属工業株式会社 | Nuclear material, semiconductor package and bump electrode forming method |
US20220216104A1 (en) * | 2019-02-14 | 2022-07-07 | Lam Research Corporation | Gold through silicon mask plating |
CN110444479B (en) * | 2019-07-22 | 2022-02-01 | 厦门通富微电子有限公司 | Manufacturing method of metal bump and chip |
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US6224690B1 (en) * | 1995-12-22 | 2001-05-01 | International Business Machines Corporation | Flip-Chip interconnections using lead-free solders |
JP2000349111A (en) * | 1999-06-03 | 2000-12-15 | Fujitsu Ltd | Electrode for solder bonding |
US6638847B1 (en) * | 2000-04-19 | 2003-10-28 | Advanced Interconnect Technology Ltd. | Method of forming lead-free bump interconnections |
JP3682227B2 (en) * | 2000-12-27 | 2005-08-10 | 株式会社東芝 | Electrode formation method |
-
2005
- 2005-06-29 EP EP05766874A patent/EP1766673A1/en not_active Withdrawn
- 2005-06-29 CN CNA2005800218814A patent/CN101044609A/en active Pending
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WO2006004809A1 (en) | 2006-01-12 |
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