JP2004158701A - Bump structure for mounting element chip and method for forming the same - Google Patents

Bump structure for mounting element chip and method for forming the same Download PDF

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Publication number
JP2004158701A
JP2004158701A JP2002324047A JP2002324047A JP2004158701A JP 2004158701 A JP2004158701 A JP 2004158701A JP 2002324047 A JP2002324047 A JP 2002324047A JP 2002324047 A JP2002324047 A JP 2002324047A JP 2004158701 A JP2004158701 A JP 2004158701A
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Prior art keywords
bump
element chip
substrate
chip
bumps
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Tomoyuki Kamakura
知之 鎌倉
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
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    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a bump structure capable of securing highly reliable connection at the time of connecting a semiconductor chip to a wiring board by using a peel transfer method. <P>SOLUTION: In this connection structure, a semiconductor chip (11) and a wiring substrate (21) are arranged so as to be faced to each other to connect a bump formed on a semiconductor chip (11) to a bump formed on the wiring board (21). The bump (14) formed on the semiconductor chip (11) is formed as a cross-sectional projecting bump by field-free plating, a bump (25) formed on the wiring board (21) is formed as a cross-sectional recessed bump by field-free plating, and the semiconductor chip (11) is connected to the wiring board (21) so that the projecting part of the bump (14) can be fit into the recessed part of the bump (25). <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は素子チップを実装基板に接続するためのバンプ構造に関し、特に、剥離転写法を用いて素子チップと実装基板を接合する際に好適なバンプ構造の改良技術に関する。
【０００２】
【従来の技術】
特開平６−７７２３３号公報（特許文献１）、特開平５−１４４８７７号公報（特許文献２）、特開２０００−１３３３３０号公報（特許文献３）、特開平５−２１５２３号公報（特許文献４）、特開平５−１０９７３４号公報（特許文献５）に開示されているように、半導体チップのバンプ（突起電極）と配線基板の電極パッドを位置合わせし、フェースダウンボンディングにより接続するフリップチップ接続法が知られている。フリップチップ接続法によれば、ワイヤーボンディングに比べてワイヤーの引き回しが不要となり、コンパクトな実装が可能となる。特許文献５には、さらに、無電界めっき処理により電極パッド上に金属皮膜を還元析出してバンプを形成する技術が開示されている。
【０００３】
一方、特開平１０−１２５９３１号公報（特許文献６）には、転写元基板上に剥離層を介して被転写層を形成し、当該被転写層に含まれる素子チップを接着剤によって転写先基板に接合した後、剥離層に光照射を行って界面剥離又は層内剥離を生じさせ、素子チップを転写先基板に転写する手法が開示されている。この転写法によれば、製造条件の異なる複数種類の素子チップを各々最適な条件で製造した後、上述の転写法で素子チップを転写先基板に転写するだけで所望の電子デバイスを製造できる。
【０００４】
【特許文献１】
特開平６−７７２３３号公報
【特許文献２】
特開平５−１４４８７７号公報
【特許文献３】
特開２０００−１３３３３０号公報
【特許文献４】
特開平５−２１５２３号公報
【特許文献５】
特開平５−１０９７３４号公報
【特許文献６】
特開平１０−１２５９３１号公報
【発明が解決しようとする課題】
ところで、転写元基板上に形成された複数種類の素子チップを剥離し、実装基板の所定の位置に転写して電子デバイスを製造する手法が検討されている。この手法で電子デバイスを製造する場合に、素子チップと実装基板の接続を如何にして確実かつ安定なものとするかが課題となる。例えば、素子チップと実装基板の接続に用いられるバンプを無電界めっきで形成すると、めっき液中に析出する金属皮膜は等方的に成長するため、バンプの先端は球形に近似した断面凸状に湾曲する。このような形状のバンプを用いて剥離転写法によって素子チップと実装基板を接続すると、バンプの先端部分で両者が点接触する構造となるため、接続が不安定になるおそれがある。素子チップと実装基板の接続が不安定になると、製品の歩留まりが低下するため、改良技術の開発が望まれる。
【０００５】
そこで、本発明は剥離転写法を用いて素子チップを実装基板に接続する際に信頼性の高い接続を確保できる素子チップと実装基板のバンプ構造、及びその形成方法、並びに当該バンプ構造を応用した電子デバイスの製造方法を提案することを課題とする。
【０００６】
【課題を解決するための手段】
上記の課題を解決するため、本発明のバンプ構造は、実装基板と接続するために素子チップに形成されるバンプ構造であって、無電界めっきにより断面凹状に形成された金属皮膜から成る。素子チップに形成されるバンプを断面凹状とすることで、実装基板に形成される断面凸状のバンプに対して凹凸嵌合することができ、横ずれなどを防止できる信頼性の高い接続が確保できる。
【０００７】
ここで、「素子チップ」とは、薄膜トランジスタ、ダイオード、抵抗、インダクタ、キャパシタ、発光素子などの機能素子又は当該機能素子を集積化した回路チップをいう。また、「実装基板」とは、素子チップを実装して所望の電子デバイスを構成するための基板をいい、素子チップに接続するべき配線などが予め形成されている。
【０００８】
本発明のバンプ構造は、素子チップと接続するために実装基板に形成されるバンプ構造であって、無電界めっきにより断面凹状に形成された金属皮膜から成る。実装基板に形成されるバンプを断面凹状とすることで、素子チップに形成される断面凸状のバンプに対して凹凸嵌合することができ、横ずれなどを防止できる信頼性の高い接続が確保できる。
【０００９】
本発明のバンプ構造は、実装基板に形成された断面凸状バンプと接続するために素子チップに形成されるバンプ構造であって、無電界めっきにより断面凹状に形成され、かつ前記断面凸状バンプの凸部と嵌合し得る凹部を具備する金属皮膜から成る。バンプを無電界めっきで形成することで、ピンホールの少ない均一な金属皮膜から成るバンプを形成できる。
【００１０】
本発明のバンプ構造は、素子チップに形成された断面凸状バンプと接続するために配線基板に形成されるバンプ構造であって、無電界めっきにより断面凹状に形成され、かつ前記断面凸状バンプの凸部と嵌合し得る凹部を具備する金属皮膜から成る。バンプを無電界めっきで形成することで、ピンホールの少ない均一な金属皮膜から成るバンプを形成できる。
【００１１】
本発明の素子チップと実装基板の接続構造は、素子チップに形成されたバンプと、実装基板に形成されたバンプとが接続するように前記素子チップと前記実装基板を対向配置した接続構造であって、前記素子チップに形成されるバンプは、無電界めっきにより断面凸状バンプに形成される一方、前記実装基板に形成されるバンプは、無電界めっきにより断面凹状バンプに形成され、前記断面凸状バンプの凸部と前記断面凹状バンプの凹部とが嵌合するように前記素子チップと前記実装基板が接続されて成る。素子チップのバンプと実装基板のバンプが凹凸嵌合するように、素子チップと実装基板を対向配置することで、振動などに起因するバンプの横ずれを防止するとともに、接触面積を大きく確保でき、信頼性の高い接続構造が得られる。
【００１２】
本発明の素子チップと実装基板の接続構造は、素子チップに形成されたバンプと、実装基板に形成されたバンプとが接続するように前記素子チップと前記実装基板を対向配置した接続構造であって、前記素子チップに形成されるバンプは、無電界めっきにより断面凹状バンプに形成される一方、前記実装基板に形成されるバンプは、無電界めっきにより断面凸状バンプに形成され、前記断面凸状バンプの凸部と前記断面凹状バンプの凹部とが嵌合するように前記素子チップと前記実装基板が接続されて成る。素子チップのバンプと実装基板のバンプが凹凸嵌合するように、素子チップと実装基板を対向配置することで、振動などに起因するバンプの横ずれを防止するとともに、接触面積を大きく確保でき、信頼性の高い接続構造が得られる。
【００１３】
好ましくは、前記素子チップと前記実装基板は、導電粒子を含む異方性導電ペーストを介して接着される。素子チップと実装基板を接着する手段として、導電粒子を含む異方性導電ペーストを用いることにより、断面凹状バンプの凹部内に着座する導電粒子を介して断面凸状バンプと断面凹状バンプが導通することで、素子チップと実装基板の電気的接続が確保できる。
【００１４】
好ましくは、前記素子チップと前記実装基板は、液状接着剤を介して接着される。素子チップと実装基板を接着する手段として、液状接着剤を用いることにより、素子チップと実装基板を安定的に接続できる。
【００１５】
本発明のバンプ形成方法は、実装基板と接続するために素子チップに形成されるバンプの形成方法であって、断面凹状の下地電極を形成する工程と、無電界めっきにより前記下地電極上に金属皮膜を還元析出し、断面凹状の金属皮膜から成るバンプを形成する工程とを含む。断面凹状の下地電極上に還元析出する金属皮膜はほぼ均一な膜厚で下地電極表面を被覆するため、断面凹状の金属皮膜を形成できる。下地電極の凹部の内径及び深さを適宜調整することで、断面凹状バンプの凹部の寸法を調整できる。
【００１６】
好ましくは、前記下地電極は、前記素子チップの表面に成膜されたパッシベーション膜の開口部の側壁及び底部に形成される。パッシベーション膜に形成される開口部内に下地電極の前駆体となる金属薄膜を成膜し、所定の形状にパターニングすることで、下地電極を容易に形成できる。
【００１７】
好ましくは、前記開口部は、前記素子チップの電極パッドが表面に露出する位置に開口される。かかる工程により、電極パッドと導通する下地電極を形成できる。
【００１８】
本発明の配線基板は、少なくとも２種類以上の素子チップを転写元基板から剥離して、前記素子チップの種類毎に予め定められた位置に形成されたバンプと接続することにより電子デバイスを形成するための配線基板であって、前記素子チップの種類に応じて前記バンプに高低差を設けて成る。転写されるべき素子チップの種類に応じてバンプに高低差を設けることで、転写が予定されていない異種の素子チップがバンプに接続することを防ぐことができる。
【００１９】
好ましくは、前記素子チップとして、電気光学装置の画素回路を構成するスイッチングトランジスタ、駆動トランジスタ及び保持容量を含む素子チップと、電流駆動型発光素子を含む素子チップが含まれる。かかる素子チップを配線基板上に転写することで、電気光学装置のパネル基板を形成できる。ここで、「電気光学装置」とは、電気的作用によって発光する電気光学素子、或いは外部から導入される光の状態を変化させる電気光学素子を備えた装置をいい、自発光するものと外部から導入される光の通過を制御するもの双方を含む。電気光学素子としては、液晶素子、電気泳動素子、エレクトロルミネセンス素子、電子放出素子などが挙げられる。
【００２０】
好ましくは、前記配線基板には、前記スイッチングトランジスタを選択するための走査線と、前記保持容量に保持される電荷量に対応したデータ信号を出力するデータ線と、前記電流駆動型発光素子に供給する電源供給線が形成されている。配線基板に走査線などを予め形成しておくことで、配線基板上に素子チップを剥離転写するだけで容易に電気光学装置のパネル基板を形成できる。
【００２１】
本発明の電気光学装置は本発明の配線基板を備えて構成される。配線基板上への素子チップの剥離転写によりパネル基板を容易に形成できるため、電気光学装置の低コスト化を実現できる。
【００２２】
本発明の電子デバイス製造方法は、剥離層を介して転写元基板に形成された素子チップを剥離して、前記素子チップの種類毎に予め定められた配線基板上の所定位置に転写することにより電子デバイスを製造するための方法であって、第１の転写元基板に形成されている第１の素子チップが前記配線基板上の所定位置に転写されるよう前記第１の転写元基板と前記配線基板とを位置合わせをする工程と、前記第１の転写元基板から前記第１の素子チップを剥離し、前記第１の素子チップが前記配線基板上の所定位置に形成されている第１のバンプと接続するよう転写する工程と、第２の転写元基板に形成されている第２の素子チップが前記配線基板上の所定位置に転写されるよう前記第２の転写元基板と前記配線基板とを位置合わせをする工程と、前記第２の転写元基板から前記第２の素子チップを剥離し、前記第２の素子チップが前記配線基板上の所定位置において前記第１のバンプの高さとは異なる高さに形成されている第２のバンプと接続するよう転写する工程とを含む。第１の素子チップと接続すべき第１のバンプの高さは、第２の素子チップと接続すべき第２のバンプの高さとは異なるため、転写が予定されていない異種の素子チップが配線基板に転写されることを防ぐことができる。
【００２３】
好ましくは、前記第１の素子チップは、電気光学装置の画素回路を構成するスイッチングトランジスタ、駆動トランジスタ及び保持容量を含む素子チップであり、前記第２の素子チップは、電流駆動型発光素子を含む素子チップである。かかる素子チップを配線基板上に転写することで、電気光学装置のパネル基板を形成できる。
【００２４】
好ましくは、前記配線基板には、前記スイッチングトランジスタを選択するための走査線と、前記保持容量に保持される電荷量に対応したデータ信号を出力するデータ線と、前記電流駆動型発光素子に供給する電源供給線が形成されている。配線基板に走査線などを予め形成しておくことで、配線基板上に素子チップを剥離転写するだけで容易に電気光学装置のパネル基板を形成できる。
【００２５】
【発明の実施の形態】
発明の実施の形態１．
図１は配線基板と接続するためのバンプを備えた半導体チップの断面図である。同図に示すように、半導体チップ１１上にはアルミニウム電極などから成る電極パッド１２と、半導体チップ１１を外部からの水分、熱、衝撃などから保護するためのパッシベーション膜１３と、無電界ニッケルめっきで形成された断面凸状（断面凸型）のバンプ１４とが各々形成されている。このような構造は、電極パッド１２が表面に露出するようにパッシベーション膜１３をエッチングして開口部を形成し、無電界めっきにより前記開口部から露出する電極パッド１２上にニッケル皮膜を還元析出させ、断面凸状のバンプ１４を形成することで得られる。無電界めっき液には、主成分（金属塩、還元剤）と補助成分（ｐＨ調整剤、緩衝剤、錯化剤、促進剤、安定剤、改良剤）が含まれ、ニッケル皮膜を還元析出するには、ニッケルイオンと次亜リン酸イオンが主成分となる。無電界めっきで形成されたニッケル皮膜は析出が均一に行われるので、欠陥が少なく、硬度、耐食性、耐摩耗性に優れている。
【００２６】
バンプ１４を電極パッド１２上に所望のサイズに成長させるには、ニッケル濃度、ｐＨ値、めっき温度、攪拌の速さ、めっき時間、めっき速度、安定剤の量などを適宜調整する作業が必要となる。特に、ＢｉやＰｂなどの安定剤を使用すれば、次亜リン酸イオンの酸化反応が抑制され、後続のニッケル析出が行われないため、ニッケル皮膜の析出位置を選択的に制御できる。無電界ニッケルめっきは、外部電源を使用せずに還元剤によってニッケルイオンを還元析出させることで形成されるため、パッシベーション膜１３の開口部から露出する電極パッド１２上に核付けを行い、電極パッド１２をめっき液に浸漬すると、ニッケル皮膜はパッシベーション膜１３の開口部から等方的に成長し、先端が略球形に湾曲した凸部１４ａを備えるバンプ１４が形成される。酸化防止のため、バンプ１４の表面を金（Ａｕ）で表面処理することが望ましい。
【００２７】
図２は半導体チップと接続するためのバンプを備えた配線基板（実装基板）の断面図である。同図に示すように、配線基板２１にはアルミニウム電極などから成る電極パッド２２と、配線基板２１を外部からの水分、熱、衝撃などから保護するためのパッシベーション膜２３と、めっき皮膜析出の下地となる下地電極２４と、無電界ニッケルめっきで形成された断面凹状（断面凹型）のバンプ２５とが各々形成されている。バンプ２５の先端にはバンプ１４の凸部１４ａが嵌合し得る程度の大きさで凹陥状に窪んだ凹部２５ａが形成されている。凹部２５ａの断面形状は凸部１４ａの断面形状とほぼ同程度に形成するのが望ましいが、バンプ１４とバンプ２５の確実かつ安定な接合が得られるならば、必ずしも両者の断面形状が相似である必要はなく、凸部１４ａの主要部分が凹部２５ａ内に収まり、両者のある程度の接触面積が確保できるよう構成されていればよい。半導体チップ１１と配線基板２１を精密な位置合わせの下で各々のバンプ１４，２５を内向させ、凸部１４ａと凹部２５ａが凹凸嵌合するように両者を接合すれば、振動などに起因する横ずれを防止し、半導体チップ１１と配線基板２１の確実かつ安定な接続が得られる。
【００２８】
図４は配線基板２１にバンプ２５を形成するための工程図である。同図（Ａ）に示すように、電極パッド２２が表面に露出するようにパッシベーション膜２３がエッチングされ、略円柱状の開口部２３ａが形成される。次いで、同図（Ｂ）に示すように、めっき析出の下地となるアルミニウム薄膜２４ａがスパッタ法、ＣＶＤ法などの成膜法で成膜される。アルミニウム薄膜２４ａは開口部２３ａの側壁及び電極パッド２２の表面をできるだけ均一な膜厚で被覆するよう成膜するのが望ましい。次いで、同図（Ｃ）に示すように、アルミニウム薄膜２４ａ上にレジストが塗布、露光、及び現像され、開口部２３ａ付近のレジスト２６が残されて、他の部分は除去される。次いで、同図（Ｄ）に示すように、開口部２３ａ付近に残存するレジスト２６をマスクとしてアルミニウム薄膜２４ａをエッチングし、開口部２３ａの周縁を被覆するようにパターニングされた下地電極２４を形成する。かかる工程により、開口部２３ａから外方に延出する鍔部２４ｂと、開口部２３ａの深さ方向に陥没する有底円筒状の凹部２４ｃとを具備する下地電極２４が形成される。
【００２９】
次いで、同図（Ｅ）に示すように、下地電極２４の表面研磨、脱脂、酸浸漬などの表面処理を施した後、無電界めっき処理により、下地電極２４上にニッケル皮膜を還元析出させる。ニッケル皮膜は鍔部２４ｂ及び凹部２４ｃの各点から等方的に成長するため、バンプ２５は断面凹状に形成される。無電界めっきの場合、電気めっきと異なり、電流分布の影響がないため、複雑な形状の下地電極２４（被めっき体）に対して均一な膜厚で直接にめっき処理を施すことが可能となる。また、無電界めっきで析出したニッケル皮膜にはピンホールが少なく、硬度が高いなどの特性がある。酸化防止のため、バンプ２５の表面を金（Ａｕ）で表面処理することが望ましい。
【００３０】
図５は剥離転写法を用いて半導体チップ１１と配線基板２１とを接合する様子を示す断面図である。転写元基板１７には分離層１６、及び中間層１５を介して半導体チップ１１が積層されている。転写元基板１７としては、光透過性の材料で構成するのが望ましく、光透過率１０％以上が好ましく、５０％以上がより好ましい。光透過率が低すぎると、照射光の減衰が大きくなり、分離層１６を剥離するのに大きな光量を必要とする。転写元基板１７はプロセス温度（３５０℃〜１０００℃）よりも高い温歪点を有する材料で構成されているのが好ましく、例えば、石英ガラス、ソーダガラス、コーニング、日本電気ガラスＯＡ−２等の耐熱ガラス、合成樹脂などが好適である。転写元基板１７の厚さは、特に限定されるものではないが、０．１〜５．０ｍｍ程度の膜厚が好ましく、０．５〜５．０ｍｍ程度が好ましい。透過光の光量を均一にするためには、転写元基板１７の厚みは均一であることが望ましい。
【００３１】
分離層１６は、照射光の照射を受けて層内剥離及び／又は界面剥離を生じるよう構成された薄膜であり、照射光を受光することで、分離層１６を構成する物質の原子間又は分子間の結合力が消失又は減少するものである。層内剥離又は界面剥離を生じさせる起因としては、例えば、アブレーションや、気体放出などがある。アブレーションとは、照射光を吸収した固体材料が光化学的又は熱的に励起され、その表面や内部の原子又は分子の結合が切断されて放出することをいい、主に、分離層１６の構成材料の全部又は一部が溶融、蒸散などの相変化を伴う。分離層１６の組成としては、例えば、（１）非晶質シリコン、（２）酸化ケイ素、ケイ酸化合物、酸化チタン、チタン酸化物、酸化ジルコニウム、ジルコン酸化合物、酸化ランタン、ランタン酸化化合物などの各種酸化物セラミックス、誘電体、が挙げられる。半導体酸化ケイ素としては、ＳｉＯ，ＳｉＯ２，Ｓｉ３Ｏ２などが挙げられ、ケイ酸化合物としては、例えば、Ｋ２ＳｉＯ３，Ｌｉ２ＳｉＯ３，ＣａＳｉＯ３，ＺｒＳｉＯ４，Ｎａ２ＳｉＯ３が挙げられる。酸化チタンとしては、ＴｉＯ，Ｔｉ２Ｏ３，ＴｉＯ２が挙げられ、チタン酸化合物としては、例えば、ＢａＴｉＯ４，ＢａＴｉＯ３，Ｂａ２Ｔｉ９Ｏ２０，ＢａＴｉ５Ｏ１１，ＳｒＴｉＯ３，ＰｂＴｉＯ３，ＭｇＴｉＯ３，ＺｒＴｉＯ２，ＳｎＴｉＯ４，Ａｌ２ＴｉＯ５，ＦｅＴｉＯ３が挙げられる。酸化ジルコニウムとしては、ＺｒＯ２が挙げられ、ジルコン酸化合物としては、例えば、ＢａＺｒＯ３，ＺｒＳｉＯ４，ＰｂＺｒＯ３，ＭｇＺｒＯ３，Ｋ２ＺｒＯ３が挙げられる。
【００３２】
分離層１６として、この他にも、例えば、（３）ＰＺＴ、ＰＬＺＴ、ＰＬＬＺＴ、ＰＢＺＴ等のセラミックス、或いは強誘電体、（４）窒化珪素、窒化アルミニウム、窒化チタン、などの窒化物セラミックス、（５）有機系高分子材料、（６）金属などが挙げられる。有機系高分子材料としては、−ＣＨ２−，−ＣＯ−（ケトン），−ＣＯＮＨ−（アミド），−ＮＨ−（イミド），−ＣＯＯ−（エステル），−Ｎ＝Ｎ−（アゾ），−ＣＨ＝Ｎ−（シフ）などの結合を有するもの、特にこれらの結合を多く有するものであれば特に限定されるものではない。また、有機系高分子材料は、構成式中に芳香族炭化水素を有するものであってもよい。このような有機系高分子材料としては、ポリエチレン、ポリプロピレンのようなポリオレフィン、ポリイミド、ポリアミド、ポリエステル、ポリメチルメタクリレート（ＰＭＭＡ）、ポリフェニレンサルファイド（ＰＰＳ）、ポリエーテルスルホン（ＰＥＳ）、エポキシ樹脂などが好適である。また、金属としては、Ａｌ，Ｌｉ，Ｔｉ，Ｍｎ，Ｉｎ，Ｓｎ，Ｙ，Ｌａ，Ｃｅ，Ｎｄ，Ｐｒ，Ｇｄ，Ｓｍ又はこれらのうち少なくとも１種を含む合金が挙げられる。
【００３３】
分離層１６の膜厚としては、分離層１６の組成、層構成、形成方法などの諸条件で異なるが、１ｎｍ〜２０μｍ程度が好ましく、１０ｎｍ〜２０μｍ程度がより好ましく、４１ｎｍ〜１μｍ程度がさらに好ましい。分離層１６の膜厚が薄すぎると、成膜の均一性が損なわれ、剥離にムラが生じることがあり、一方、膜厚が厚すぎると、分離層１６の良好な剥離性を確保するために照射光の光量を多くする必要があるとともに、後工程で分離層１６を除去するのに時間を要する。分離層１６の形成方法は、特に限定されず、膜組成や膜厚などの諸条件に応じて適宜選択される。ＣＶＤ、蒸着、分子線蒸着、スパッタリング、イオンプレーティング、ＰＶＤなどの各種気相成長法、電気めっき、浸漬めっき、無電界めっきなどの各種めっき法、ラングミュア・ブロジェット法、スピンコート、スプレーコート、ロールコート等の塗布法、各種印刷法、転写法、インクジェット法、粉末ジェット法、ゾル・ゲル法などが挙げられる。中間層１５は、半導体チップ１１を配線基板２１に剥離転写する際に、半導体チップ１１を物理的或いは化学的に保護するための保護層として機能するものである。
【００３４】
被転写層としての半導体チップ１１の表面には導電粒子３０を含む接着剤から成る異方性導電ペースト（ＡＣＰ：Ａｎ−ｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）４１が塗布され、半導体チップ１１のバンプ１４と配線基板２１のバンプ２５の凹凸が嵌合し得るよう精密な位置合わせの下で配線基板２１と半導体チップ１１が適度な圧力で圧接することで、両者の電気的接続を確保する。異方性導電ペースト４１は熱可塑性、熱硬化性、紫外線硬化性の樹脂から成る接着層中に導電粒子３０を分散させたもので、半導体チップ１１と配線基板２１の圧接方向に導電性を発揮する。図３は異方性導電ペースト４１に含まれる導電粒子３０の断面図である。同図に示すように、導電粒子３０は、直径数μｍ程度の金属微粒子から成るコア３１と、コア３１の表面を被覆する絶縁皮膜３２とから成る。絶縁皮膜３２として、例えば、二酸化シリコン膜などの絶縁性薄膜が用いられる。半導体チップ１１と配線基板２１を内向させ、異方性導電ペースト４１を介して両者を適度な圧力で押圧すると、バンプ１４，２５の凹凸部分に位置する導電粒子３０の絶縁皮膜３２が圧壊し、表面に導電性のコア３１が露出する。すると、コア３１の露出部分において、バンプ１４，２５が導通するため、半導体チップ１１と配線基板２１の電気的接続が確保される。
【００３５】
半導体チップ１１と配線基板２１を接合したならば、転写元基板１７の裏面から照射光を照射する。この照射光は転写元基板１７を透過した後、分離層１６に吸収され、分離層１６の層内剥離又は界面剥離を誘起する。すると、分離層１６の分子間結合が弱まり、半導体チップ１１が転写元基板１７から剥離する。照射光としては、分離層１６の層内剥離又は界面剥離を生じさせるものであれば、特に限定されるものではないが、例えば、Ｘ線、紫外線、可視光、赤外線（熱線）、レーザ光、ミリ波、マイクロ波、電子線、放射線（α線、β線、γ線）などが挙げられるが、アブレーションを生じさせ易いという点ではレーザ光が好適である。レーザ光としては、気体レーザ、固体レーザなどが挙げられるが、特に、エキシマレーザ、Ｎｄ−ＹＡＧレーザ、Ａｒレーザ、ＣＯ２レーザ、Ｈｅ−Ｎｅレーザなどが好適である。エキシマレーザは、短波長で高エネルギーを出力するため、極めて短時間で分離層１６に層内剥離を生じさせることができる。分離層１６内にアブレーションを誘起させるために、波長依存性がある場合は、照射されるレーザ光の波長は１００〜３５０ｎｍ程度が望ましい。また、分離層１６に、ガス放出、気化、昇華などの相変化を誘起して層内剥離若しくは界面剥離を生じさせるには、レーザ光の波長は３５０〜１２００ｎｍ程度が望ましい。
【００３６】
図６は半導体チップ１１を配線基板２１に剥離転写した後の断面図である。半導体チップ１１の裏面に形成されていた中間層１５は剥離層１６とともに除去されている。半導体チップ１１と配線基板２１の間には導電粒子３０が分散された異方性導電ペースト４１が介在しており、半導体チップ１４を配線基板２１に剥離転写した際に、バンプ１４，２５の押圧により導電粒子３０の絶縁皮膜３２が剥落、若しくは破砕することによって、表面に露出したコア３１を介してバンプ１４，２５を導通させることができる。このように、本実施形態によれば、断面凹状の下地電極２４の表面にニッケル皮膜を還元析出させ、内部に陥没する凹部２５ａを有するバンプ２５を形成することによって、凹部２５ａ内に所定の分散密度で導電粒子３０を着座させることができる。半導体チップ１１のバンプ１４はその先端の凸部１４ａが凹部２５ａと直接接触することで、或いは、導電粒子３０を介して間接的にバンプ２５と導通することができる。つまり、バンプ２５を断面凹状に形成することで、断面凸状のバンプ１４との接触面積をできるだけ多く確保することができ、半導体チップ１１と配線基板２１との間のより安定した電気的接続を確保できる。
【００３７】
バンプ１４とバンプ２５を確実に接合するには、バンプ形状をμｍオーダーで精密に加工制御する必要があるが、バンプ２５は無電界ニッケルめっきにより均一な膜厚で形成でき、しかも、ニッケル皮膜の析出速度はニッケル濃度、ｐＨ値、めっき温度、攪拌の速さ、めっき時間、安定剤の量などによって比較的容易に制御できるため、下地電極２４の加工精度が重要となる。下地電極２４の鍔部２４ｂ及び凹部２４ｃの寸法はレジスト２６の加工精度、アルミニウム薄膜２４ａに対するエッチング処理の異方性、パッシベーション膜２３への開口部２３ａの加工精度、パッシベーション膜２３の膜厚、及び電極パッド２２の膜厚などに依存するため、これらを所望の精度で加工することで、所望の内径及び深さに加工された凹部２４ｃと、所望の外径に加工された鍔部２４ｂを有する下地電極２４を形成できる。
【００３８】
尚、上述の説明では、半導体チップ１１と配線基板２１を接着するための手段として、導電粒子３０を含む異方性導電ペースト４１を用いたが、本発明はこれに限らず、例えば、図７に示すように、導電粒子３０を含まない液状接着剤（ＮＣＰ：Ｎｏｎ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）４２を用いて半導体チップ１１と配線基板２１を接着するよう構成してもよい。液状接着剤４２を用いる場合には、導電粒子３０が含まれていないため、バンプ１４，２５の良好な接続を得るには、配線基板２１として、フレキシブル基板のようにある程度の柔軟性、可撓性のある材質を用いるのが好ましい。配線基板２１に柔軟性、可撓性があれば、バンプ１４，２５が面接触する割合を高めることができる。
【００３９】
また、上述の説明では、半導体チップ１１に形成されるバンプ１４は断面凸状に形成される場合を例示したが、本発明はこれに限らず、例えば、図８に示すように、半導体チップ１１に形成されるバンプ１９を断面凹状に形成してもよい。このバンプ１９は、パッシベーション膜１３の開口部において電極パッド１２に接続する断面凹状の下地電極１８表面にニッケル皮膜を還元析出させることで形成される。下地電極１８及びバンプ１９の具体的な製造プロセスは上述したプロセス（図４参照）と同様である。半導体チップ１１のバンプ１９と、配線基板２１のバンプ２５が内向するように、精密な位置合わせの下でアライメント調整し、両者の間に導電粒子３０を含む異方性導電ペースト４１を介在させた状態で半導体チップ１１を配線基板２１に剥離転写することで、半導体チップ１１と配線基板２１を電気的に接続することができる。バンプ１９，２５は共に断面凹状に形成されているため、バンプ１９，２５の先端の平坦部分において、両者の接触面積を多く確保することができる。また、バンプ１９，２５の各々の凹部１９ａ，２５ａ内に着座する導電粒子３０の絶縁皮膜３２がバンプ１９，２５の押圧力によって圧壊し、剥落することによって表面に露出した導電性のコア３１を通じてバンプ１９，２５が導通するため、半導体チップ１１と配線基板２１の安定した電気的接続を確保できる。
【００４０】
半導体チップ１１と配線基板２１を接着する手段として、図８では異方性導電ペースト４１を用いる例を示したが、本発明はこれに限らず、例えば、図９に示すように液状接着剤４２を用いることもできる。液状接着剤４２を用いる場合には、導電粒子３０が含まれていないため、バンプ１９，２５を断面凹状に形成することで、両者の接触面積を大きく確保でき、より安定した電気的接続が得られる。特に、液状接着剤４２を用いる場合には、バンプ１９，２５の先端部分をできるだけ平坦なものとすることで、バンプ１９，２５が面接触できるよう工夫するのが望ましい。
【００４１】
発明の実施の形態２．
本発明の第２の実施形態は、配線基板上に素子チップを剥離転写し、所望の電子デバイスを形成する技術に関するものである。本実施例では、配線基板上にＴＦＴチップ、ＥＬチップなどを剥離転写して有機ＥＬディスプレイパネルを形成する場合を例に挙げて説明する。図１１は有機ＥＬディスプレイの画素の回路構成図である。同図において、符号５２は走査線Ｖｓｅｌに接続するスイッチングトランジスタＴｒ１と、データ線Ｉｄａｔから供給される電荷を蓄積する保持容量Ｃと、保持容量Ｃに保持された制御電圧に対応する駆動電流を電源供給線Ｖｄｄから電源供給を受けて有機ＥＬ素子ＯＬＥＤに供給する駆動トランジスタＴｒ２を含むＴＦＴチップである。符号６２は、陰極／電子輸送層／発光層／正孔輸送層／画素電極などのデバイス層を積層した有機ＥＬ素子ＯＬＥＤを含むＥＬチップである。有機ＥＬ素子ＯＬＥＤの積層構造としては、陰極／発光層／画素電極、陰極／電子輸送層／発光層／画素電極、陰極／発光層／正孔輸送層／画素電極などであってもよい。
【００４２】
図１０は配線基板２１上にＴＦＴチップ５２、及びＥＬチップ６２を剥離転写して有機ＥＬディスプレイパネルを形成する手順を示す説明図である。配線基板２１には、画素がＮ行Ｍ列のマトリクス状に形成されるよう、走査線Ｖｓｅｌ、データ線Ｉｄａｔ、電源供給線Ｖｄｄなどが予め所定のパターンで形成されている。つまり、走査線Ｖｓｅｌは画素マトリクスの行方向に平行となるように予め形成され、データ線Ｉｄａｔと電源供給線Ｖｄｄはこれと略直交する向きで交差するよう画素マトリクスの列方向に平行となるよう予め形成されている。ここでは、説明の便宜上、同図には走査線Ｖｓｅｌ、データ線Ｉｄａｔ、電源供給線Ｖｄｄは図示していない。配線基板２１上には、画素が形成されるべき位置に対応して、ＴＦＴチップ５２が転写されるべきＮ個の被転写領域Ｔ１，Ｔ２，…，ＴＮと、ＥＬチップ６２が転写されるべきＮ個の被転写領域Ｅ１，Ｅ２，…，ＥＮが予め設定されている。被転写領域Ｔｎ（ｎ＝１〜Ｎ）には一方向に並ぶＭ個のＴＦＴチップ５２が転写されるだけの面積が確保されており、被転写領域Ｅｎ（ｎ＝１〜Ｎ）には一方向に並ぶＭ個のＥＬチップ６２が転写されるだけの面積が確保されている。第ｎ行目に並ぶ被転写領域Ｔｎ及びＥｎに転写されるＭ個のＴＦＴチップ５２及びＥＬチップ６２によって、第ｎ行目に並ぶ画素群が形成される。
【００４３】
一方、ＴＦＴチップ形成基板５１には、図示しない剥離層及び中間層を介してＴＦＴチップ５２がマトリクス状に形成されている。ＴＦＴチップ形成基板５１は前述した転写元基板１７と同様に、光透過性のある材料で構成されるのが望ましい。ＴＦＴチップ形成基板５１は、少なくともＮ個のチップ形成領域ＳＴ１，ＳＴ２，…，ＳＴＮを含んでおり、各々のチップ形成領域ＳＴ１，ＳＴ２，…，ＳＴＮには、行方向に少なくともＭ個のＴＦＴチップ５２が形成されている。チップ形成領域ＳＴｎ（ｎ＝１〜Ｎ）に形成されているＴＦＴチップ５２のうち行方向に並ぶ少なくともＭ個のＴＦＴチップ５２は被転写領域Ｔｎ（ｎ＝１〜Ｎ）に転写される。ＴＦＴチップ５２を配線基板２１上に転写するには、ＴＦＴチップ形成基板５１のアライメントマークＢ１〜Ｂ３と、配線基板２１のアライメントマークＡ１〜Ａ３を目印に位置合わせを行い、配線基板２１の上にＴＦＴチップ形成基板５１を重ね合わせた状態でＴＦＴチップ形成基板５１の裏面から光照射などを行い、ＴＦＴチップ形成基板５１とＴＦＴチップ５２の間に介在する剥離層の層内剥離又は界面剥離などを通じてＴＦＴチップ５２を配線基板２１に転写する。
【００４４】
ＥＬチップ形成基板６１には、図示しない剥離層及び中間層を介してＥＬチップ６２がマトリクス状に形成されている。ＥＬチップ形成基板６１は前述した転写元基板１７と同様に、光透過性のある材料で構成されるのが望ましい。ＥＬチップ形成基板６１は、少なくともＮ個のチップ形成領域ＳＥ１，ＳＥ２，…，ＳＥＮを含んでおり、各々のチップ形成領域ＳＥ１，ＳＥ２，…，ＳＥＮには、行方向に少なくともＭ個のＥＬチップ６２が形成されている。チップ形成領域ＳＥｎ（ｎ＝１〜Ｎ）に形成されているＥＬチップ６２のうち行方向に並ぶ少なくともＭ個のＥＬチップ６２は被転写領域Ｅｎ（ｎ＝１〜Ｎ）に転写される。ＥＬチップ６２を配線基板２１上に転写するには、ＥＬチップ形成基板６１のアライメントマークＣ１〜Ｃ３と、配線基板２１のアライメントマークＡ１〜Ａ３を目印に位置合わせを行い、配線基板２１の上にＥＬチップ形成基板６１を重ね合わせた状態でＥＬチップ形成基板６１の裏面から光照射などを行い、ＥＬチップ形成基板６１とＥＬチップ６２の間に介在する剥離層の層内剥離又は界面剥離などを通じてＥＬチップ６２を配線基板２１上に転写する。尚、アライメントマークＡ１〜Ａ３、Ｂ１〜Ｂ３、及びＣ１〜Ｃ３は説明の便宜上、各々の基板の角部に設けているが、必ずしもこの位置に設ける必要はない。
【００４５】
図１２は配線基板２１にＴＦＴチップ５２を剥離転写するときの有機ＥＬディスプレイパネルの断面構造図である。ＴＦＴチップ形成基板５１上には、中間層１５及び剥離層１６を介してＴＦＴチップ５２が形成されている。ＴＦＴチップ５２には配線基板２１と接続するための電極パッド５３が形成されている。一方、配線基板２１には、ＴＦＴチップ５２に対して電気的に接続するための電極パッド２７及びバンプ８１と、ＥＬチップ６２に対して電気的に接続するための電極パッド２８及びバンプ８２が形成されている。また、ＴＦＴチップ５２と配線基板２１の間には液状接着剤４２が塗布され、両者を接着している。バンプ８１，８２は共に無電界めっき処理により形成された断面凸状の突起電極である。バンプ８１の高さはバンプ８２の高さよりも高くなるよう無電界めっき条件が工夫されている。つまり、配線基板２１上に転写されるべき素子チップの種類に応じて当該素子チップに接続するバンプの高さを変えている。このように、ＴＦＴチップ５２に接続すべきバンプ８１の高さをＥＬチップ６２に接続すべきバンプ８２の高さよりも高くすることで、ＴＦＴチップ５２をバンプ８１に接合したとき、ＴＦＴチップ５２が不用意にバンプ８２と接合することを防止できる。仮に、バンプ８１，８２の高さを略均一に揃えると、ＴＦＴチップ５２を配線基板２１に転写する際、ＴＦＴチップ５２がバンプ８２と接合してしまうおそれが十分にあるが、バンプ８１，８２の高さに高低差を設けることでこのような事態をできるだけ回避できる。
【００４６】
尚、ＥＬチップ６２には、有機ＥＬ素子ＯＬＥＤに駆動電流を供給する都合上、電極パッド２８及びバンプ８２は電極パッド２７及びバンプ８１よりも開口部大きくなるよう設計されている。また、ＴＦＴチップ５２の電極パッド５３と、配線基板２１の電極パッド８１が接合するよう正確にアライメント調整を行って、ＴＦＴチップ５２と配線基板２１を適度な圧力で圧着し、ＴＦＴ形成基板５１の裏面からレーザ光などの照射光を照射すると、剥離層１６に層内剥離又は界面剥離が生じ、ＴＦＴチップ５２を配線基板２１に転写することができる。レーザ照射は転写されるべきＴＦＴチップ５２を選択した上で、個々のＴＦＴチップ５２毎に、又は選択された一群のＴＦＴチップ５２に対してまとめて一括照射する。
【００４７】
図１３は配線基板２１にＥＬチップ６２を剥離転写するときの有機ＥＬディスプレイパネルの断面構造図である。配線基板２１には既にＴＦＴチップ５２が接続されている。ＥＬチップ形成基板６１上には中間層１５及び剥離層１６を介してＥＬチップ６２が形成されている。また、ＥＬチップ６２には配線基板２１と接続するための電極パッド６３が形成されている。ＥＬチップ６２と配線基板２１の間には導電粒子３０を含む異方性導電ペースト４１が塗布され、導電粒子３０を介して電極パッド６３とバンプ８２が導通するよう構成されている。ＥＬチップ６２の電極パッド６３と、配線基板２１のバンプ８２が接合するよう正確にアライメント調整を行って、ＥＬチップ６２と配線基板２１を適度な圧力で圧着し、ＥＬチップ形成基板６１の裏面からレーザ光などの照射光を照射すると、剥離層１６に層内剥離又は界面剥離が生じ、ＥＬチップ６２を配線基板２１に転写することができる。レーザ照射は転写されるべきＥＬチップ６２を選択した上で、個々のＥＬチップ６２毎に、又は選択された一群のＥＬチップ６２に対してまとめて一括照射する。
【００４８】
図１４はＥＬチップ６２と接続するためのバンプ８２の製造工程を説明するための断面図である。ＥＬチップ６２には、有機ＥＬ素子ＯＬＥＤに駆動電流を供給する都合上、電極パッド２８及びバンプ８２は電極パッド２７及びバンプ８１よりも開口部大きくなるよう設計されているため、普通に無電界めっきを行えば、バンプ８１とバンプ８２は同一の高さになる。そこで、バンプ８２形成の前準備として、バンプ８２が形成されるべき位置、つまり、電極パッド２８の形成位置に合わせて、パッシベーション膜２３に小径の開口部２３ｂを多数形成する。バンプ８２が未だ形成されていない状態では、電極パッド２８は開口部２３ｂを介して表面に露出する。開口部２３ｂ付近に無電界めっき処理の前準備を施した後、めっき液に含まれる安定剤の量を適宜調整し、電極パッド２８をめっき液に浸漬すると、開口部２３ｂから浸液するめっき液の量を適度に加減できる。つまり、安定剤の量を加減することで、開口部２３ｂにおけるニッケル皮膜の還元析出の有無を選択的に制御することができる。ニッケル皮膜の還元析出はめっき液に浸されているあらゆる箇所から等方的に行われるため、めっき液が浸液しにくい小径の開口部２３ｂの内部に位置する電極パッド２８の表面はニッケル皮膜が成長しにくい環境下にある。このような環境下において、さらに、安定剤の量を加減することで、開口部２３ｂにおけるニッケル皮膜の成長を選択的に制限することが可能となる。このようなめっき条件で無電界めっき処理を行うと、バンプ８２の析出成長速度は遅くなり、バンプ８２の高さはＴＦＴチップ５２と接続するためのバンプ８１の高さよりも低くなる。
【００４９】
図１５はＥＬチップ５２と接続するためのバンプ８２他の製造工程を説明するための工程図である。同図（Ａ）に示すように、まず、配線基板２１上のパッシベーション膜２３をエッチング処理し、ＴＦＴチップ５２と接続するための電極パッド２７を表面に露出するための開口部２３ｃと、ＥＬチップ６２と接続するための電極パッド２８を表面に露出するための開口部２３ｄとを形成する。次いで、同図（Ｂ）に示すように、無電界めっき処理により電極パッド２７，２８の表面及び開口部２３ｃ、２３ｄ付近のパッシベーション膜２３上にニッケル皮膜を還元析出させ、バンプ８１，８２の前駆体となるニッケル皮膜８１ａ，８２ａを形成する。次いで、同図（Ｃ）に示すように、ニッケル皮膜８２ａの表面にマスク９０を形成し、無電界ニッケルめっき処理を行う。マスク９０としては、無電界ニッケルめっきの還元析出を阻害するものであれば、特に限定されるものではなく、任意の絶縁膜、金属薄膜などを用いることができるが、後工程において容易に除去できる薄膜であることが望ましい。かかる工程により、ニッケル皮膜８１ａ上へのニッケル皮膜の再析出が行われる一方、ニッケル皮膜８２ａ上へのニッケル皮膜の再析出は阻害され、バンプ８１，８２の高さ調整を行うことが可能となる。次いで、同図（Ｄ）に示すように、バンプ８１の高さが所望の値となるよう、ニッケル皮膜８２ａ上へのニッケル皮膜の再析出が適度な量で行われた時点で、無電界めっき処理を中止し、マスク９０を除去する。これにより、所望の高低差ｈを有するバンプ８１，８２が形成される。
【００５０】
尚、本実施形態においては、ＴＦＴチップ６２、ＥＬチップ５２と接続するためのバンプ８１，８２として、断面凸状の構造を例示して説明したが、本発明はこれに限られるものではなく、バンプ８１，８２の構造として断面凹状の構造を採用してもよい。このように、本実施形態によれば、配線基板に転写される素子チップの種類に応じて、素子チップと接続すべきバンプに高低差を設けたため、素子チップを配線基板に転写する際に、所望の転写領域に素子チップを転写することができ、歩留まりの向上を図ることができる。
【図面の簡単な説明】
【図１】本実施形態の半導体チップの断面図である。
【図２】本実施形態の配線基板の断面図である。
【図３】導電粒子の断面図である。
【図４】断面凹状バンプの製造工程断面図である。
【図５】半導体チップと配線基板の接続工程を示す断面図である。
【図６】半導体チップと配線基板の接続状態を示す断面図である。
【図７】半導体チップと配線基板の接続状態を示す断面図である。
【図８】半導体チップと配線基板の接続状態を示す断面図である。
【図９】半導体チップと配線基板の接続状態を示す断面図である。
【図１０】配線基板上への素子チップを実装する工程の説明図である。
【図１１】有機ＥＬディスプレイの画素回路の構成図である。
【図１２】ＴＦＴチップと配線基板の接続工程を示す断面図である。
【図１３】ＥＬチップと配線基板の接続工程を示す断面図である。
【図１４】断面凸状バンプの形成工程断面である。
【図１５】断面凸状バンプの形成工程断面図である。
【符号の説明】
１１…半導体チップ １２…電極パッド １３…パッシベーション膜 １４…バンプ １５…中間層 １６…分離層 １７…転写元基板 １８…下地電極 １９…バンプ ２１…配線基板 ２２…電極パッド ２３…パッシベーション膜 ２４…下地電極 ２５…バンプ ２６…レジスト ２７…電極パッド ２８…電極パッド ３０…導電粒子 ３１…コア ３２…絶縁皮膜 ４１…異方性導電ペースト ４２…液状接着剤[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a bump structure for connecting an element chip to a mounting substrate, and more particularly to an improved bump structure suitable for bonding the element chip to the mounting substrate using a peeling transfer method.
[0002]
[Prior art]
JP-A-6-77233 (Patent Document 1), JP-A-5-144877 (Patent Document 2), JP-A-2000-133330 (Patent Document 3), and JP-A-5-21523 (Patent Document 4) Japanese Patent Application Laid-Open No. 5-109734 (Patent Document 5) discloses a flip-chip connection in which bumps (protruding electrodes) of a semiconductor chip and electrode pads of a wiring board are aligned and connected by face-down bonding. The law is known. According to the flip-chip connection method, wire routing is not required as compared with wire bonding, and compact mounting is possible. Patent Document 5 further discloses a technique of forming a bump by reducing and depositing a metal film on an electrode pad by electroless plating.
[0003]
On the other hand, Japanese Patent Application Laid-Open No. 10-125931 (Patent Document 6) discloses a method in which a transfer-receiving layer is formed on a transfer-source substrate via a release layer, and an element chip included in the transfer-target layer is bonded with an adhesive to a transfer-receiving substrate. A method is disclosed in which, after bonding to a substrate, light is applied to a separation layer to cause interfacial separation or separation within the layer, and the element chip is transferred to a transfer destination substrate. According to this transfer method, a desired electronic device can be manufactured only by manufacturing a plurality of types of element chips having different manufacturing conditions under optimum conditions and then transferring the element chips to a transfer destination substrate by the above-described transfer method.
[0004]
[Patent Document 1]
JP-A-6-77233
[Patent Document 2]
JP-A-5-144877
[Patent Document 3]
JP-A-2000-133330
[Patent Document 4]
JP-A-5-21523
[Patent Document 5]
JP-A-5-109734
[Patent Document 6]
JP-A-10-125931
[Problems to be solved by the invention]
By the way, a method of peeling a plurality of types of element chips formed on a transfer source substrate and transferring the chip to a predetermined position on a mounting substrate to manufacture an electronic device has been studied. When an electronic device is manufactured by this method, a problem is how to reliably and stably connect an element chip to a mounting substrate. For example, if a bump used to connect an element chip and a mounting board is formed by electroless plating, the metal film deposited in the plating solution grows isotropically, so that the tip of the bump has a convex cross section that approximates a sphere. Bend. When an element chip and a mounting substrate are connected by a peeling transfer method using a bump having such a shape, the two are point-contacted to each other at a tip portion of the bump, so that connection may be unstable. If the connection between the element chip and the mounting board becomes unstable, the yield of the product is reduced, and therefore, development of an improved technique is desired.
[0005]
Therefore, the present invention applies a bump structure between an element chip and a mounting substrate, which can ensure a highly reliable connection when the element chip is connected to the mounting substrate using a peeling transfer method, and a method for forming the bump structure, and the bump structure is applied. It is an object to propose a method for manufacturing an electronic device.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, a bump structure according to the present invention is a bump structure formed on an element chip for connection to a mounting board, and is formed of a metal film formed in a concave cross section by electroless plating. By making the bumps formed on the element chip have a concave cross section, the bumps having a convex cross section formed on the mounting substrate can be fitted into the bumps in a concave and convex manner, and a highly reliable connection that can prevent lateral displacement and the like can be secured. .
[0007]
Here, the "element chip" refers to a functional element such as a thin film transistor, a diode, a resistor, an inductor, a capacitor, a light emitting element, or a circuit chip in which the functional element is integrated. Further, the “mounting substrate” refers to a substrate for mounting a device chip to configure a desired electronic device, and wirings to be connected to the device chip are formed in advance.
[0008]
The bump structure of the present invention is a bump structure formed on a mounting substrate for connecting to an element chip, and is formed of a metal film formed in a concave shape by electroless plating. By making the bumps formed on the mounting substrate have a concave cross section, the bumps having a convex cross section formed on the element chip can be fitted into the bumps, and a reliable connection that can prevent lateral displacement and the like can be secured. .
[0009]
The bump structure according to the present invention is a bump structure formed on an element chip for connection with a bump having a cross-section that is formed on a mounting substrate, the bump having a cross-section that is formed by electroless plating, and the bump having a cross-section that is convex. And a metal film having a concave portion that can be fitted with the convex portion of the metal film. By forming the bumps by electroless plating, bumps made of a uniform metal film with few pinholes can be formed.
[0010]
The bump structure according to the present invention is a bump structure formed on a wiring board for connection with a bump having a cross section formed on an element chip, wherein the bump is formed to have a concave cross section by electroless plating. And a metal film having a concave portion that can be fitted with the convex portion of the metal film. By forming the bumps by electroless plating, bumps made of a uniform metal film with few pinholes can be formed.
[0011]
The connection structure between the element chip and the mounting board according to the present invention is a connection structure in which the element chip and the mounting board are arranged to face each other so that the bump formed on the element chip is connected to the bump formed on the mounting board. The bump formed on the element chip is formed into a bump having a cross-sectional convex shape by electroless plating, while the bump formed on the mounting substrate is formed into a bump having a concave cross-sectional shape by electroless plating. The element chip and the mounting board are connected so that the convex portion of the bump and the concave portion of the bump having a concave cross section are fitted. By arranging the element chip and the mounting board facing each other so that the bumps on the element chip and the bumps on the mounting board are fitted into the bumps, it is possible to prevent lateral displacement of the bumps due to vibration, etc. A highly reliable connection structure can be obtained.
[0012]
The connection structure between the element chip and the mounting board according to the present invention is a connection structure in which the element chip and the mounting board are arranged to face each other so that the bump formed on the element chip is connected to the bump formed on the mounting board. The bump formed on the element chip is formed into a bump having a concave cross section by electroless plating, while the bump formed on the mounting substrate is formed into a bump having a convex cross section by electroless plating. The element chip and the mounting board are connected so that the convex portion of the bump and the concave portion of the bump having a concave cross section are fitted. By arranging the element chip and the mounting board facing each other so that the bumps on the element chip and the bumps on the mounting board are fitted into the bumps, it is possible to prevent lateral displacement of the bumps due to vibration, etc. A highly reliable connection structure can be obtained.
[0013]
Preferably, the element chip and the mounting board are bonded via an anisotropic conductive paste containing conductive particles. By using an anisotropic conductive paste containing conductive particles as a means for bonding the element chip and the mounting substrate, the convex cross-section bumps and the concave cross-section bumps conduct through the conductive particles seated in the concave portions of the cross-sectional concave bumps. Thus, electrical connection between the element chip and the mounting board can be secured.
[0014]
Preferably, the element chip and the mounting substrate are bonded via a liquid adhesive. By using a liquid adhesive as a means for bonding the element chip and the mounting board, the element chip and the mounting board can be stably connected.
[0015]
The bump forming method of the present invention is a method of forming a bump formed on an element chip for connection with a mounting substrate, the method including forming a base electrode having a concave cross section, and forming a metal on the base electrode by electroless plating. Forming a bump composed of a metal film having a concave cross section by reductively depositing the film. Since the metal film that is reduced and deposited on the base electrode having a concave cross section covers the base electrode surface with a substantially uniform film thickness, a metal film having a concave cross section can be formed. By appropriately adjusting the inner diameter and the depth of the concave portion of the base electrode, the size of the concave portion of the cross-sectional concave bump can be adjusted.
[0016]
Preferably, the base electrode is formed on a side wall and a bottom of an opening of a passivation film formed on a surface of the element chip. By forming a metal thin film as a precursor of the base electrode in the opening formed in the passivation film and patterning the thin film into a predetermined shape, the base electrode can be easily formed.
[0017]
Preferably, the opening is opened at a position where an electrode pad of the element chip is exposed on the surface. By such a process, a base electrode that is electrically connected to the electrode pad can be formed.
[0018]
The wiring board of the present invention forms an electronic device by peeling at least two or more types of element chips from the transfer source substrate and connecting to bumps formed at predetermined positions for each type of the element chips. A wiring board for providing the bumps with a height difference according to the type of the element chip. By providing a height difference between the bumps in accordance with the type of the element chip to be transferred, it is possible to prevent a different type of element chip not scheduled to be transferred from being connected to the bump.
[0019]
Preferably, the element chip includes an element chip including a switching transistor, a driving transistor, and a storage capacitor which constitute a pixel circuit of the electro-optical device, and an element chip including a current driven light emitting element. By transferring such an element chip onto a wiring substrate, a panel substrate of an electro-optical device can be formed. Here, the “electro-optical device” refers to an electro-optical device that emits light by an electric action or a device that includes an electro-optical device that changes the state of light introduced from the outside. Includes both that control the passage of the light introduced. Examples of the electro-optical element include a liquid crystal element, an electrophoretic element, an electroluminescent element, and an electron emitting element.
[0020]
Preferably, the wiring board includes a scanning line for selecting the switching transistor, a data line for outputting a data signal corresponding to an amount of charge held in the storage capacitor, and a data line for supplying the current driven light emitting element. Power supply line is formed. By forming the scanning lines and the like on the wiring substrate in advance, the panel substrate of the electro-optical device can be easily formed only by peeling and transferring the element chip on the wiring substrate.
[0021]
An electro-optical device according to the present invention includes the wiring substrate according to the present invention. Since the panel substrate can be easily formed by peeling and transferring the element chip onto the wiring substrate, the cost of the electro-optical device can be reduced.
[0022]
The electronic device manufacturing method according to the present invention is configured such that an element chip formed on a transfer source substrate is separated via a separation layer, and is transferred to a predetermined position on a wiring substrate predetermined for each type of the element chip. A method for manufacturing an electronic device, comprising: a step of transferring a first element chip formed on a first transfer source substrate to a predetermined position on the wiring board; A step of aligning with a wiring substrate, and a step of peeling the first element chip from the first transfer source substrate, wherein the first element chip is formed at a predetermined position on the wiring substrate. Transferring the second element chip formed on the second transfer source substrate to a predetermined position on the wiring board, and transferring the second element chip formed on the second transfer source substrate to the predetermined position on the wiring board. Work to align the substrate And peeling the second element chip from the second transfer source substrate, wherein the second element chip is formed at a predetermined position on the wiring substrate at a height different from the height of the first bump. Transferring to be connected to the second bump. Since the height of the first bump to be connected to the first element chip is different from the height of the second bump to be connected to the second element chip, a different type of element chip to which transfer is not scheduled is performed. It can be prevented from being transferred to the substrate.
[0023]
Preferably, the first element chip is an element chip including a switching transistor, a driving transistor, and a storage capacitor that constitute a pixel circuit of the electro-optical device, and the second element chip includes a current-driven light-emitting element. An element chip. By transferring such an element chip onto a wiring substrate, a panel substrate of an electro-optical device can be formed.
[0024]
Preferably, the wiring board includes a scanning line for selecting the switching transistor, a data line for outputting a data signal corresponding to an amount of charge held in the storage capacitor, and a data line for supplying the current driven light emitting element. Power supply line is formed. By forming the scanning lines and the like on the wiring substrate in advance, the panel substrate of the electro-optical device can be easily formed only by peeling and transferring the element chip on the wiring substrate.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
First Embodiment of the Invention
FIG. 1 is a cross-sectional view of a semiconductor chip provided with bumps for connecting to a wiring board. As shown in FIG. 1, an electrode pad 12 made of an aluminum electrode or the like is provided on a semiconductor chip 11, a passivation film 13 for protecting the semiconductor chip 11 from external moisture, heat, impact, etc., and an electroless nickel plating. And the bumps 14 having a convex cross-section (convex cross-section) formed by the above. In such a structure, an opening is formed by etching the passivation film 13 so that the electrode pad 12 is exposed on the surface, and a nickel film is reduced and deposited on the electrode pad 12 exposed from the opening by electroless plating. Is formed by forming a bump 14 having a convex cross section. The electroless plating solution contains a main component (metal salt, reducing agent) and an auxiliary component (pH adjuster, buffer, complexing agent, accelerator, stabilizer, modifier) to reduce and deposit a nickel film. Contains nickel ions and hypophosphite ions as main components. Since the nickel film formed by electroless plating is uniformly deposited, it has few defects and is excellent in hardness, corrosion resistance and wear resistance.
[0026]
In order to grow the bump 14 on the electrode pad 12 to a desired size, it is necessary to appropriately adjust the nickel concentration, the pH value, the plating temperature, the stirring speed, the plating time, the plating speed, the amount of the stabilizer, and the like. Become. In particular, when a stabilizer such as Bi or Pb is used, the oxidation reaction of hypophosphite ions is suppressed, and subsequent nickel deposition is not performed, so that the deposition position of the nickel film can be selectively controlled. Since the electroless nickel plating is formed by reducing and depositing nickel ions with a reducing agent without using an external power supply, nucleation is performed on the electrode pad 12 exposed from the opening of the passivation film 13 and the electrode pad is formed. When the nickel film 12 is immersed in the plating solution, the nickel film grows isotropically from the opening of the passivation film 13 to form a bump 14 having a convex portion 14a having a substantially spherical curved tip. In order to prevent oxidation, the surface of the bump 14 is desirably surface-treated with gold (Au).
[0027]
FIG. 2 is a cross-sectional view of a wiring board (mounting board) provided with bumps for connecting to a semiconductor chip. As shown in FIG. 1, an electrode pad 22 made of an aluminum electrode or the like, a passivation film 23 for protecting the wiring board 21 from external moisture, heat, impact, and the like, and a base for plating film deposition are provided on the wiring board 21. And a bump 25 having a concave section (concave section) formed by electroless nickel plating. At the tip of the bump 25, a concave portion 25a is formed having a size such that the convex portion 14a of the bump 14 can fit into the concave portion 25a. It is desirable that the cross-sectional shape of the concave portion 25a is substantially the same as the cross-sectional shape of the convex portion 14a. However, if reliable and stable joining of the bump 14 and the bump 25 can be obtained, the cross-sectional shapes of both are necessarily similar. It is not necessary that the main portion of the convex portion 14a be accommodated in the concave portion 25a and that a certain contact area between them be secured. If the bumps 14 and 25 are turned inward under precise alignment of the semiconductor chip 11 and the wiring board 21 and the bumps 14a and the recesses 25a are joined so that the protrusions 14a and the recesses 25a are fitted to each other, lateral displacement due to vibration or the like can be obtained. And a reliable and stable connection between the semiconductor chip 11 and the wiring board 21 can be obtained.
[0028]
FIG. 4 is a process chart for forming the bumps 25 on the wiring board 21. As shown in FIG. 2A, the passivation film 23 is etched so that the electrode pad 22 is exposed on the surface, and a substantially cylindrical opening 23a is formed. Next, as shown in FIG. 2B, an aluminum thin film 24a serving as a base for plating deposition is formed by a film forming method such as a sputtering method or a CVD method. The aluminum thin film 24a is desirably formed so as to cover the side wall of the opening 23a and the surface of the electrode pad 22 with as uniform a thickness as possible. Next, as shown in FIG. 3C, a resist is applied, exposed, and developed on the aluminum thin film 24a, leaving the resist 26 near the opening 23a, and removing other portions. Next, as shown in FIG. 3D, the aluminum thin film 24a is etched using the resist 26 remaining near the opening 23a as a mask to form a base electrode 24 patterned to cover the periphery of the opening 23a. . By such a process, the base electrode 24 including the flange portion 24b extending outward from the opening 23a and the bottomed cylindrical concave portion 24c depressed in the depth direction of the opening 23a is formed.
[0029]
Next, as shown in FIG. 3E, after performing surface treatment such as surface polishing, degreasing, and acid immersion of the base electrode 24, a nickel film is reduced and deposited on the base electrode 24 by electroless plating. Since the nickel film grows isotropically from each point of the flange portion 24b and the concave portion 24c, the bump 25 is formed to have a concave cross section. In the case of electroless plating, unlike electroplating, since there is no influence of current distribution, it is possible to directly apply a plating treatment to the underlying electrode 24 (plated body) having a complicated shape with a uniform film thickness. . Further, the nickel film deposited by electroless plating has characteristics such as few pinholes and high hardness. In order to prevent oxidation, the surface of the bump 25 is desirably surface-treated with gold (Au).
[0030]
FIG. 5 is a cross-sectional view showing a state in which the semiconductor chip 11 and the wiring substrate 21 are joined by using the peeling transfer method. The semiconductor chip 11 is stacked on the transfer source substrate 17 via the separation layer 16 and the intermediate layer 15. The transfer source substrate 17 is preferably made of a light-transmitting material, and has a light transmittance of preferably 10% or more, more preferably 50% or more. If the light transmittance is too low, the attenuation of irradiation light increases, and a large amount of light is required to peel off the separation layer 16. The transfer source substrate 17 is preferably made of a material having a higher thermal strain point than the process temperature (350 ° C. to 1000 ° C.), such as quartz glass, soda glass, Corning, and NEC Glass OA-2. Heat resistant glass, synthetic resin and the like are preferred. The thickness of the transfer source substrate 17 is not particularly limited, but is preferably about 0.1 to 5.0 mm, more preferably about 0.5 to 5.0 mm. In order to make the amount of transmitted light uniform, it is desirable that the thickness of the transfer source substrate 17 be uniform.
[0031]
The separation layer 16 is a thin film configured to cause intra-layer separation and / or interfacial separation when irradiated with irradiation light. Upon receiving the irradiation light, the separation layer 16 is formed between atoms or molecules of a substance constituting the separation layer 16. The bonding force between them disappears or decreases. Causes of causing delamination or interfacial delamination include, for example, ablation and gas release. Ablation means that the solid material that has absorbed the irradiation light is photochemically or thermally excited and the surface or internal bonds of atoms or molecules are cut and released, and mainly the constituent material of the separation layer 16 Is accompanied by a phase change such as melting or evaporation. Examples of the composition of the separation layer 16 include (1) amorphous silicon, (2) silicon oxide, silicate compound, titanium oxide, titanium oxide, zirconium oxide, zirconate compound, lanthanum oxide, and lanthanum oxide compound. Various oxide ceramics and dielectrics can be used. As the semiconductor silicon oxide, SiO, SiO 2 , Si 3 O 2 And the like. Examples of the silicate compound include, for example, K 2 SiO 3 , Li 2 SiO 3 , CaSiO 3 , ZrSiO 4 , Na 2 SiO 3 Is mentioned. As titanium oxide, TiO, Ti 2 O 3 , TiO 2 And as the titanate compound, for example, BaTiO 4 , BaTiO 3 , Ba 2 Ti 9 O 20 , BaTi 5 O 11 , SrTiO 3 , PbTiO 3 , MgTiO 3 , ZrTiO 2 , SnTiO 4 , Al 2 TiO 5 , FeTiO 3 Is mentioned. As zirconium oxide, ZrO 2 And the zirconate compound includes, for example, BaZrO 3 , ZrSiO 4 , PbZrO 3 , MgZrO 3 , K 2 ZrO 3 Is mentioned.
[0032]
Other examples of the separation layer 16 include (3) ceramics such as PZT, PLZT, PLLZT, and PBZT, or ferroelectrics; (4) nitride ceramics such as silicon nitride, aluminum nitride, and titanium nitride; 5) Organic polymer materials and (6) metals. As an organic polymer material, -CH 2 -, -CO- (ketone), -CONH- (amide), -NH- (imide), -COO- (ester), -N = N- (azo), -CH = N- (shif), etc. Is not particularly limited as long as it has many of these bonds. Further, the organic polymer material may have an aromatic hydrocarbon in the structural formula. As such organic polymer materials, polyolefins such as polyethylene and polypropylene, polyimides, polyamides, polyesters, polymethyl methacrylate (PMMA), polyphenylene sulfide (PPS), polyether sulfone (PES), and epoxy resins are preferable. It is. Examples of the metal include Al, Li, Ti, Mn, In, Sn, Y, La, Ce, Nd, Pr, Gd, and Sm, or an alloy containing at least one of these.
[0033]
The thickness of the separation layer 16 varies depending on various conditions such as the composition, the layer structure, and the formation method of the separation layer 16, but is preferably about 1 nm to 20 μm, more preferably about 10 nm to 20 μm, and further preferably about 41 nm to 1 μm. . If the thickness of the separation layer 16 is too small, the uniformity of the film is impaired, and the separation may be uneven. On the other hand, if the thickness is too large, good separation of the separation layer 16 is ensured. It is necessary to increase the amount of irradiation light, and it takes time to remove the separation layer 16 in a later step. The method for forming the separation layer 16 is not particularly limited, and is appropriately selected according to various conditions such as a film composition and a film thickness. Various vapor deposition methods such as CVD, vapor deposition, molecular beam deposition, sputtering, ion plating, PVD, various plating methods such as electroplating, immersion plating, and electroless plating, Langmuir-Blodgett method, spin coating, spray coating, Coating methods such as roll coating, various printing methods, transfer methods, ink jet methods, powder jet methods, sol-gel methods, and the like can be mentioned. The intermediate layer 15 functions as a protective layer for physically or chemically protecting the semiconductor chip 11 when peeling and transferring the semiconductor chip 11 to the wiring board 21.
[0034]
An anisotropic conductive paste (ACP) 41 made of an adhesive containing conductive particles 30 is applied to the surface of the semiconductor chip 11 as the transfer target layer, and the bump 14 of the semiconductor chip 11 and the wiring board 21 are applied. The wiring board 21 and the semiconductor chip 11 are pressed against each other with an appropriate pressure under precise alignment so that the unevenness of the bumps 25 can be fitted, so that the electrical connection between them is ensured. The anisotropic conductive paste 41 is obtained by dispersing conductive particles 30 in an adhesive layer made of a thermoplastic, thermosetting, or ultraviolet curable resin, and exhibits conductivity in a direction in which the semiconductor chip 11 and the wiring board 21 are pressed. I do. FIG. 3 is a cross-sectional view of the conductive particles 30 included in the anisotropic conductive paste 41. As shown in the figure, the conductive particles 30 include a core 31 made of metal fine particles having a diameter of about several μm, and an insulating film 32 covering the surface of the core 31. As the insulating film 32, for example, an insulating thin film such as a silicon dioxide film is used. When the semiconductor chip 11 and the wiring board 21 are turned inward and both are pressed with an appropriate pressure via the anisotropic conductive paste 41, the insulating film 32 of the conductive particles 30 located on the uneven portions of the bumps 14 and 25 is crushed, The conductive core 31 is exposed on the surface. Then, in the exposed portion of the core 31, the bumps 14 and 25 conduct, so that the electrical connection between the semiconductor chip 11 and the wiring board 21 is secured.
[0035]
When the semiconductor chip 11 and the wiring board 21 are joined, irradiation light is emitted from the back surface of the transfer source substrate 17. After being transmitted through the transfer source substrate 17, the irradiation light is absorbed by the separation layer 16, and induces separation within the separation layer 16 or interface separation. Then, the intermolecular bond of the separation layer 16 is weakened, and the semiconductor chip 11 is separated from the transfer source substrate 17. The irradiation light is not particularly limited as long as it causes separation within the separation layer 16 or separation at the interface, and examples thereof include X-ray, ultraviolet light, visible light, infrared light (heat ray), laser light, and the like. Examples include millimeter waves, microwaves, electron beams, and radiation (α rays, β rays, and γ rays), but laser light is preferable in that ablation is easily caused. Examples of the laser light include a gas laser and a solid-state laser. In particular, excimer laser, Nd-YAG laser, Ar laser, CO 2 Lasers, He-Ne lasers and the like are preferred. Since the excimer laser outputs high energy at a short wavelength, it is possible to cause the delamination of the separation layer 16 in an extremely short time. If there is wavelength dependence in order to induce ablation in the separation layer 16, the wavelength of the irradiated laser beam is preferably about 100 to 350 nm. Further, in order to induce phase change such as gas release, vaporization, and sublimation in the separation layer 16 to cause delamination or interfacial delamination, the wavelength of the laser beam is desirably about 350 to 1200 nm.
[0036]
FIG. 6 is a cross-sectional view after the semiconductor chip 11 is peeled and transferred to the wiring board 21. The intermediate layer 15 formed on the back surface of the semiconductor chip 11 has been removed together with the release layer 16. An anisotropic conductive paste 41 in which conductive particles 30 are dispersed is interposed between the semiconductor chip 11 and the wiring board 21, and when the semiconductor chip 14 is peeled and transferred to the wiring board 21, the bumps 14 and 25 are pressed. As a result, the insulating film 32 of the conductive particles 30 is peeled off or crushed, so that the bumps 14 and 25 can be conducted through the core 31 exposed on the surface. As described above, according to the present embodiment, the nickel film is reduced and deposited on the surface of the base electrode 24 having a concave cross section, and the bump 25 having the concave portion 25a which is depressed inside is formed. The conductive particles 30 can be seated at a high density. The bumps 14 of the semiconductor chip 11 can be electrically connected to the bumps 25 by direct contact of the protrusions 14a at the tips with the recesses 25a or indirectly through the conductive particles 30. That is, by forming the bumps 25 with a concave cross section, the contact area with the bumps 14 having a convex cross section can be ensured as much as possible, and more stable electrical connection between the semiconductor chip 11 and the wiring board 21 can be achieved. Can be secured.
[0037]
In order to bond the bumps 14 and the bumps 25 reliably, it is necessary to precisely control the shape of the bumps in the order of μm. However, the bumps 25 can be formed to have a uniform film thickness by electroless nickel plating. Since the deposition rate can be relatively easily controlled by the nickel concentration, the pH value, the plating temperature, the stirring speed, the plating time, the amount of the stabilizer, and the like, the processing accuracy of the base electrode 24 is important. The dimensions of the flange portion 24b and the concave portion 24c of the base electrode 24 are the processing accuracy of the resist 26, the anisotropy of the etching process on the aluminum thin film 24a, the processing accuracy of the opening 23a in the passivation film 23, the film thickness of the passivation film 23, and Since they depend on the film thickness of the electrode pad 22 and the like, they are processed with a desired accuracy, so that a concave portion 24c processed to a desired inner diameter and depth and a flange portion 24b processed to a desired outer diameter are provided. The base electrode 24 can be formed.
[0038]
In the above description, the anisotropic conductive paste 41 including the conductive particles 30 is used as a means for bonding the semiconductor chip 11 and the wiring board 21. However, the present invention is not limited to this. As shown in (2), the semiconductor chip 11 and the wiring board 21 may be bonded using a liquid adhesive (NCP: Non Conductive Paste) 42 not containing the conductive particles 30. When the liquid adhesive 42 is used, since the conductive particles 30 are not included, in order to obtain good connection between the bumps 14 and 25, the wiring board 21 has a certain degree of flexibility and flexibility as a flexible board. It is preferable to use a material having properties. If the wiring board 21 has flexibility and flexibility, the ratio of the bumps 14 and 25 in surface contact can be increased.
[0039]
Further, in the above description, the case where the bumps 14 formed on the semiconductor chip 11 are formed to have a convex cross section has been exemplified. However, the present invention is not limited to this. For example, as shown in FIG. May be formed to have a concave cross section. The bump 19 is formed by reducing and depositing a nickel film on the surface of the base electrode 18 having a concave cross section connected to the electrode pad 12 at the opening of the passivation film 13. The specific manufacturing process of the base electrode 18 and the bump 19 is the same as the above-described process (see FIG. 4). The alignment was adjusted under precise alignment so that the bumps 19 of the semiconductor chip 11 and the bumps 25 of the wiring board 21 faced inward, and an anisotropic conductive paste 41 containing the conductive particles 30 was interposed between the two. By peeling and transferring the semiconductor chip 11 to the wiring board 21 in the state, the semiconductor chip 11 and the wiring board 21 can be electrically connected. Since both of the bumps 19 and 25 are formed to have a concave cross-section, a large contact area between the bumps 19 and 25 can be secured in the flat portions at the tips of the bumps 19 and 25. Further, the insulating film 32 of the conductive particles 30 seated in the concave portions 19a, 25a of the bumps 19, 25 is crushed by the pressing force of the bumps 19, 25, and is peeled off through the conductive core 31 exposed on the surface. Since the bumps 19 and 25 conduct, stable electrical connection between the semiconductor chip 11 and the wiring board 21 can be secured.
[0040]
FIG. 8 shows an example in which the anisotropic conductive paste 41 is used as a means for bonding the semiconductor chip 11 and the wiring board 21. However, the present invention is not limited to this. For example, as shown in FIG. Can also be used. When the liquid adhesive 42 is used, since the conductive particles 30 are not included, by forming the bumps 19 and 25 in a concave cross section, a large contact area between them can be secured, and more stable electrical connection can be obtained. Can be In particular, when the liquid adhesive 42 is used, it is desirable to make the tips of the bumps 19 and 25 as flat as possible so that the bumps 19 and 25 can make surface contact.
[0041]
Embodiment 2 of the invention
The second embodiment of the present invention relates to a technique for forming a desired electronic device by peeling and transferring an element chip on a wiring substrate. In this embodiment, a case where an organic EL display panel is formed by peeling and transferring a TFT chip, an EL chip, and the like on a wiring substrate will be described as an example. FIG. 11 is a circuit configuration diagram of a pixel of the organic EL display. In the figure, reference numeral 52 denotes a scanning line V sel The switching transistor Tr1 connected to the dat And a drive current corresponding to the control voltage held in the storage capacitor C are supplied to the power supply line V. dd Is a TFT chip including a drive transistor Tr2 that receives power supply from the OLED and supplies it to the organic EL element OLED. Reference numeral 62 denotes an EL chip including an organic EL element OLED in which device layers such as a cathode / electron transport layer / light emitting layer / hole transport layer / pixel electrode are stacked. The stacked structure of the organic EL element OLED may be a cathode / light-emitting layer / pixel electrode, a cathode / electron transport layer / light-emitting layer / pixel electrode, a cathode / light-emitting layer / hole transport layer / pixel electrode, or the like.
[0042]
FIG. 10 is an explanatory diagram showing a procedure for forming an organic EL display panel by peeling and transferring the TFT chip 52 and the EL chip 62 on the wiring substrate 21. The scanning lines V are arranged on the wiring substrate 21 so that pixels are formed in a matrix of N rows and M columns. sel , Data line I dat , Power supply line V dd Are formed in a predetermined pattern in advance. That is, the scanning line V sel Are formed in advance so as to be parallel to the row direction of the pixel matrix. dat And power supply line V dd Are formed in advance so as to be parallel to the column direction of the pixel matrix so as to intersect in a direction substantially orthogonal to this. Here, for convenience of explanation, FIG. sel , Data line I dat , Power supply line V dd Is not shown. On the wiring substrate 21, N transfer regions T 1, T 2,..., TN to which the TFT chips 52 are to be transferred and the EL chips 62 are to be transferred, corresponding to the positions where the pixels are to be formed. .., EN are set in advance. In the transfer area Tn (n = 1 to N), an area for transferring the M TFT chips 52 arranged in one direction is secured, and in the transfer area En (n = 1 to N), one area is provided. An area sufficient to transfer M EL chips 62 arranged in the direction is secured. The M TFT chips 52 and the EL chips 62 transferred to the transfer regions Tn and En arranged in the n-th row form a pixel group arranged in the n-th row.
[0043]
On the other hand, the TFT chips 52 are formed in a matrix on the TFT chip forming substrate 51 via a separation layer (not shown) and an intermediate layer. The TFT chip forming substrate 51 is desirably made of a light-transmissive material similarly to the transfer source substrate 17 described above. The TFT chip forming substrate 51 includes at least N chip forming regions ST1, ST2,..., STN. Each of the chip forming regions ST1, ST2,. 52 are formed. At least M TFT chips 52 arranged in the row direction among the TFT chips 52 formed in the chip forming region STn (n = 1 to N) are transferred to the transfer region Tn (n = 1 to N). To transfer the TFT chip 52 onto the wiring board 21, the alignment is performed using the alignment marks B 1 to B 3 of the TFT chip forming substrate 51 and the alignment marks A 1 to A 3 of the wiring board 21 as marks. In the state where the TFT chip forming substrate 51 is overlapped, light irradiation or the like is performed from the back surface of the TFT chip forming substrate 51, and through the peeling of the peeling layer interposed between the TFT chip forming substrate 51 and the TFT chip 52 or the interface peeling. The TFT chip 52 is transferred to the wiring board 21.
[0044]
EL chips 62 are formed in a matrix on the EL chip forming substrate 61 via a separation layer and an intermediate layer (not shown). The EL chip forming substrate 61 is desirably made of a light transmissive material, similarly to the transfer source substrate 17 described above. The EL chip forming substrate 61 includes at least N chip forming regions SE1, SE2,..., SEN, and each chip forming region SE1, SE2,. 62 are formed. At least M EL chips 62 arranged in the row direction among the EL chips 62 formed in the chip formation region SEn (n = 1 to N) are transferred to the transfer target region En (n = 1 to N). To transfer the EL chip 62 onto the wiring substrate 21, the alignment marks C 1 to C 3 of the EL chip forming substrate 61 and the alignment marks A 1 to A 3 of the wiring substrate 21 are aligned with the mark, and the EL chip 62 is transferred onto the wiring substrate 21. Light irradiation is performed from the back surface of the EL chip forming substrate 61 in a state where the EL chip forming substrate 61 is overlapped, and through the peeling of the peeling layer interposed between the EL chip forming substrate 61 and the EL chip 62 or the interface peeling. The EL chip 62 is transferred onto the wiring board 21. The alignment marks A1 to A3, B1 to B3, and C1 to C3 are provided at the corners of each substrate for convenience of description, but are not necessarily provided at these positions.
[0045]
FIG. 12 is a sectional structural view of the organic EL display panel when the TFT chip 52 is peeled and transferred to the wiring board 21. On the TFT chip forming substrate 51, a TFT chip 52 is formed via an intermediate layer 15 and a release layer 16. An electrode pad 53 for connecting to the wiring board 21 is formed on the TFT chip 52. On the other hand, the electrode pads 27 and bumps 81 for electrically connecting to the TFT chip 52 and the electrode pads 28 and bumps 82 for electrically connecting to the EL chip 62 are formed on the wiring board 21. Have been. In addition, a liquid adhesive 42 is applied between the TFT chip 52 and the wiring board 21 to bond them. Each of the bumps 81 and 82 is a projection electrode having a convex cross section formed by electroless plating. Electroless plating conditions are devised so that the height of the bump 81 is higher than the height of the bump 82. That is, the height of the bump connected to the element chip is changed according to the type of the element chip to be transferred onto the wiring board 21. As described above, by setting the height of the bump 81 to be connected to the TFT chip 52 higher than the height of the bump 82 to be connected to the EL chip 62, when the TFT chip 52 is bonded to the bump 81, Inadvertent joining with the bumps 82 can be prevented. If the heights of the bumps 81 and 82 are substantially uniform, there is a possibility that the TFT chip 52 will be bonded to the bump 82 when the TFT chip 52 is transferred to the wiring board 21. Such a situation can be avoided as much as possible by providing a height difference in the height.
[0046]
In the EL chip 62, the electrode pads 28 and the bumps 82 are designed to have larger openings than the electrode pads 27 and the bumps 81 in order to supply a driving current to the organic EL element OLED. The electrode pad 53 of the TFT chip 52 and the electrode pad 81 of the wiring board 21 are precisely adjusted so as to be bonded to each other, and the TFT chip 52 and the wiring board 21 are pressure-bonded with an appropriate pressure. When irradiation light such as laser light is irradiated from the back surface, peeling within the peeling layer or peeling at the interface occurs in the peeling layer 16, and the TFT chip 52 can be transferred to the wiring substrate 21. The laser irradiation selects the TFT chips 52 to be transferred, and irradiates the individual TFT chips 52 or a group of selected TFT chips 52 collectively.
[0047]
FIG. 13 is a sectional structural view of the organic EL display panel when the EL chip 62 is peeled and transferred onto the wiring board 21. The TFT chip 52 is already connected to the wiring board 21. An EL chip 62 is formed on an EL chip forming substrate 61 via an intermediate layer 15 and a release layer 16. Further, an electrode pad 63 for connecting to the wiring board 21 is formed on the EL chip 62. An anisotropic conductive paste 41 containing the conductive particles 30 is applied between the EL chip 62 and the wiring board 21 so that the electrode pads 63 and the bumps 82 are electrically connected via the conductive particles 30. The electrode pads 63 of the EL chip 62 and the bumps 82 of the wiring board 21 are precisely adjusted for alignment, and the EL chip 62 and the wiring board 21 are press-bonded with an appropriate pressure. When irradiation light such as a laser beam is applied, in-layer peeling or interface peeling occurs in the peeling layer 16, and the EL chip 62 can be transferred to the wiring substrate 21. In the laser irradiation, after the EL chips 62 to be transferred are selected, irradiation is performed collectively on each EL chip 62 or on a selected group of EL chips 62 at a time.
[0048]
FIG. 14 is a cross-sectional view for explaining a manufacturing process of the bump 82 for connecting to the EL chip 62. In the EL chip 62, the electrode pads 28 and the bumps 82 are designed to have larger openings than the electrode pads 27 and the bumps 81 for the purpose of supplying a drive current to the organic EL element OLED. Is performed, the bumps 81 and 82 have the same height. Therefore, as preparation for the formation of the bumps 82, a large number of small-diameter openings 23b are formed in the passivation film 23 in accordance with the positions where the bumps 82 are to be formed, that is, the positions where the electrode pads 28 are to be formed. In a state where the bump 82 has not been formed yet, the electrode pad 28 is exposed on the surface through the opening 23b. After performing pre-preparation of the electroless plating process in the vicinity of the opening 23b, the amount of the stabilizer contained in the plating solution is appropriately adjusted, and the electrode pad 28 is immersed in the plating solution. Can be moderately adjusted. That is, by adjusting the amount of the stabilizer, it is possible to selectively control the presence or absence of the reductive deposition of the nickel film in the opening 23b. Since the reductive deposition of the nickel film is performed isotropically from every place immersed in the plating solution, the surface of the electrode pad 28 located inside the small-diameter opening 23b in which the plating solution is hardly immersed has a nickel film. The environment is difficult to grow. Under such an environment, by further adjusting the amount of the stabilizer, it is possible to selectively restrict the growth of the nickel film in the opening 23b. When the electroless plating process is performed under such plating conditions, the deposition growth rate of the bumps 82 becomes slow, and the height of the bumps 82 becomes lower than the height of the bumps 81 for connecting to the TFT chip 52.
[0049]
FIG. 15 is a process diagram for explaining a manufacturing process of the bump 82 for connecting to the EL chip 52 and other processes. As shown in FIG. 3A, first, the passivation film 23 on the wiring substrate 21 is subjected to etching treatment, and an opening 23c for exposing an electrode pad 27 for connecting to the TFT chip 52 to the surface, and an EL chip An opening 23d for exposing the electrode pad 28 for connection to the surface 62 is formed. Next, as shown in FIG. 2B, a nickel film is reduced and deposited on the surfaces of the electrode pads 27 and 28 and on the passivation film 23 near the openings 23c and 23d by electroless plating, and the precursors of the bumps 81 and 82 are formed. The nickel films 81a and 82a serving as a body are formed. Next, as shown in FIG. 3C, a mask 90 is formed on the surface of the nickel film 82a, and electroless nickel plating is performed. The mask 90 is not particularly limited as long as it inhibits the reductive deposition of electroless nickel plating, and any insulating film, metal thin film, or the like can be used, but can be easily removed in a later step. Desirably, it is a thin film. By this step, while the nickel film is re-deposited on the nickel film 81a, the re-deposition of the nickel film on the nickel film 82a is hindered, and the height of the bumps 81, 82 can be adjusted. . Next, as shown in FIG. 4D, when the nickel film is re-deposited on the nickel film 82a in an appropriate amount so that the height of the bump 81 becomes a desired value, the electroless plating is performed. The processing is stopped, and the mask 90 is removed. Thereby, bumps 81 and 82 having a desired height difference h are formed.
[0050]
In the present embodiment, the bumps 81 and 82 for connecting to the TFT chip 62 and the EL chip 52 have been described by exemplifying a structure having a convex cross section. However, the present invention is not limited to this. A structure having a concave cross section may be adopted as the structure of the bumps 81 and 82. As described above, according to the present embodiment, the bumps to be connected to the element chips are provided with a height difference according to the type of the element chips to be transferred to the wiring board. The element chip can be transferred to a desired transfer area, and the yield can be improved.
[Brief description of the drawings]
FIG. 1 is a sectional view of a semiconductor chip of the present embodiment.
FIG. 2 is a cross-sectional view of the wiring board of the present embodiment.
FIG. 3 is a sectional view of a conductive particle.
FIG. 4 is a cross-sectional view illustrating a manufacturing process of the concave bump.
FIG. 5 is a cross-sectional view showing a step of connecting a semiconductor chip and a wiring board.
FIG. 6 is a sectional view showing a connection state between a semiconductor chip and a wiring board.
FIG. 7 is a sectional view showing a connection state between a semiconductor chip and a wiring board.
FIG. 8 is a sectional view showing a connection state between a semiconductor chip and a wiring board.
FIG. 9 is a sectional view showing a connection state between a semiconductor chip and a wiring board.
FIG. 10 is an explanatory diagram of a step of mounting an element chip on a wiring board.
FIG. 11 is a configuration diagram of a pixel circuit of an organic EL display.
FIG. 12 is a cross-sectional view showing a step of connecting a TFT chip and a wiring board.
FIG. 13 is a cross-sectional view illustrating a process of connecting an EL chip and a wiring board.
FIG. 14 is a cross-sectional view showing a process of forming a bump having a cross section.
FIG. 15 is a sectional view showing a step of forming a bump having a cross section.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Semiconductor chip 12 ... Electrode pad 13 ... Passivation film 14 ... Bump 15 ... Intermediate layer 16 ... Separation layer 17 ... Transfer source substrate 18 ... Base electrode 19 ... Bump 21 ... Wiring board 22 ... Electrode pad 23 ... Passivation film 24 ... Base Electrode 25 Bump 26 Resist 27 Electrode pad 28 Electrode pad 30 Conductive particles 31 Core 32 Insulating film 41 Anisotropic conductive paste 42 Liquid adhesive

Claims (18)

実装基板と接続するために素子チップに形成されるバンプ構造であって、無電界めっきにより断面凹状に形成された金属皮膜から成る、バンプ構造。A bump structure formed on an element chip to be connected to a mounting substrate, the bump structure being formed of a metal film formed in a concave cross section by electroless plating. 素子チップと接続するために実装基板に形成されるバンプ構造であって、無電界めっきにより断面凹状に形成された金属皮膜から成る、バンプ構造。A bump structure formed on a mounting board for connection with an element chip, the bump structure being formed of a metal film formed in a concave cross section by electroless plating. 実装基板に形成された断面凸状バンプと接続するために素子チップに形成されるバンプ構造であって、無電界めっきにより断面凹状に形成され、かつ前記断面凸状バンプの凸部と嵌合し得る凹部を具備する金属皮膜から成る、バンプ構造。A bump structure formed on an element chip for connection with a bump having a cross-sectional shape formed on a mounting board, formed in a concave shape by electroless plating, and fitted with a convex portion of the bump having a cross-sectional shape. A bump structure consisting of a metal film with a recess obtained. 素子チップに形成された断面凸状バンプと接続するために配線基板に形成されるバンプ構造であって、無電界めっきにより断面凹状に形成され、かつ前記断面凸状バンプの凸部と嵌合し得る凹部を具備する金属皮膜から成る、バンプ構造。A bump structure formed on a wiring board for connection with a bump having a cross section formed on an element chip, the bump having a cross section formed by electroless plating, and fitting with a projection of the bump having a cross section. A bump structure consisting of a metal film with a recess obtained. 素子チップに形成されたバンプと、実装基板に形成されたバンプとが接続するように前記素子チップと前記実装基板を対向配置した接続構造であって、前記素子チップに形成されるバンプは、無電界めっきにより断面凸状バンプに形成される一方、前記実装基板に形成されるバンプは、無電界めっきにより断面凹状バンプに形成され、前記断面凸状バンプの凸部と前記断面凹状バンプの凹部とが嵌合するように前記素子チップと前記実装基板が接続されて成る、素子チップと実装基板の接続構造。A connection structure in which the element chip and the mounting substrate are opposed to each other so that the bump formed on the element chip is connected to the bump formed on the mounting substrate, and the bump formed on the element chip has no bump. On the other hand, the bumps formed on the mounting substrate are formed on the mounting substrate by electroless plating, while the bumps formed on the mounting substrate are formed on the concave bumps by electroless plating. A connection structure between an element chip and a mounting board, wherein the element chip and the mounting board are connected so that the elements are fitted. 素子チップに形成されたバンプと、実装基板に形成されたバンプとが接続するように前記素子チップと前記実装基板を対向配置した接続構造であって、前記素子チップに形成されるバンプは、無電界めっきにより断面凹状バンプに形成される一方、前記実装基板に形成されるバンプは、無電界めっきにより断面凸状バンプに形成され、前記断面凸状バンプの凸部と前記断面凹状バンプの凹部とが嵌合するように前記素子チップと前記実装基板が接続されて成る、素子チップと実装基板の接続構造。A connection structure in which the element chip and the mounting substrate are opposed to each other so that the bump formed on the element chip is connected to the bump formed on the mounting substrate, and the bump formed on the element chip has no bump. The bumps formed on the mounting substrate are formed on the mounting substrate by electroless plating, while the bumps formed on the mounting substrate are formed on the mounting substrate by electroless plating. A connection structure between an element chip and a mounting board, wherein the element chip and the mounting board are connected so that the elements are fitted. 前記素子チップと前記実装基板は、導電粒子を含む異方性導電ペーストを介して接着される、請求項５又は請求項６に記載の素子チップと実装基板の接続構造。The connection structure between an element chip and a mounting board according to claim 5, wherein the element chip and the mounting board are bonded via an anisotropic conductive paste containing conductive particles. 前記素子チップと前記実装基板は、液状接着剤を介して接着される、請求項５又は請求項６に記載の素子チップと実装基板の接続構造。7. The connection structure between an element chip and a mounting board according to claim 5, wherein the element chip and the mounting board are bonded via a liquid adhesive. 実装基板と接続するために素子チップに形成されるバンプの形成方法であって、断面凹状の下地電極を形成する工程と、無電界めっきにより前記下地電極上に金属皮膜を還元析出し、断面凹状の金属皮膜から成るバンプを形成する工程とを含む、バンプ形成方法。A method for forming a bump formed on an element chip for connection with a mounting substrate, comprising: forming a base electrode having a concave cross section; and reducing and depositing a metal film on the base electrode by electroless plating to form a concave section. Forming a bump made of a metal film. 前記下地電極は、前記素子チップの表面に成膜されたパッシベーション膜の開口部の側壁及び底部に形成される、請求項９に記載のバンプ形成方法。The bump forming method according to claim 9, wherein the base electrode is formed on a side wall and a bottom of an opening of a passivation film formed on a surface of the element chip. 前記開口部は、前記素子チップの電極パッドが表面に露出する位置に開口される、請求項１０に記載のバンプ形成方法。The bump forming method according to claim 10, wherein the opening is opened at a position where an electrode pad of the element chip is exposed on a surface. 少なくとも２種類以上の素子チップを転写元基板から剥離して、前記素子チップの種類毎に予め定められた位置に形成されたバンプと接続することにより電子デバイスを形成するための配線基板であって、前記素子チップの種類に応じて前記バンプに高低差を設けて成る、配線基板。A wiring board for forming an electronic device by peeling at least two or more types of element chips from a transfer source substrate and connecting them to bumps formed at predetermined positions for each type of the element chips. A wiring board, wherein the bump has a height difference according to the type of the element chip. 前記素子チップとして、電気光学装置の画素回路を構成するスイッチングトランジスタ、駆動トランジスタ及び保持容量を含む素子チップと、電流駆動型発光素子を含む素子チップが含まれる、請求項１２に記載の配線基板。13. The wiring board according to claim 12, wherein the element chips include an element chip including a switching transistor, a driving transistor, and a storage capacitor included in a pixel circuit of the electro-optical device, and an element chip including a current-driven light emitting element. 前記配線基板には、前記スイッチングトランジスタを選択するための走査線と、前記保持容量に保持される電荷量に対応したデータ信号を出力するデータ線と、前記電流駆動型発光素子に供給する電源供給線が形成されている、請求項１３に記載の配線基板。A scanning line for selecting the switching transistor, a data line for outputting a data signal corresponding to an amount of charge held in the storage capacitor, and a power supply for supplying the current-driven light-emitting element to the wiring substrate. 14. The wiring board according to claim 13, wherein the line is formed. 請求項１２乃至請求項１４のうち何れか１項に記載の配線基板を備えた電気光学装置。An electro-optical device comprising the wiring substrate according to claim 12. 剥離層を介して転写元基板に形成された素子チップを剥離して、前記素子チップの種類毎に予め定められた配線基板上の所定位置に転写することにより電子デバイスを製造するための方法であって、
第１の転写元基板に形成されている第１の素子チップが前記配線基板上の所定位置に転写されるよう前記第１の転写元基板と前記配線基板とを位置合わせをする工程と、
前記第１の転写元基板から前記第１の素子チップを剥離し、前記第１の素子チップが前記配線基板上の所定位置に形成されている第１のバンプと接続するよう転写する工程と、
第２の転写元基板に形成されている第２の素子チップが前記配線基板上の所定位置に転写されるよう前記第２の転写元基板と前記配線基板とを位置合わせをする工程と、
前記第２の転写元基板から前記第２の素子チップを剥離し、前記第２の素子チップが前記配線基板上の所定位置において前記第１のバンプの高さとは異なる高さに形成されている第２のバンプと接続するよう転写する工程と、
を含む、電子デバイスの製造方法。A method for manufacturing an electronic device by peeling an element chip formed on a transfer source substrate via a peeling layer and transferring the chip to a predetermined position on a wiring substrate predetermined for each type of the element chip. So,
Positioning the first transfer source substrate and the wiring substrate so that the first element chip formed on the first transfer source substrate is transferred to a predetermined position on the wiring substrate;
Removing the first element chip from the first transfer source substrate, and transferring the first element chip so as to be connected to a first bump formed at a predetermined position on the wiring substrate;
Positioning the second transfer source substrate and the wiring substrate such that a second element chip formed on the second transfer source substrate is transferred to a predetermined position on the wiring substrate;
The second element chip is peeled off from the second transfer source substrate, and the second element chip is formed at a predetermined position on the wiring substrate at a height different from the height of the first bump. Transferring to connect to the second bump;
A method for manufacturing an electronic device, comprising: 前記第１の素子チップは、電気光学装置の画素回路を構成するスイッチングトランジスタ、駆動トランジスタ及び保持容量を含む素子チップであり、前記第２の素子チップは、電流駆動型発光素子を含む素子チップである、請求項１６に記載の電子デバイスの製造方法。The first element chip is an element chip including a switching transistor, a driving transistor, and a storage capacitor that constitute a pixel circuit of the electro-optical device, and the second element chip is an element chip including a current driven light emitting element. The method for manufacturing an electronic device according to claim 16. 前記配線基板には、前記スイッチングトランジスタを選択するための走査線と、前記保持容量に保持される電荷量に対応したデータ信号を出力するデータ線と、前記電流駆動型発光素子に供給する電源供給線が形成されている、請求項１７に記載の電子デバイスの製造方法。A scanning line for selecting the switching transistor, a data line for outputting a data signal corresponding to an amount of charge held in the storage capacitor, and a power supply for supplying the current-driven light-emitting element to the wiring substrate. The method for manufacturing an electronic device according to claim 17, wherein the line is formed.
JP2002324047A 2002-11-07 2002-11-07 Bump structure for mounting element chip and method for forming the same Pending JP2004158701A (en)

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