JP2007103878A - Wiring board and manufacturing method thereof - Google Patents

Wiring board and manufacturing method thereof Download PDF

Info

Publication number
JP2007103878A
JP2007103878A JP2005295477A JP2005295477A JP2007103878A JP 2007103878 A JP2007103878 A JP 2007103878A JP 2005295477 A JP2005295477 A JP 2005295477A JP 2005295477 A JP2005295477 A JP 2005295477A JP 2007103878 A JP2007103878 A JP 2007103878A
Authority
JP
Japan
Prior art keywords
conductor
wiring board
opening
bump
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005295477A
Other languages
Japanese (ja)
Other versions
JP4769056B2 (en
Inventor
Seiji Mori
聖二 森
Tatsuya Ito
達也 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP2005295477A priority Critical patent/JP4769056B2/en
Publication of JP2007103878A publication Critical patent/JP2007103878A/en
Application granted granted Critical
Publication of JP4769056B2 publication Critical patent/JP4769056B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Wire Bonding (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring board with which an interval of diameter of conductor bumps can be microfabricated. <P>SOLUTION: A wiring board 1A includes a conductor bump 7 as an external connecting terminal on a board surface MP1. A method of manufacturing the wiring board 1A includes an opening boring step of boring a top insulating layer SR1 forming the board surface MP1 with an opening 6A, and exposing a conductor pad 56 on a bottom surface of the relevant opening 6A; and a bump forming step of applying plating to an exposed portion using a plating resist patterned to expose the inside and the edge of the opening 6A as a mask, and forming the conductor bump 7. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、基板表面に外部接続端子としての導体バンプを有する配線基板及びその製法方法に関する。   The present invention relates to a wiring board having conductor bumps as external connection terminals on the surface of the board and a method for manufacturing the same.

従来より、半導体集積回路素子（以下「ＩＣチップ」という）が搭載される配線基板は、ＩＣチップ接続用の外部接続端子として、基板表面から盛り上がった形状の半田からなる導体バンプを有する。   2. Description of the Related Art Conventionally, a wiring board on which a semiconductor integrated circuit element (hereinafter referred to as “IC chip”) is mounted has a conductor bump made of solder having a shape rising from the surface of the board as an external connection terminal for connecting an IC chip.

特開２００５−２６４９１JP 2005-26491 A

上記のような導体バンプは、バンプ径に対応した開口を有する塗布用マスクを用いて半田ペーストを印刷形成し、リフローすることによって得ることができる。しかしながら、このように導体バンプをペースト印刷により得る手法では、導体バンプの間隔や径などを微細化しようにも限度があり、近年、配線基板に求められている高密度配線化に対応することが困難である。   The conductor bump as described above can be obtained by printing and reflowing a solder paste using a coating mask having an opening corresponding to the bump diameter. However, in the method of obtaining the conductor bumps by paste printing in this way, there is a limit to miniaturizing the interval and the diameter of the conductor bumps, and in recent years, it can cope with the high density wiring required for the wiring board. Have difficulty.

本発明は、上記問題を鑑みて為されたものであり、導体バンプの間隔や径などの微細化が可能な配線基板の製造方法を提供することを目的とする。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a wiring board capable of miniaturizing the interval and diameter of conductor bumps.

課題を解決するための手段及び発明の効果Means for Solving the Problems and Effects of the Invention

上記課題を解決するため、本発明の配線基板の製造方法は、基板表面に外部接続端子としての導体バンプを有する配線基板の製造方法であって、基板表面をなす表層絶縁層に開口を穿設して、当該開口の底面に導体パッドを露出させる開口穿設工程と、開口内およびその周縁を露出させるようパターンニングされたメッキレジストをマスクとして、その露出部分にメッキを施して導体バンプを形成するバンプ形成工程と、を備えることを特徴とする。   In order to solve the above problems, a method for manufacturing a wiring board according to the present invention is a method for manufacturing a wiring board having conductor bumps as external connection terminals on the surface of the board, and an opening is formed in a surface insulating layer forming the surface of the board. Then, an opening drilling process for exposing the conductor pad to the bottom surface of the opening and a plating resist patterned so as to expose the inside and the periphery of the opening as a mask, and plating the exposed portion to form a conductor bump And a bump forming step.

これによれば、フォトリソグラフィーを代表とする周知のリソグラフィー技術を用いて微細にパターンニングされたメッキレジストによって、配線基板の内部配線を得るが如く、メッキの微細なパターンとして導体バンプを得ることが可能となるため、ペースト印刷の場合と比較して、微細な間隔や径の導体バンプを形成することができる。また、かかる製造方法によって得られる本発明の配線基板は、以下の特徴を有する。   According to this, it is possible to obtain a conductor bump as a fine pattern of plating, as in the case of obtaining an internal wiring of a wiring board by a plating resist finely patterned by using a well-known lithography technique typified by photolithography. Therefore, it is possible to form conductor bumps with finer intervals and diameters than in the case of paste printing. Moreover, the wiring board of the present invention obtained by such a manufacturing method has the following characteristics.

すなわち、本発明の配線基板は、基板表面に外部接続端子としての導体バンプを有する配線基板であって、基板表面をなす表層絶縁層に開口が設けられ、当該開口の底面をなす導体パッドに接続された導体バンプが、メッキによって開口の内壁および周縁に密着して形成されてなることを特徴とする。   That is, the wiring board of the present invention is a wiring board having conductor bumps as external connection terminals on the substrate surface, and an opening is provided in the surface insulating layer forming the substrate surface and connected to the conductor pad forming the bottom surface of the opening. The conductive bump formed is formed in close contact with the inner wall and peripheral edge of the opening by plating.

これによれば、導体バンプがメッキにより形成されていることから、導体パッドのみならず、鉤型に形成されて開口の内壁および周縁にも密着しており、導体バンプの密着面積が大きく、密着性が向上したものとなっている。すなわち、表層絶縁層には粗化処理が施されていることから、開口の内壁および周縁へのメッキの密着性が強固なものとなる。そのため、配線基板を構成する樹脂材料とそれに搭載されるＩＣチップとの熱膨張差によって、その間の導体バンプに剪断応力が加わっても、導体バンプの密着性が向上していることにより、その剪断応力を吸収し、接合部分におけるクラックの発生が防止されるため、良好な接続信頼性が得られる。これに対し、従来のペースト印刷では、ペーストを開口内に印刷により流し込むことにより導体バンプを形成しているため、導体バンプは、開口の内壁に密着するというよりは接触しているに過ぎず、本発明における導体バンプよりも密着性が劣るものとなっている。   According to this, since the conductor bump is formed by plating, it is formed not only in the conductor pad but also in a bowl shape and is in close contact with the inner wall and the peripheral edge of the opening, and the contact area of the conductor bump is large, and the contact It has become improved. That is, since the surface insulating layer is roughened, the adhesion of the plating to the inner wall and peripheral edge of the opening becomes strong. Therefore, even if shear stress is applied to the conductor bump between the resin material constituting the wiring board and the IC chip mounted on the resin material, the adhesion of the conductor bump is improved. Since the stress is absorbed and the occurrence of cracks at the joint is prevented, good connection reliability can be obtained. On the other hand, in conventional paste printing, since the conductor bump is formed by pouring the paste into the opening by printing, the conductor bump is only in contact rather than in close contact with the inner wall of the opening, Adhesiveness is inferior to the conductor bump in this invention.

次に、本発明の配線基板では、導体パッドとそれに接続された導体バンプとをＣｕメッキにより形成することができる。これによれば、導体パッドと導体バンプとが同じＣｕメッキにより形成されるため、両者の密着性が向上し、良好な接続信頼性が得られる。これに対し、従来の半田ペーストを用いた導体バンプは、通常、Ｃｕメッキからなる導体パッド上にＮｉ−Ａｕメッキを介して設置されるが、この場合、無電解Ｎｉメッキ浴に含まれるリン酸化合物によって、半田からなる導体バンプとの界面にリン濃化層が形成されてしまい、この層でクラックが発生し易いことから、本発明における導体バンプよりも接続信頼性が劣る。   Next, in the wiring board of the present invention, the conductor pads and the conductor bumps connected thereto can be formed by Cu plating. According to this, since the conductor pads and the conductor bumps are formed by the same Cu plating, the adhesion between them is improved, and good connection reliability is obtained. On the other hand, a conductor bump using a conventional solder paste is usually installed on a conductor pad made of Cu plating via Ni-Au plating. In this case, phosphoric acid contained in an electroless Ni plating bath is used. The compound forms a phosphorus-enriched layer at the interface with the conductor bump made of solder, and cracks are likely to occur in this layer, so the connection reliability is inferior to the conductor bump in the present invention.

次に、本発明の配線基板では、導体バンプの頂面を凹面とすることができる。すなわち、本発明の配線基板では、基板表面に外部接続端子としての導体バンプを有する配線基板であって、基板表面をなす表層絶縁層に開口が設けられ、当該開口の底面をなす導体パッドに接続された導体バンプは、その頂面が凹面とされてなることを特徴とする。これによれば、配線基板に搭載されるＩＣチップがフリップチップ接続される場合、導体バンプの凹面状の頂面に、それよりも径小のＩＣチップの端子が嵌ることから（図２参照）、ＩＣチップが位置ズレを起こし難いという利点がある。また、導体バンプは、開口の内壁および周縁に密着する形状（鉤型）となっており、基板表面上に表れた部分が開口径よりも径大であることから、頂面を凹面状に形成しやすい。また、開口径に捕われることなく、基板表面上に表れた部分（ひいては導体バンプの頂面）をＩＣチップの端子よりも径大に形成することができる。   Next, in the wiring board of the present invention, the top surface of the conductor bump can be a concave surface. That is, the wiring board of the present invention is a wiring board having conductor bumps as external connection terminals on the surface of the board, and an opening is provided in the surface insulating layer forming the surface of the board and connected to the conductor pad forming the bottom surface of the opening. The formed conductor bump is characterized in that its top surface is a concave surface. According to this, when the IC chip mounted on the wiring board is flip-chip connected, the terminal of the IC chip having a smaller diameter is fitted on the concave top surface of the conductor bump (see FIG. 2). There is an advantage that the IC chip is not easily displaced. In addition, the conductor bump has a shape that fits closely to the inner wall and the periphery of the opening (saddle shape), and the top surface is formed in a concave shape because the portion that appears on the substrate surface is larger than the opening diameter. It's easy to do. Further, the portion appearing on the substrate surface (and the top surface of the conductor bump) can be formed larger in diameter than the terminal of the IC chip without being caught by the opening diameter.

次に、本発明の配線基板では、表層絶縁層を、層間絶縁層と同じ樹脂材料で構成することができる。従来の半田ペーストを印刷する手法では、印刷後にリフローを行う必要があるため、基板表面をなす表層絶縁層は半田の溶融温度にも耐えうる特性（半田耐熱性）を有している必要がある。しかしながら、本発明のようにメッキにより導体バンプを形成する手法によれば、表層絶縁層に半田耐熱性が必要とされないため、層間絶縁層と同じ樹脂材料を用いることができる。   Next, in the wiring board of the present invention, the surface insulating layer can be made of the same resin material as the interlayer insulating layer. In the conventional method of printing a solder paste, since reflow needs to be performed after printing, the surface insulating layer forming the substrate surface needs to have characteristics (solder heat resistance) that can withstand the melting temperature of the solder. . However, according to the method of forming the conductor bumps by plating as in the present invention, the surface insulating layer does not require solder heat resistance, and therefore, the same resin material as that of the interlayer insulating layer can be used.

＜配線基板＞
本発明の配線基板の実施形態を、図面を参照しながら説明する。図１は、本発明の第１実施形態に係る配線基板１の断面構造を概略的に表す図である。なお、配線基板１は、図中で上側に表れている面を第１表面ＭＰ１とし、下側に表れている面を第２表面ＭＰ２とする。配線基板１は、ＩＣチップと主基板（マザーボード等）との間に配置されるものであり、第１表面ＭＰ１側に形成されたＣｕバンプ７には、図２に示すように、ＩＣチップがフリップチップ接続される。他方、第２表面ＭＰ２側に形成された導体パッド５７は、図示しないリードピンや半田ボール等が設置され、これを介して主基板が接続される。 <Wiring board>
An embodiment of a wiring board of the present invention will be described with reference to the drawings. FIG. 1 is a diagram schematically showing a cross-sectional structure of a wiring board 1 according to the first embodiment of the present invention. In the wiring board 1, a surface appearing on the upper side in the drawing is a first surface MP1, and a surface appearing on the lower side is a second surface MP2. The wiring board 1 is disposed between the IC chip and the main board (motherboard or the like). The Cu bump 7 formed on the first surface MP1 side has an IC chip as shown in FIG. Flip chip connected. On the other hand, the conductor pads 57 formed on the second surface MP2 side are provided with lead pins, solder balls and the like (not shown), and the main board is connected thereto.

基板コア部ＣＢは、繊維強化樹脂板（例えばガラス繊維強化エポキシ樹脂）等の樹脂板２で主に構成されており、樹脂板２には板厚方向に貫通する貫通孔２１Ａが形成され、その内壁には配線積層部Ｌ１，Ｌ２間の導通を図る貫通導体２１がＣｕメッキにより形成されている。また、貫通導体２１の内側には、無機フィラー（例えばシリカフィラー）を含むエポキシ系の樹脂からなる樹脂製穴埋め材２３が充填されており、貫通導体２１の端部にはＣｕメッキからなる蓋導体５２が形成されている。   The substrate core portion CB is mainly composed of a resin plate 2 such as a fiber reinforced resin plate (for example, a glass fiber reinforced epoxy resin), and the resin plate 2 is formed with a through hole 21A penetrating in the plate thickness direction. A through conductor 21 is formed on the inner wall by Cu plating for conducting electrical connection between the wiring laminated portions L1 and L2. The inside of the through conductor 21 is filled with a resin filler 23 made of an epoxy resin containing an inorganic filler (for example, silica filler), and the end of the through conductor 21 is a lid conductor made of Cu plating. 52 is formed.

基板コア部ＣＢの両面上に設けられた配線積層部Ｌ１，Ｌ２は、樹脂絶縁層（Ｂ１１〜Ｂ１３，ＳＲ１，Ｂ２１〜Ｂ２３，ＳＲ２）と導体層（Ｍ１１〜Ｍ１４，Ｍ２１〜Ｍ２４）とが交互に積層された構造を有する。導体層Ｍ１１〜Ｍ１４，Ｍ２１〜Ｍ２４は、Ｃｕメッキからなる配線５３や導体パッド５５，５６，５７やベタ導体５１，５４等を含むものであり、その層間はビア導体５によって層間接続がなされている。ここで、導体層Ｍ１１〜Ｍ１３，Ｍ２１〜Ｍ２３における導体パッド５５は、ビア導体５の受け皿となる導体部分である。導体層Ｍ１４における導体パッド５６は、Ｃｕバンプ７の受け皿となる導体部分である。導体層Ｍ２４における導体パッド５７は、リードピンや半田ボール（図示せず）を形成するためのものであり、その表面にはＮｉ−Ａｕメッキが施されている。   In the wiring laminated portions L1 and L2 provided on both surfaces of the substrate core portion CB, resin insulating layers (B11 to B13, SR1, B21 to B23, SR2) and conductor layers (M11 to M14, M21 to M24) are alternately arranged. Have a laminated structure. The conductor layers M11 to M14 and M21 to M24 include wiring 53 made of Cu plating, conductor pads 55, 56, 57, solid conductors 51, 54, and the like, and interlayer connection is made between the layers by via conductors 5. Yes. Here, the conductor pads 55 in the conductor layers M <b> 11 to M <b> 13 and M <b> 21 to M <b> 23 are conductor portions that serve as receptacles for the via conductor 5. The conductor pad 56 in the conductor layer M <b> 14 is a conductor portion that serves as a tray for the Cu bump 7. The conductor pads 57 in the conductor layer M24 are for forming lead pins and solder balls (not shown), and the surface thereof is Ni-Au plated.

樹脂絶縁層（層間絶縁層）Ｂ１１〜Ｂ１３，Ｂ２１〜Ｂ２３は、シリカ粉末等の無機フィラーを適宜含んだエポキシ樹脂等の熱硬化性の樹脂材料３からなり、導体層Ｍ１１〜Ｍ１４，Ｍ２１〜Ｍ２４間を絶縁するとともに、層間接続のためのビア導体５が貫通形成されている。また、導体層Ｍ１４，Ｍ２４上には、シリカ粉末等の無機フィラーを適宜含み、更にリン化合物等の難燃剤などを含んだエポキシ樹脂等の感光性の樹脂材料４からなるソルダーレジスト層（表層絶縁層）ＳＲ１，ＳＲ２が形成され、導体パッド５６，５７を露出させるための開口６Ａ，８Ａが穿設されている。   The resin insulating layers (interlayer insulating layers) B11 to B13, B21 to B23 are made of a thermosetting resin material 3 such as an epoxy resin appropriately including an inorganic filler such as silica powder, and the conductor layers M11 to M14 and M21 to M24. A via conductor 5 is formed through the insulating layer for interlayer connection. Further, on the conductor layers M14 and M24, a solder resist layer (surface layer insulation) made of a photosensitive resin material 4 such as an epoxy resin containing an inorganic filler such as silica powder as appropriate and further containing a flame retardant such as a phosphorus compound. Layers) SR1 and SR2 are formed, and openings 6A and 8A for exposing the conductor pads 56 and 57 are formed.

Ｃｕバンプ７は、Ｃｕメッキからなり、導体パッド５６に接続されてなるとともに、ソルダーレジスト層ＳＲ１の開口６Ａの内壁６１および周縁６２に密着する鉤型の形状とされている。すなわち、Ｃｕバンプ７は、層間接続のためのビア導体５と同様の形状を為しており、導体パッド５６に接続された開口６Ａ内に存在する部分７５と、当該部分７５よりも径大の第１表面ＭＰ１上に表れた部分７３とを有する。また、Ｃｕバンプ７は、その間隔（中心間隔）が例えば１５０μｍ以下とされている。   The Cu bump 7 is made of Cu plating, is connected to the conductor pad 56, and has a bowl shape that is in close contact with the inner wall 61 and the peripheral edge 62 of the opening 6A of the solder resist layer SR1. That is, the Cu bump 7 has the same shape as the via conductor 5 for interlayer connection, and has a portion 75 present in the opening 6A connected to the conductor pad 56 and a diameter larger than that of the portion 75. And a portion 73 appearing on the first surface MP1. Further, the Cu bump 7 has an interval (center interval) of, for example, 150 μm or less.

また、Ｃｕバンプ７は、図２に示すように、ＩＣチップをフリップチップ接続しやすいよう、第１表面ＭＰ１上に表れた部分７３（Ｃｕバンプ７の頂面７１）がＩＣチップの端子Ｔよりも径大に形成されている。さらに、この頂面７１は凹曲面とされ、ＩＣチップがフリップチップ接続されると、凹面状の頂面７１に端子Ｔが嵌って位置ズレが防止される。なお、Ｃｕバンプ７の頂面７１は、図１および２に示したような凹曲面に限らず、図３の（Ｃ）に示した平坦面や（Ｄ）に示した凸曲面とすることもでき、これにより端子Ｔとの接触面積を向上させることができる。   Further, as shown in FIG. 2, the Cu bump 7 has a portion 73 (the top surface 71 of the Cu bump 7) appearing on the first surface MP1 from the terminal T of the IC chip so that the IC chip can be easily flip-chip connected. Is also formed in a large diameter. Further, the top surface 71 is a concave curved surface, and when the IC chip is flip-chip connected, the terminal T fits into the concave top surface 71 to prevent displacement. The top surface 71 of the Cu bump 7 is not limited to the concave curved surface as shown in FIGS. 1 and 2, but may be a flat surface shown in FIG. 3C or a convex curved surface shown in FIG. Thus, the contact area with the terminal T can be improved.

また、Ｃｕバンプ７は、第１表面ＭＰ１上に表れた部分７３の高さが開口６Ａの径に対して１／１０以上１／２以下程度とすることができる。例えば、開口６Ａの径を８０〜１００μｍ、第１表面ＭＰ１上に表れた部分７３の高さを１０〜５０μｍとすることができる。この範囲とすることで、上述の如く、良好にＩＣチップをフリップチップ接続することができる。   Further, in the Cu bump 7, the height of the portion 73 appearing on the first surface MP1 can be set to about 1/10 or more and 1/2 or less with respect to the diameter of the opening 6A. For example, the diameter of the opening 6A can be set to 80 to 100 μm, and the height of the portion 73 appearing on the first surface MP1 can be set to 10 to 50 μm. By setting this range, the IC chip can be flip-chip connected satisfactorily as described above.

また、Ｃｕバンプ７は、第１表面ＭＰ１上に表れた部分７３の開口６Ａ端からの張り出し長さを、近接する開口間隔の１／３以下、より好ましくは１／４以下とすることができる。また、隣接するＣｕバンプ７の間隔は、隣接する開口６Ａの間隔の半分以上とすることができる。これらを越えると、隣接するＣｕバンプ７同士が短絡を起こす惧れがある。   Further, the Cu bump 7 can have a protruding length from the end of the opening 6A of the portion 73 appearing on the first surface MP1 to be 1/3 or less, more preferably 1/4 or less of the adjacent opening interval. . Further, the interval between the adjacent Cu bumps 7 can be set to half or more of the interval between the adjacent openings 6A. Exceeding these may cause a short circuit between adjacent Cu bumps 7.

＜配線基板の製造方法＞
本発明の配線基板の製造方法の実施形態を、図面を参照しながら説明する。
配線基板１は、基板コア部ＣＢの両面上に、樹脂絶縁層（Ｂ１１〜Ｂ１３，ＳＲ１，Ｂ２１〜Ｂ２３，ＳＲ２）と、導体層（Ｍ１１〜Ｍ１４，Ｍ２１〜Ｍ２４）とを交互に積層して配線積層部Ｌ１，Ｌ２を形成することによって得られる。これは、公知のビルドアップ工程（セミアディティブ法，フィルム状樹脂材料のラミネート形成技術，フォトリソグラフィー技術などを組み合わせた工程）を用いることで実現できる。また、基板コア部ＣＢは、ガラス繊維２８により強化されたエポキシ樹脂からなる樹脂板２に、ドリル加工により板厚方向に貫通する貫通孔２１Ａを形成し、その内壁を覆う貫通導体２１をＣｕメッキにより形成し、その内側に穴埋め材２３を充填することで得られる。 <Manufacturing method of wiring board>
An embodiment of a method for manufacturing a wiring board according to the present invention will be described with reference to the drawings.
The wiring board 1 is formed by alternately laminating resin insulating layers (B11 to B13, SR1, B21 to B23, SR2) and conductor layers (M11 to M14, M21 to M24) on both surfaces of the substrate core portion CB. It is obtained by forming the wiring laminated portions L1 and L2. This can be realized by using a known build-up process (a process that combines a semi-additive process, a film-form resin material laminate formation technique, a photolithography technique, etc.). Further, the substrate core portion CB is formed with a through hole 21A penetrating in the thickness direction by drilling in the resin plate 2 made of an epoxy resin reinforced with glass fibers 28, and the through conductor 21 covering the inner wall is plated with Cu. It is obtained by filling the hole filling material 23 inside.

図７および図８は、配線基板１のうち配線積層部Ｌ１，Ｌ２を製造する際の最終段階、すなわちソルダーレジスト層ＳＲ１を形成してＣｕバンプ７を形成する工程の工程図である。工程１の前において、層間絶縁層Ｂ１３上には導体パッド５６が形成されている。   7 and 8 are process diagrams of the final stage when manufacturing the wiring laminated portions L1 and L2 of the wiring substrate 1, that is, the process of forming the Cu bumps 7 by forming the solder resist layer SR1. Prior to step 1, a conductor pad 56 is formed on the interlayer insulating layer B13.

まず、工程１（Ｃｕ粗化工程）では、導体パッド５６に対し、後に形成する樹脂材料４との密着性を向上させるため、Ｃｕ粗化処理（公知のマイクロエッチング法や黒化処理等）を施す。工程２（表層絶縁層形成工程）では、導体パッド５６を覆うようにソルダーレジスト層ＳＲ１（樹脂材料４からなる層）をラミネート形成する。この際、導体パッド５６の表面は、Ｃｕ粗化処理が施されているので、ソルダーレジスト層ＳＲ１との密着性が良好である。なお、後述するように、ＣｕメッキによってＣｕバンプ７が形成されることから、第１表面ＭＰ１をなす表層絶縁層には、従来の半田リフローを必要とするペースト印刷の手法の場合に必要とされていた半田耐熱性が要求されない。しかし、第２表面ＭＰ２側の表層絶縁層には、開口８Ａに露出する導体パッド５７にリードピン（半田で固着）や半田ボールを設置するため、半田耐熱性が要求される。このため、第２表面ＭＰ２をなす表層絶縁層を、半田耐熱性を有する樹脂材料４からなるソルダーレジスト層ＳＲ２とし、これと併せて、第１表面ＭＰ１をなす表層絶縁層も同じ樹脂材料４からなるソルダーレジスト層ＳＲ１として構成すれば、両者ＳＲ１，ＳＲ２を一括して形成することができるので、工程が簡易となる。   First, in Step 1 (Cu roughening step), Cu roughening treatment (a known microetching method, blackening treatment, etc.) is performed on the conductor pad 56 in order to improve adhesion to the resin material 4 to be formed later. Apply. In step 2 (surface insulating layer forming step), a solder resist layer SR1 (a layer made of the resin material 4) is laminated so as to cover the conductor pads 56. At this time, since the surface of the conductor pad 56 has been subjected to Cu roughening treatment, the adhesiveness with the solder resist layer SR1 is good. As will be described later, since the Cu bumps 7 are formed by Cu plating, the surface insulating layer forming the first surface MP1 is required in the case of a conventional paste printing method that requires solder reflow. The required solder heat resistance is not required. However, the surface insulating layer on the second surface MP2 side is required to have solder heat resistance because lead pins (fixed with solder) and solder balls are placed on the conductor pads 57 exposed in the openings 8A. For this reason, the surface insulating layer forming the second surface MP2 is a solder resist layer SR2 made of the resin material 4 having solder heat resistance, and the surface insulating layer forming the first surface MP1 is also made of the same resin material 4 together with this. If the solder resist layer SR1 is formed, both SR1 and SR2 can be formed at a time, so that the process becomes simple.

次に、工程３（開口穿設工程）では、いわゆるフォトビアプロセスによる加工によって、ソルダーレジスト層ＳＲ１に開口６Ａを穿設する。これにより、開口６Ａの底面には導体パッド５６が露出する。工程４（樹脂粗化工程）では、後にメッキにより形成されるＣｕバンプ７との密着性を向上させるために、過マンガン酸カリウム等を用いて、開口６Ａの内壁６１や周縁６２を含むソルダーレジスト層ＳＲ１の表面に粗化処理を施す。   Next, in step 3 (opening drilling step), the opening 6A is drilled in the solder resist layer SR1 by processing by a so-called photo via process. As a result, the conductor pad 56 is exposed on the bottom surface of the opening 6A. In step 4 (resin roughening step), a solder resist including the inner wall 61 and the peripheral edge 62 of the opening 6A is used by using potassium permanganate or the like in order to improve the adhesion to the Cu bump 7 formed later by plating. A roughening process is performed on the surface of the layer SR1.

次に、工程５（バンプ形成工程）では、開口６Ａ内（導体バンプ５６，内壁６１）およびその周縁６２を露出させるようパターンニングされたメッキレジストＭＳをマスクとして、その露出部分にＣｕメッキを施してＣｕバンプ７を形成する。具体的には、５−１（無電解メッキ），５−２（マスク形成），５−３（電解メッキ）等の手順によってＣｕバンプ７を形成する。まず５−１（無電解メッキ）では、開口６Ａ内（導体バンプ５６，内壁６１）も含むソルダーレジスト層ＳＲ１の表面全体に対し、Ｐｄ触媒の付与後、硫酸銅系の無電解Ｃｕメッキ液を用いて無電解Ｃｕメッキを施すことにより、無電解Ｃｕメッキ層７７を形成する。５−２（マスク形成）では、開口６Ａおよびその周縁６２を除く位置にメッキレジストＭＳを形成する。これは、感光性レジストを露光・現像し、開口６Ａおよびその周縁６２上に当たる部分を除去することによって、これらを露出させるようなパターンを得ることができる。   Next, in step 5 (bump formation step), the exposed portion is subjected to Cu plating using the plating resist MS patterned to expose the inside of the opening 6A (conductor bump 56, inner wall 61) and its peripheral edge 62 as a mask. Cu bumps 7 are formed. Specifically, the Cu bumps 7 are formed by procedures such as 5-1 (electroless plating), 5-2 (mask formation), and 5-3 (electrolytic plating). First, in 5-1 (electroless plating), a copper sulfate-based electroless Cu plating solution is applied to the entire surface of the solder resist layer SR1 including the inside of the opening 6A (conductor bump 56, inner wall 61) after applying a Pd catalyst. The electroless Cu plating layer 77 is formed by applying electroless Cu plating. In 5-2 (mask formation), a plating resist MS is formed at a position excluding the opening 6A and the peripheral edge 62 thereof. This can be obtained by exposing and developing the photosensitive resist and removing the portions of the openings 6A and the peripheral edge 62 that are exposed, thereby exposing the patterns.

続いて、５−３（電解メッキ）では、無電解Ｃｕメッキ層７７を下地として電解Ｃｕメッキを施して電解Ｃｕメッキ層７８を形成し、無電解Ｃｕメッキ層７７と電解Ｃｕメッキ層７８からなるＣｕバンプ７を露出部分（開口６Ａおよびその周縁６２）に形成する。ここで、Ｃｕバンプ７の頂面７１は、電解Ｃｕメッキ層７８の形成時においてその形状を制御することができる。例えば、図３（Ａ）に示すように、メッキレジストＭＳの厚さや電解Ｃｕメッキ層７８の形成厚さ等の関係によって、Ｃｕバンプ７の頂面７１は、凹面状（図３（Ｂ）），平坦状（図３（Ｃ）），凸面状（図３（Ｄ））と変化する。例えば、電解Ｃｕメッキ層７８の形成厚さがメッキレジストＭＳの厚さよりも不足する場合には、Ｃｕバンプ７の頂面７１は開口６Ａの形状に倣って凹面状となり易く、他方、電解Ｃｕメッキ層７８の形成厚さが増加すると、かかる凹面状の部分が埋まり、平坦状や凸面状となり易い。   Subsequently, in 5-3 (electrolytic plating), electrolytic Cu plating is performed using the electroless Cu plating layer 77 as a base to form an electrolytic Cu plating layer 78, and the electroless Cu plating layer 77 and the electrolytic Cu plating layer 78 are formed. A Cu bump 7 is formed on the exposed portion (opening 6A and its peripheral edge 62). Here, the shape of the top surface 71 of the Cu bump 7 can be controlled when the electrolytic Cu plating layer 78 is formed. For example, as shown in FIG. 3A, the top surface 71 of the Cu bump 7 has a concave shape (FIG. 3B) depending on the thickness of the plating resist MS, the formation thickness of the electrolytic Cu plating layer 78, and the like. , Flat shape (FIG. 3C), convex shape (FIG. 3D). For example, when the formation thickness of the electrolytic Cu plating layer 78 is less than the thickness of the plating resist MS, the top surface 71 of the Cu bump 7 tends to be concave following the shape of the opening 6A, while the electrolytic Cu plating is performed. When the formation thickness of the layer 78 is increased, such a concave portion is filled, and the layer 78 is likely to be flat or convex.

電解Ｃｕメッキ層７８の形成後は、メッキレジストＭＳを除去し、クイックエッチングによりメッキレジストＭＳの下部に存在していた無電解Ｃｕメッキ層７７を除去することでＣｕバンプ７が得られる。その後、電気的検査，外観検査等の所定の検査を経て、配線基板１が完成する。   After the formation of the electrolytic Cu plating layer 78, the plating resist MS is removed, and the Cu bump 7 is obtained by removing the electroless Cu plating layer 77 existing under the plating resist MS by quick etching. Thereafter, the wiring board 1 is completed through predetermined inspections such as electrical inspection and appearance inspection.

＜他の実施形態＞
以下、本発明の他の実施形態を、図面を参照しながら説明する。なお、上述の第１実施形態と重複する箇所については、同番号を付して説明を省略する。 <Other embodiments>
Hereinafter, other embodiments of the present invention will be described with reference to the drawings. In addition, about the location which overlaps with the above-mentioned 1st Embodiment, the same number is attached | subjected and description is abbreviate | omitted.

図４は、第２実施形態の配線基板１Ｂの断面構造を概略的に表す図である。配線基板１Ｂは、第１表面ＭＰ１をなす表層絶縁層に、層間絶縁層Ｂ１１〜Ｂ１３，Ｂ２１〜２３と同じ樹脂材料３を用いた絶縁層Ｂ１４を用いている。これは、ＣｕメッキによってＣｕバンプ７が形成されることから、第１表面ＭＰ１をなす表層絶縁層には、従来の半田リフローを必要とするペースト印刷の手法の場合に必要とされていた半田耐熱性が要求されないことによる。なお、本実施形態では、第２表面ＭＰ２をなす表層絶縁層も、樹脂材料３を用いた絶縁層Ｂ２４とされている。この場合、絶縁層Ｂ１４，Ｂ２４を一括して形成することができるので、工程が簡易である。   FIG. 4 is a diagram schematically showing a cross-sectional structure of the wiring board 1B of the second embodiment. In the wiring board 1B, an insulating layer B14 using the same resin material 3 as the interlayer insulating layers B11 to B13 and B21 to 23 is used for the surface insulating layer forming the first surface MP1. This is because the Cu bumps 7 are formed by Cu plating, so that the surface heat insulating layer forming the first surface MP1 has a solder heat resistance that has been required in the case of a conventional paste printing method that requires solder reflow. This is because sex is not required. In the present embodiment, the surface insulating layer forming the second surface MP2 is also the insulating layer B24 using the resin material 3. In this case, since the insulating layers B14 and B24 can be formed at once, the process is simple.

図５は、第３実施形態の配線基板１Ｃの断面構造を概略的に表す図である。配線基板１Ｃは、第１表面ＭＰ１をなす表層絶縁層に、層間絶縁層Ｂ１１〜Ｂ１３，Ｂ２１〜２３と同じ樹脂材料３を用いた絶縁層Ｂ１４を用いる一方で、第２表面ＭＰ２をなす表層絶縁層に、半田耐熱性を有する樹脂材料４からなるソルダーレジスト層ＳＲ２を用いている。これは、絶縁層Ｂ１４とソルダーレジスト層ＳＲ２を順に形成することで得られる。これによれば、第１表面ＭＰ１をなす表層絶縁層を、層間絶縁層Ｂ１１〜Ｂ１３，Ｂ２１〜２３と同じ樹脂材料３を用いることができる一方で、第２表面ＭＰ２をなす表層絶縁層に半田耐熱性を有する樹脂材料４を用いるため、リードピン（半田で固着）や半田ボールを良好に設置できる。   FIG. 5 is a diagram schematically illustrating a cross-sectional structure of the wiring board 1 </ b> C of the third embodiment. The wiring substrate 1C uses the insulating layer B14 using the same resin material 3 as the interlayer insulating layers B11 to B13 and B21 to 23 as the surface insulating layer that forms the first surface MP1, while the surface insulating layer that forms the second surface MP2. The solder resist layer SR2 made of the resin material 4 having solder heat resistance is used for the layer. This is obtained by sequentially forming the insulating layer B14 and the solder resist layer SR2. According to this, the surface layer insulating layer forming the first surface MP1 can be made of the same resin material 3 as the interlayer insulating layers B11 to B13 and B21 to 23, while being soldered to the surface layer insulating layer forming the second surface MP2. Since the resin material 4 having heat resistance is used, lead pins (fixed with solder) and solder balls can be satisfactorily installed.

図６は、上記Ｃｕバンプ７に代えて半田メッキバンプ７Ｈを形成した第４実施形態の配線基板１Ｄの要部拡大図である。半田メッキバンプ７Ｈを形成する場合も同様に、半田ペーストの印刷による場合と比較して、バンプの微小化が実現する。これに限らず、他の金属メッキも同様に導体バンプとして適用できる。また、半田メッキバンプ７Ｈと導体パッド５６との間には、Ｎｉメッキ層７９が介挿されており、両者の密着性を向上させている。   FIG. 6 is an enlarged view of a main part of a wiring board 1D of the fourth embodiment in which solder plating bumps 7H are formed instead of the Cu bumps 7. Similarly, when the solder plating bump 7H is formed, the size of the bump can be reduced as compared with the case where the solder paste is printed. Not only this but other metal plating can be similarly applied as a conductor bump. Further, a Ni plating layer 79 is interposed between the solder plating bump 7H and the conductor pad 56, thereby improving the adhesion between them.

以上、本発明の実施形態について説明したが、本発明はこれらの形式に限定されるものではなく、これらに具現された発明と同一性の範囲内において適宜変更して実施し得る。   As mentioned above, although embodiment of this invention was described, this invention is not limited to these forms, In the range of the same identity as the invention embodied in these, it can change suitably and can implement.

本発明の配線基板（第１実施形態）の断面構造を概略的に表す図The figure which represents roughly the cross-section of the wiring board (1st Embodiment) of this invention 導体バンプにＩＣチップがフリップ接続された状態を表す図The figure showing the state where the IC chip is flip-connected to the conductor bump 導体バンプの形状についての説明図Illustration of conductor bump shape 本発明の配線基板（第２実施形態）の断面構造を概略的に表す図The figure which represents roughly the cross-section of the wiring board (2nd Embodiment) of this invention 本発明の配線基板（第３実施形態）の断面構造を概略的に表す図The figure which represents roughly the cross-section of the wiring board (3rd Embodiment) of this invention 導体バンプの第１変形例First modification of conductor bump 本発明の配線基板の製造方法を表す工程図Process drawing showing the manufacturing method of the wiring board of this invention 図８に続く図Figure following Figure 8

符号の説明Explanation of symbols

１ 配線基板
５６ 導体パッド
６Ａ 開口
６１ 開口の内壁
６２ 開口の周縁
７ 導体バンプ
７１ 導体バンプの頂面
ＳＲ 表層絶縁層
Ｂ 層間絶縁層
ＭＰ 基板表面
ＭＳ メッキレジスト
DESCRIPTION OF SYMBOLS 1 Wiring board 56 Conductor pad 6A Opening 61 Opening inner wall 62 Opening periphery 7 Conductive bump 71 Conductive bump top surface SR Surface insulating layer B Interlayer insulating layer MP Substrate surface MS Plating resist

Claims (7)

基板表面に外部接続端子としての導体バンプを有する配線基板であって、基板表面をなす表層絶縁層に開口が設けられ、当該開口の底面をなす導体パッドに接続された前記導体バンプが、メッキによって前記開口の内壁および周縁に密着して形成されてなることを特徴とする配線基板。   A wiring board having conductor bumps as external connection terminals on the substrate surface, wherein an opening is provided in a surface insulating layer forming the substrate surface, and the conductor bump connected to the conductor pad forming the bottom surface of the opening is formed by plating. A wiring board characterized by being formed in close contact with an inner wall and a peripheral edge of the opening. 前記導体パッドとそれに接続された前記導体バンプとがＣｕメッキにより形成されてなる請求項１に記載の配線基板。   The wiring board according to claim 1, wherein the conductor pad and the conductor bump connected to the conductor pad are formed by Cu plating. 前記導体バンプは、その頂面が凹面とされてなる請求項１または２に記載の配線基板。   The wiring board according to claim 1, wherein a top surface of the conductor bump is a concave surface. 前記表層絶縁層は、層間絶縁層と同じ樹脂材料で構成されてなる請求項１ないし３のいずれか１項に記載の配線基板。   The wiring substrate according to any one of claims 1 to 3, wherein the surface insulating layer is made of the same resin material as that of the interlayer insulating layer. 前記導体バンプは、基板表面上に表れた部分が柱状に形成されてなる請求項１ないし４のいずれか１項に記載の配線基板。   The wiring board according to any one of claims 1 to 4, wherein the conductor bump is formed in a columnar shape on a surface of the board. 基板表面に外部接続端子としての導体バンプを有する配線基板であって、基板表面をなす表層絶縁層に開口が設けられ、当該開口の底面をなす導体パッドに接続された前記導体バンプは、その頂面が凹面とされてなることを特徴とする配線基板。   A wiring board having conductor bumps as external connection terminals on a substrate surface, wherein an opening is provided in a surface insulating layer forming the substrate surface, and the conductor bump connected to the conductor pad forming the bottom surface of the opening has a top. A wiring board having a concave surface. 基板表面に外部接続端子としての導体バンプを有する配線基板の製造方法であって、基板表面をなす表層絶縁層に開口を穿設して、当該開口の底面に導体パッドを露出させる開口穿設工程と、前記開口内およびその周縁を露出させるようパターンニングされたメッキレジストをマスクとして、その露出部分にメッキを施して前記導体バンプを形成するバンプ形成工程と、を備えることを特徴とする配線基板の製造方法。
A method of manufacturing a wiring board having conductor bumps as external connection terminals on a substrate surface, wherein an opening is made in a surface insulating layer forming the substrate surface, and a conductor pad is exposed on a bottom surface of the opening. And a bump forming step of forming the conductor bump by plating the exposed portion using a plating resist patterned so as to expose the inside and the periphery of the opening as a mask. Manufacturing method.
JP2005295477A 2005-10-07 2005-10-07 Wiring board and method of manufacturing the same Expired - Fee Related JP4769056B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005295477A JP4769056B2 (en) 2005-10-07 2005-10-07 Wiring board and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005295477A JP4769056B2 (en) 2005-10-07 2005-10-07 Wiring board and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JP2007103878A true JP2007103878A (en) 2007-04-19
JP4769056B2 JP4769056B2 (en) 2011-09-07

Family

ID=38030481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005295477A Expired - Fee Related JP4769056B2 (en) 2005-10-07 2005-10-07 Wiring board and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP4769056B2 (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009004744A (en) * 2007-06-20 2009-01-08 Samsung Electro Mech Co Ltd Printed-circuit board
JP2009117721A (en) * 2007-11-08 2009-05-28 Mitsui Mining & Smelting Co Ltd Wiring board, circuit board and method of manufacturing the same
JP2012129368A (en) * 2010-12-15 2012-07-05 Ngk Spark Plug Co Ltd Wiring board and manufacturing method of the same
JP2012169591A (en) * 2011-01-24 2012-09-06 Ngk Spark Plug Co Ltd Multilayer wiring board
US9334576B2 (en) 2014-02-24 2016-05-10 Shinko Electric Industries Co., Ltd. Wiring substrate and method of manufacturing wiring substrate
US9431333B2 (en) 2014-07-04 2016-08-30 Shinko Electric Industries Co., Ltd. Wiring substrate
JP2017011013A (en) * 2015-06-18 2017-01-12 日本特殊陶業株式会社 Wiring board for inspection, and manufacturing method of wiring board for inspection
US9966331B2 (en) 2015-03-20 2018-05-08 Shinko Electric Industries Co., Ltd. Wiring substrate and semiconductor device
US10129980B2 (en) 2016-05-24 2018-11-13 Shinko Electric Industries Co., Ltd. Circuit board and electronic component device
US10643934B2 (en) 2018-01-17 2020-05-05 Shinko Electric Industries Co., Ltd. Wiring substrate and electronic component device
US11121107B2 (en) 2018-04-02 2021-09-14 Shinko Electric Industries Co., Ltd. Interconnect substrate having columnar electrodes
US11211326B2 (en) 2019-06-26 2021-12-28 Shinko Electric Industries Co., Ltd. Wiring substrate and manufacturing method thereof

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05144815A (en) * 1991-11-25 1993-06-11 Ibiden Co Ltd Substrate for mounting of electronic part with bump
JPH07221101A (en) * 1994-02-02 1995-08-18 Hitachi Ltd Formation of bump electrode on semiconductor wafer
JPH10224013A (en) * 1997-02-12 1998-08-21 Nippon Mektron Ltd Production of circuit board
JPH10322032A (en) * 1997-05-23 1998-12-04 Kyocera Corp Manufacture of multilayered wiring board
JPH10326965A (en) * 1997-05-23 1998-12-08 Kyocera Corp Manufacture of multilayered wiring board
JP2003142513A (en) * 2001-10-31 2003-05-16 Seiko Epson Corp Method of forming bump, flip chip, semiconductor device, their manufacturing methods, circuit board, and electronic equipment
JP2004119464A (en) * 2002-09-24 2004-04-15 Kyocera Corp Wiring board with solder bump and method for manufacturing same
JP2004158701A (en) * 2002-11-07 2004-06-03 Seiko Epson Corp Bump structure for mounting element chip and method for forming the same
JP2005123247A (en) * 2003-10-14 2005-05-12 Seiko Epson Corp Semiconductor device and its manufacturing method

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05144815A (en) * 1991-11-25 1993-06-11 Ibiden Co Ltd Substrate for mounting of electronic part with bump
JPH07221101A (en) * 1994-02-02 1995-08-18 Hitachi Ltd Formation of bump electrode on semiconductor wafer
JPH10224013A (en) * 1997-02-12 1998-08-21 Nippon Mektron Ltd Production of circuit board
JPH10322032A (en) * 1997-05-23 1998-12-04 Kyocera Corp Manufacture of multilayered wiring board
JPH10326965A (en) * 1997-05-23 1998-12-08 Kyocera Corp Manufacture of multilayered wiring board
JP2003142513A (en) * 2001-10-31 2003-05-16 Seiko Epson Corp Method of forming bump, flip chip, semiconductor device, their manufacturing methods, circuit board, and electronic equipment
JP2004119464A (en) * 2002-09-24 2004-04-15 Kyocera Corp Wiring board with solder bump and method for manufacturing same
JP2004158701A (en) * 2002-11-07 2004-06-03 Seiko Epson Corp Bump structure for mounting element chip and method for forming the same
JP2005123247A (en) * 2003-10-14 2005-05-12 Seiko Epson Corp Semiconductor device and its manufacturing method

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009004744A (en) * 2007-06-20 2009-01-08 Samsung Electro Mech Co Ltd Printed-circuit board
US8080741B2 (en) 2007-06-20 2011-12-20 Samsung Electro-Mechanics Co., Ltd. Printed circuit board
JP2009117721A (en) * 2007-11-08 2009-05-28 Mitsui Mining & Smelting Co Ltd Wiring board, circuit board and method of manufacturing the same
TWI477218B (en) * 2007-11-08 2015-03-11 Chipbond Technology Corp Wiring board, circuit board, and manufacturing thereof
JP2012129368A (en) * 2010-12-15 2012-07-05 Ngk Spark Plug Co Ltd Wiring board and manufacturing method of the same
US8785786B2 (en) 2010-12-15 2014-07-22 Ngk Spark Plug Co., Ltd. Wiring board and method of manufacturing the same
JP2012169591A (en) * 2011-01-24 2012-09-06 Ngk Spark Plug Co Ltd Multilayer wiring board
US9334576B2 (en) 2014-02-24 2016-05-10 Shinko Electric Industries Co., Ltd. Wiring substrate and method of manufacturing wiring substrate
US9431333B2 (en) 2014-07-04 2016-08-30 Shinko Electric Industries Co., Ltd. Wiring substrate
US9966331B2 (en) 2015-03-20 2018-05-08 Shinko Electric Industries Co., Ltd. Wiring substrate and semiconductor device
JP2017011013A (en) * 2015-06-18 2017-01-12 日本特殊陶業株式会社 Wiring board for inspection, and manufacturing method of wiring board for inspection
US10129980B2 (en) 2016-05-24 2018-11-13 Shinko Electric Industries Co., Ltd. Circuit board and electronic component device
US10643934B2 (en) 2018-01-17 2020-05-05 Shinko Electric Industries Co., Ltd. Wiring substrate and electronic component device
US11121107B2 (en) 2018-04-02 2021-09-14 Shinko Electric Industries Co., Ltd. Interconnect substrate having columnar electrodes
US11211326B2 (en) 2019-06-26 2021-12-28 Shinko Electric Industries Co., Ltd. Wiring substrate and manufacturing method thereof
US11574866B2 (en) 2019-06-26 2023-02-07 Shinko Electric Industries Co., Ltd. Wiring substrate and manufacturing method thereof

Also Published As

Publication number Publication date
JP4769056B2 (en) 2011-09-07

Similar Documents

Publication Publication Date Title
JP4769056B2 (en) Wiring board and method of manufacturing the same
JP3865989B2 (en) Multilayer wiring board, wiring board, multilayer wiring board manufacturing method, wiring board manufacturing method, and semiconductor device
JP5101169B2 (en) Wiring board and manufacturing method thereof
US9485853B2 (en) Wiring substrate having a plurality of connection terminals and a filling member provided therebetween
KR20120029311A (en) Package substrate unit and method for manufacturing package substrate unit
JP6210777B2 (en) Bump structure, wiring board, semiconductor device, and bump structure manufacturing method
JP2006196860A (en) Semiconductor package and method of fabricating it
JP2010251552A (en) Wiring substrate, semiconductor package, and method of manufacturing them
JP2007318098A (en) Circuit arrangement and manufacturing method thereof
JP2010135721A (en) Printed circuit board comprising metal bump and method of manufacturing the same
US8754336B2 (en) Wiring board and method of producing the same
JP2009277916A (en) Wiring board, manufacturing method thereof, and semiconductor package
JP2017163027A (en) Wiring board, semiconductor device, and manufacturing method for wiring board
US8053886B2 (en) Semiconductor package and manufacturing method thereof
JP2015050343A (en) Wiring board, semiconductor device and wiring board manufacturing method
JP2009267149A (en) Part built-in wiring board, and method for manufacturing part built-in wiring board
JP2012129501A (en) Printed wiring board
US11171081B2 (en) Wiring substrate, semiconductor package and method of manufacturing wiring substrate
TWI393229B (en) Packing substrate and method for manufacturing the same
JP2016111297A (en) Wiring board, semiconductor device, and method of manufacturing wiring board
JP2006134914A (en) Module with built-in electronic part
JP4429435B2 (en) Bumped double-layer circuit tape carrier and manufacturing method thereof
JP3874669B2 (en) Wiring board manufacturing method
JP5913055B2 (en) Wiring board
JP2017045923A (en) Printed wiring board with bump, and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080829

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110221

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110309

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110502

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110524

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110617

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140624

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140624

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees