CN111128913A - Flip-chip welding packaging structure and method thereof - Google Patents
Flip-chip welding packaging structure and method thereof Download PDFInfo
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- CN111128913A CN111128913A CN201911353667.9A CN201911353667A CN111128913A CN 111128913 A CN111128913 A CN 111128913A CN 201911353667 A CN201911353667 A CN 201911353667A CN 111128913 A CN111128913 A CN 111128913A
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- Prior art keywords
- chip
- micro
- blind hole
- conductive column
- tin
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 28
- 238000003466 welding Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 229910000679 solder Inorganic materials 0.000 claims abstract description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052802 copper Inorganic materials 0.000 claims abstract description 13
- 239000010949 copper Substances 0.000 claims abstract description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 6
- 238000005459 micromachining Methods 0.000 claims description 6
- 229910018082 Cu3Sn Inorganic materials 0.000 claims description 5
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 4
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 claims description 4
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000005476 soldering Methods 0.000 claims description 4
- 229910000969 tin-silver-copper Inorganic materials 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000009736 wetting Methods 0.000 abstract description 4
- 238000003672 processing method Methods 0.000 abstract description 2
- 230000004907 flux Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
The invention relates to a flip-chip welding packaging structure of a chip, which comprises the chip, a plastic package, a welding flux and a substrate; the bottom surface of the chip is provided with a micro-bump formed by solder, and the micro-bump is provided with a blind hole; the substrate is provided with a copper column, the conductive column is inserted in the blind hole, and the inner diameter of the conductive column is matched with the outer diameter of the blind hole; and the chip and the micro bumps are wrapped by plastic package. The invention solves the problems of difficult alignment, poor wetting, easy dislocation, low connection strength and the like in the flip chip welding of the prior chip by utilizing the traditional semiconductor processing method, and has the advantages of simple process, easy operation and the like.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a flip chip bonding packaging structure and a method thereof.
Background
As integrated circuits become more powerful, higher in performance and integration, and new types of integrated circuits emerge, packaging technology plays an increasingly important role in integrated circuits, accounting for an increasing proportion of the value of the entire electronic system. Meanwhile, as the feature size of the integrated circuit reaches the nanometer level, the transistor is developed to a higher density and a higher clock frequency, and the package is also developed to a higher density. With ever increasing packaging density, narrow pitch electrical interconnections from chip to chip or chip to package substrate and their reliability have become challenging. The copper pillar bump flip interconnection technology is becoming a key technology of narrow-pitch interconnection of next-generation chips due to good electrical performance and electromigration resistance.
However, the bump has a small size and a small contact area with the substrate pad, so that the bump and the pad are not easily aligned, the wetting is not good, the soldering is easy to dislocate, the connection strength is not high, and the like. The flip chip bonding efficiency and performance are severely reduced.
In view of the above, a package structure and a package method with simple process, easy alignment and high package strength are provided.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the problems that the existing flip-chip welding process is not easy to align, is not good in wetting, is easy to misplace during welding, is not high in connection strength and the like are solved.
The technical scheme is as follows:
the invention provides a flip chip welding packaging structure of a chip, which comprises a chip (1), a plastic package (6), a solder and a substrate (4);
the bottom surface of the chip is provided with a micro-bump formed by solder, and the micro-bump is provided with a blind hole;
the substrate is provided with a copper column (5), the conductive column is inserted in the blind hole, and the inner diameter of the conductive column is matched with the outer diameter of the blind hole;
and the chip and the micro bumps are wrapped by plastic package.
Further, the micro-bumps are formed by micro-machining, preferably, by laser micro-machining.
Furthermore, the micro-bumps are made of solder. Preferably, the solder material is tin, tin-silver alloy or tin-silver-copper alloy.
Further, the micro-bumps are configured as spheres or cubes.
Further, the conductive column is a copper column, or the conductive column is a cylinder or a prism.
The flip chip bonding packaging method of the chip comprises the following steps:
constructing a micro-bump on the bottom surface of a chip by adopting a micro-processing technology, and processing a blind hole on the micro-bump; forming a conductive column (5) on a bonding pad of the substrate;
step two, attaching the chip to the substrate so that the conductive column is inserted into the blind hole;
thirdly, performing diffusion welding, preferably reflow welding, on the conductive posts and the blind holes;
and step four, wrapping the chip with a plastic package material after welding is finished, and packaging the chip on the substrate.
Further, the micro-processing technology is laser, electroplating, sputtering or vapor deposition technology.
Furthermore, a plurality of blind holes are formed on each micro bump, and each blind hole is inserted with one conductive column.
Furthermore, the conductive column is a copper column, the micro-bumps are tin or tin-based solder, and the tin or tin-based solder is fully reacted to generate Cu3Sn in the reflow soldering. The Cu3Sn has higher strength and higher melting point, so that the welding point has higher strength, and the phenomenon that the welding point melts back in the subsequent re-reflow process can be prevented.
The invention has the beneficial effects that: the invention solves the problems of difficult alignment, poor wetting, easy dislocation, low connection strength and the like in the flip chip welding of the prior chip by utilizing the traditional semiconductor processing method, and has the advantages of simple process, easy operation and the like. The invention can be applied to the second-level packaging in IC packaging, can also be applied to wafer-level packaging, three-dimensional packaging, system-level packaging and MEMS packaging, can greatly improve the quality and strength of packaging welding spots, reduces the packaging difficulty, and has wide application prospect in the field of semiconductor manufacturing.
Drawings
FIG. 1 is a schematic view of the structure of the invention after plastic encapsulation;
FIG. 2 is a schematic structural diagram of a micro bump;
FIG. 3 is a schematic illustration of the method of the present invention before it is encapsulated with a molding compound;
wherein: 1-chip; 2-micro convex points; 3-a conductive post; 4-a substrate; 5-blind holes; 6-plastic packaging.
Detailed Description
The following embodiments are given in conjunction with the accompanying drawings
the bottom surface of the chip is provided with a micro-bump formed by solder, and the micro-bump is provided with a blind hole;
the substrate is provided with a copper column (5), the conductive column is inserted in the blind hole, and the inner diameter of the conductive column is matched with the outer diameter of the blind hole;
and the chip and the micro bumps are wrapped by plastic package.
The micro-bumps are made of solder, and the solder is made of tin, tin-silver alloy and tin-silver-copper alloy.
The micro-bumps are constructed as spheres.
The conductive column is a copper column, or the conductive column is a cylinder.
The flip chip welding packaging method of the chip comprises the following steps:
constructing a micro-bump on the bottom surface of a chip by adopting a micro-processing technology, and processing a blind hole on the micro-bump; forming a conductive column (5) on a bonding pad of the substrate;
step two, attaching the chip to the substrate so that the conductive column is inserted into the blind hole;
thirdly, performing diffusion welding, preferably reflow welding, on the conductive posts and the blind holes;
and step four, wrapping the chip with a plastic package material after welding is finished, and packaging the chip on the substrate.
The micro-machining process is a laser process.
the bottom surface of the chip is provided with a micro-bump formed by solder, and the micro-bump is provided with a blind hole;
the substrate is provided with a copper column (5), the conductive column is inserted in the blind hole, and the inner diameter of the conductive column is matched with the outer diameter of the blind hole;
and the chip and the micro bumps are wrapped by plastic package.
The micro-bumps are formed by laser micro-machining.
The micro-bumps are made of solder, and the solder is made of tin, tin-silver alloy and tin-silver-copper alloy.
The micro-bumps are constructed as spheres.
The conductive column is a copper column, or the conductive column is a cylinder.
The flip chip welding packaging method of the chip comprises the following steps:
constructing a micro-bump on the bottom surface of a chip by adopting a micro-processing technology, and processing a blind hole on the micro-bump; forming a conductive column (5) on a bonding pad of the substrate;
step two, attaching the chip to the substrate so that the conductive column is inserted into the blind hole;
thirdly, performing diffusion welding, preferably reflow welding, on the conductive posts and the blind holes;
and step four, wrapping the chip with a plastic package material after welding is finished, and packaging the chip on the substrate.
The micro-processing technology is laser, electroplating, sputtering or vapor deposition technology.
A plurality of blind holes are formed in each micro bump, and each blind hole is inserted with one conductive column.
The conductive column is a copper column, the micro-convex points are tin or tin-based solder, and the tin or tin-based solder is fully reacted to generate Cu3Sn in the reflow soldering. The Cu3Sn has higher strength and higher melting point, so that the welding point has higher strength, and the phenomenon that the welding point melts back in the subsequent re-reflow process can be prevented.
Claims (10)
1. The utility model provides a flip-chip bonding packaging structure of chip which characterized in that: the packaging structure comprises a chip (1), a plastic package (6), solder and a substrate (4);
the bottom surface of the chip is provided with a micro-bump formed by solder, and the micro-bump is provided with a blind hole;
the substrate is provided with a copper column (5), the conductive column is inserted in the blind hole, and the inner diameter of the conductive column is matched with the outer diameter of the blind hole;
and the chip and the micro bumps are wrapped by plastic package.
2. The flip chip package structure of claim 1, wherein: the microbumps are formed by micromachining, preferably, by laser micromachining.
3. The flip chip package structure of claim 1, wherein: the micro-bumps are made of solder.
4. The flip chip package structure of claim 3, wherein: the solder material is tin, tin-silver alloy and tin-silver-copper alloy.
5. The flip chip package structure of claim 1, wherein: the micro-bumps are configured as spheres or cubes.
6. The flip chip package structure of claim 1, wherein: the conductive column is a copper column, and the conductive column is a cylinder or a prism.
7. A flip chip bonding packaging method of a chip comprises the following steps:
constructing a micro-bump on the bottom surface of a chip by adopting a micro-processing technology, and processing a blind hole on the micro-bump; forming a conductive column (5) on a bonding pad of the substrate;
step two, attaching the chip to the substrate so that the conductive column is inserted into the blind hole;
thirdly, performing diffusion welding, preferably reflow welding, on the conductive posts and the blind holes;
and step four, wrapping the chip with a plastic package material after welding is finished, and packaging the chip on the substrate.
8. The flip chip bonding packaging method of a chip according to claim 7, wherein: the conductive column is a copper column, the micro-convex points are tin or tin-based solder, and the tin or tin-based solder is fully reacted to generate Cu3Sn in the reflow soldering.
9. The flip chip bonding packaging method of a chip according to claim 7, wherein: the micro-processing technology is laser, electroplating, sputtering or vapor deposition technology.
10. The flip chip bonding packaging method of a chip according to claim 7, wherein: a plurality of blind holes are formed in each micro bump, and each blind hole is inserted with one conductive column.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911353667.9A CN111128913B (en) | 2019-12-24 | 2019-12-24 | Flip-chip welding packaging structure and method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911353667.9A CN111128913B (en) | 2019-12-24 | 2019-12-24 | Flip-chip welding packaging structure and method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111128913A true CN111128913A (en) | 2020-05-08 |
| CN111128913B CN111128913B (en) | 2022-02-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201911353667.9A Active CN111128913B (en) | 2019-12-24 | 2019-12-24 | Flip-chip welding packaging structure and method thereof |
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| CN (1) | CN111128913B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112420528A (en) * | 2020-11-27 | 2021-02-26 | 上海易卜半导体有限公司 | Semiconductor packaging method, semiconductor assembly and electronic equipment comprising semiconductor assembly |
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|---|---|---|---|---|
| JPH0766207A (en) * | 1993-08-24 | 1995-03-10 | Sony Corp | Surface mount device, manufacture thereof, and soldering method |
| JP2004158701A (en) * | 2002-11-07 | 2004-06-03 | Seiko Epson Corp | Bump structure for mounting element chip and method for forming the same |
| JP2004207293A (en) * | 2002-12-24 | 2004-07-22 | Seiko Epson Corp | Semiconductor device and its manufacturing method, circuit board, and electronic equipment |
| US20090146301A1 (en) * | 2007-12-11 | 2009-06-11 | Panasonic Corporation | Semiconductor device and method of manufacturing the same |
| CN104051356A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Package-on-Package Structure and Method for Forming the Same |
| CN104241236A (en) * | 2014-08-28 | 2014-12-24 | 南通富士通微电子股份有限公司 | Semiconductor flip-chip packaging structure |
| CN104779231A (en) * | 2014-01-15 | 2015-07-15 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN106816417A (en) * | 2017-01-13 | 2017-06-09 | 南京大学 | A kind of high-density packages and its manufacture method |
-
2019
- 2019-12-24 CN CN201911353667.9A patent/CN111128913B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0766207A (en) * | 1993-08-24 | 1995-03-10 | Sony Corp | Surface mount device, manufacture thereof, and soldering method |
| JP2004158701A (en) * | 2002-11-07 | 2004-06-03 | Seiko Epson Corp | Bump structure for mounting element chip and method for forming the same |
| JP2004207293A (en) * | 2002-12-24 | 2004-07-22 | Seiko Epson Corp | Semiconductor device and its manufacturing method, circuit board, and electronic equipment |
| US20090146301A1 (en) * | 2007-12-11 | 2009-06-11 | Panasonic Corporation | Semiconductor device and method of manufacturing the same |
| CN104051356A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Package-on-Package Structure and Method for Forming the Same |
| CN104779231A (en) * | 2014-01-15 | 2015-07-15 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
| CN104241236A (en) * | 2014-08-28 | 2014-12-24 | 南通富士通微电子股份有限公司 | Semiconductor flip-chip packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112420528A (en) * | 2020-11-27 | 2021-02-26 | 上海易卜半导体有限公司 | Semiconductor packaging method, semiconductor assembly and electronic equipment comprising semiconductor assembly |
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| CN111128913B (en) | 2022-02-11 |
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