JP2004103798A - Method of manufacturing two metal tapes and wiring substrate - Google Patents

Method of manufacturing two metal tapes and wiring substrate Download PDF

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Publication number
JP2004103798A
JP2004103798A JP2002263123A JP2002263123A JP2004103798A JP 2004103798 A JP2004103798 A JP 2004103798A JP 2002263123 A JP2002263123 A JP 2002263123A JP 2002263123 A JP2002263123 A JP 2002263123A JP 2004103798 A JP2004103798 A JP 2004103798A
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Japan
Prior art keywords
conductor
adhesive
layer
base material
via hole
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Pending
Application number
JP2002263123A
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Japanese (ja)
Inventor
Kentaro Kaneko
金子　健太郎
Mamoru Hayashi
林　衛
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2002263123A priority Critical patent/JP2004103798A/en
Publication of JP2004103798A publication Critical patent/JP2004103798A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing two metal tapes which can prevent the generation of voids within vias and peeling between a base material and a bonding agent, and simultaneously can improve adhesive strength between the bonding agent and a conductive layer, and the etching property of the conductive layer. <P>SOLUTION: A first conductive layer of laminated conductor foil is formed on only one surface of a base material, a via-hole with the conductive layer as a bottom is also formed. A via is formed by electrolytic plating using the conductive layer as a power feed layer after dry-cleaning the inside of the via-hole, or filling the entire via-hole with a conductor of conductive paste. A second conductive layer is formed on the other surface of the base material by wet-desmearing, non-electrolytic plating, electrolytic plating or by laminating the conductive foils. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体パッケージの配線基板に適した２メタルテープ（２ｍｅｔａｌテープ）の製造方法に関し、詳しくは、絶縁性樹脂基材の両面にそれぞれ第１、第２の接着剤を介して第１、第２の導体層を備え、上記基材と上記第１、第２の接着剤とを貫通するビアにより上記第１、第２の導体層が相互に電気的に接続されている２メタルテープの製造方法に関する。
【０００２】
本発明は更に、上記の２メタルテープを用いて配線基板を製造する方法に関する。
【０００３】
【従来の技術】
半導体パッケージ、特にＣＳＰ（チップサイズパッケージ）やＢＧＡ（ボールグリッドアレー）等の半導体パッケージの配線基板に上記の構造を有する２メタルテープが用いられている。
【０００４】
図１（１）に示すように、２メタルテープ１００は、絶縁性樹脂基材１０の両面に接着剤層１２ａ、１２ｂを介して導体層１４ａ、１４ｂを被覆し、所定箇所に基材１０を貫通して設けたビア１６により両面の導体層１４ａと１４ｂを電気的に接続したものである。各構成部分の材質は、樹脂基材１０としてポリイミドやアラミド等の樹脂フィルム、接着剤１２ａ、１２ｂとしてポリイミド系接着剤、導体層１４ａ、１４ｂとして銅が、それぞれ代表的である。
【０００５】
図１（２）に、２メタルテープを用いた半導体パッケージの構造例を示す。半導体パッケージ１０２は、図１（１）の２メタルテープ１００を用いて作製した配線基板１０４に半導体チップ１０６を搭載した構成である。配線基板１０４の主部１００’は、２メタルテープ１００の両面の導体層１４ａ、１４ｂをパターニングすることによりそれぞれ所定の配線パターン１４Ａ、１４Ｂを形成したものである。
【０００６】
下面の配線パターン１４Ｂは一部が端子用ランドとして形成されており、そこに外部接続端子１８が接合されている。配線基板１０４の下面は外部接続端子１８を除く全面がソルダレジスト２１により覆われている。
【０００７】
上面の配線パターン１４Ａは一部が接続用パッドとして形成されており、そこに接続バンプ２０が接合されている。配線基板１０４の上面は接続バンプ２０を除く全面がソルダレジスト２２により覆われている。半導体チップ１０６はその電極端子２４が接続バンプ２０に接合されて配線基板１０４上に搭載され、封止樹脂２６により封止されて、半導体パッケージ１０２を構成する。
【０００８】
なお、図１（２）に示した半導体パッケージ１０２は配線基板１０４上に直接半導体チップ１０６を搭載した最も単純な構造例であるが、配線基板主部１００’上にビルトアップによる多層配線を形成した回路基板としての半導体パッケージや、更にその上に半導体チップ１０６を搭載した半導体パッケージもある。
【０００９】
従来、２メタルテープ１００の製造は図２に示す工程１〜７を順次行なう方法により行なわれていた。
【００１０】
〔工程１〕樹脂基材の準備（図２（１））
ポリイミドやアラミド等の樹脂フィルムから成る樹脂基材１０を準備する。樹脂基材１０の厚さは、例えば２５μｍ、１２．５μｍ等である。
【００１１】
〔工程２〕接着剤の塗布（図２（２））
樹脂基材１０の一方の面にポリイミド系等の接着剤１２ａ’を塗布する。塗布厚さは、例えば１０μｍ程度である。接着剤１２ａ’は未硬化のままとする。
【００１２】
〔工程３〕接着剤の塗布（図２（３））
樹脂基材１０の他方の面にもポリイミド系等の接着材１２ｂ’を塗布する。塗布厚さは、例えば１０μｍ程度である。接着剤１２ｂ’も未硬化のままとする。
【００１３】
〔工程４〕接着剤の硬化処理（図２（４））
両面の接着剤１２ａ’、１２ｂ’を硬化させる（硬化後の接着剤を１２ａ、１２ｂで示す）。この硬化は、例えば１００〜１５０℃に１〜２時間加熱することにより行なう。
【００１４】
〔工程５〕ビア穴の形成（図２（５））
レーザ加工等により貫通孔としてのビア穴１６’を形成する。ビア穴の径は、例えば２０〜３０μｍである。
【００１５】
〔工程６〕デスミアと無電解めっき（図２（６））
酸素プラズマや反応性ガス（ＣＦ４）等を用いたドライデスミアによる表面クリーニングと、ＫＭｎＯ４水溶液に例えば１０分浸漬する等のウェットデスミアによる表面粗化とを順次行なった後に、無電解めっきにより、硬化接着剤１２ａ、１２ｂの表面全体およびビア穴１６’の壁面に銅の薄層１４’を形成する。
【００１６】
〔工程７〕電解めっき（図２（７））
銅薄層１４’を給電層とする電解めっきにより、硬化接着剤１２ａ、１２ｂの表面全体およびビア穴１６’内全体に、薄層１４’を含む銅の導体層１４ａ、１４ｂおよびビア１６を形成して、２メタルテープ１００が完成する。
【００１７】
【発明が解決しようとする課題】
前記従来の２メタルテープの製造方法には、下記の点で問題があった。
【００１８】
（１）前記の工程７において、電解めっきによるビア１６の形成は、ビア穴１６’の両端から導体の充填が進行することにより行なわれる。その際、ビア穴１６’の内部が完全に充填される前にビア穴１６’の端部が導体で閉塞されると、形成されたビア１６の内部に未充填部すなわち空洞（ボイド）が発生する。
【００１９】
（２）前記の工程６において、ウェットデスミア処理の際に、基材１０と接着剤１２ａ、１２ｂとの界面がビア穴１６の壁面に露出しているため、この界面に処理液が浸透し、基材１０と接着剤１２ａ、１２ｂとの界面で剥離が発生する原因になる。
【００２０】
また、従来方法の下記の点を改良すれば更に有利である。
【００２１】
前記の工程６〜７において、ウェットデスミア＋導体無電解めっき＋導体電解めっきにより、接着剤１２ａ、１２ｂの表面に導体層１４ａ、１４ｂを形成している。このような形成方法の場合、接着剤１２ａ、１２ｂと導体層１４ａ、１４ｂとの接合強度（ピール強度）の向上と、導体層１４ａ、１４ｂのエッチング性の向上とが相反する関係にあるため、両者を共に向上させることができない。
【００２２】
そこで本発明は、ビア内部のボイドの発生および基材と接着剤との剥離を防止し、同時に接着剤と導体層との接合強度および導体層のエッチング性を同時に向上させることができる、２メタルテープの製造方法を提供することを目的とする。
【００２３】
本発明は更に、上記の２メタルテープを用いて配線基板を製造する方法を提供することを目的とする。
【００２４】
【課題を解決するための手段】
上記の目的を達成するために、本発明の２メタルテープの製造方法は、絶縁性樹脂基材の両面にそれぞれ第１、第２の接着剤を介して第１、第２の導体層を備え、上記基材と上記第１、第２の接着剤とを貫通するビアにより上記第１、第２の導体層が相互に電気的に接続されている２メタルテープの製造方法において、下記の工程〔１〕〜〔１２〕：
〔１〕絶縁性樹脂基板を準備する工程、
〔２〕絶縁性樹脂基材の一方の面に第１接着剤を塗布する工程、
〔３〕上記第１接着剤の上に第１導体層として導体箔をラミネートする工程、
〔４〕上記第１接着剤を硬化させることにより、上記基板の一方の面に上記導体箔を接合して第１導体層とする工程、
〔５〕上記基材の他方の面に第２接着剤を塗布する工程、
〔６〕上記導体箔の自由表面に保護皮膜を被覆する工程、
〔７〕上記第２接着剤、上記基材および上記第１接着剤を貫通して上記導体箔により底部が確定されたビア穴を形成する工程、
〔８〕上記ビア穴の内部を乾式クリーニングする工程、
〔９〕上記ビア穴の底部に露出した上記導体箔を給電層とする電解めっきにより上記ビア穴内全体に導体を充填して、該導体箔で底面が画定されたビアを形成する工程、
〔１０〕上記第２接着剤の表面および上記ビアの露出面に、表面粗化処理を施した後に、無電解めっきにより導体の薄層を形成する工程、
〔１１〕上記導体薄層を給電層とする電解めっきにより該導体薄層上に第２導体層を形成する工程、および
〔１２〕上記第２接着剤を硬化させることにより上記基板の他方の面に上記第２導体層を接合する工程
を順次行なうことを特徴とする。
【００２５】
上記工程〔９〕に代えて、上記ビア穴内に導電性ペーストを充填することにより、上記ビアを形成することもできる。
【００２６】
上記工程〔１０〕および〔１１〕に代えて、上記第２接着剤の表面および上記ビアの露出面に導体箔をラミネートすることにより、上記第２導体層を形成することもできる。
【００２７】
更に、上記の方法により製造された２メタルテープの前記第１、第２の導体層をそれぞれパターニングして配線パターンを形成することにより配線基板を製造することができる。
【００２８】
【発明の実施の形態】
本発明の２メタルテープの製造方法によれば、前記従来方法の問題点（１）および（２）を下記のように解消できる。
【００２９】
（１）ビア内のボイド発生防止
従来法においてビア内にボイド（導体未充填部）が発生したのは、ビア穴への導体の充填を基材両面から進行させたことが原因である。
【００３０】
これに対して本発明の方法においては、まず工程〔１〕〜〔４〕で基材の一方の面のみに導体層（導体箔のラミネートによる第１導体層）を形成し、工程〔５〕〜〔７〕で上記導体層を底面とするビア穴を形成し、工程〔８〕でビア穴内を乾式クリーニングしてから、工程〔９〕で上記導体層を給電層とする電解めっきを行なうことによりビア穴全体を導体で充填してビアを形成する。
【００３１】
このようにビア穴全体の充填を基材の一方の面側からのみ行なうので、従来のようにビア内に未充填によるボイドが発生することがない。
【００３２】
本発明の方法においてビアの形成は、上記の工程〔９〕に代えて、ビア穴への導電性ペーストの充填によっても行なうことができる。この場合にも、底面が導体層（導体箔）で画定されているビア穴へ、ビア穴開口端側から導電性ペーストを供給して充填するので、充填により形成されたビア内部に未充填によりボイドが発生することはない。
【００３３】
（２）基材／接着剤界面での剥離防止
従来法において基材／接着剤界面で剥離が発生したのは、基材両面からの電解めっきによりビア穴の充填と両面の導体層とを一括して形成していたため、電解めっきのための給電層として無電解めっきによる導体の薄層を前もって形成する必要があり、無電解めっきに必要な表面粗化を、基材／接着剤界面がビア穴の壁面に露出している状態でウェットデスミアによって行なっていたことが原因である。
【００３４】
これに対して本発明においては、工程〔７〕で形成したビア穴の内部を工程〔８〕で乾式クリーニングした後に、工程〔９〕でビア穴の底面を構成する導体箔を給電層する電解めっきによりビア穴を導体で充填する。
【００３５】
すなわち、ビア穴を導体で充填するための電解めっきは、ビア穴底面の導体箔を給電層として行なえるので、従来のようにウェットデスミアと無電解めっきによる給電層の形成を行なう必要がないため、ウェットデスミアの際の処理液浸透に起因する基材／接着剤界面での剥離は発生することがない。また、電解めっき前に行なうビア穴内部のクリーニングは乾式で行なうので、ビア穴壁面から処理液が浸透することはない。
【００３６】
本発明は、従来方法に比べて更に下記の点で有利である。
【００３７】
すなわち、従来方法では基材両面の導体層はいずれも接着剤上への導体電解めっきによって行なっていたので、配線パターン形成のために導体層をエッチングする際に、接着剤による接合強度とエッチング性と同時に向上させることができなかった。
【００３８】
これに対して本発明においては、基材両面の導体層のうち少なくとも一方は導体箔のラミネートにより形成する。すなわち、最初に形成する第１導体層は導体箔のラミネートにより形成し、後で形成する第２導体層は、工程〔１０〕の前処理と工程〔１１〕の電解めっきで形成するか、あるいは工程〔１０〕〜〔１１〕の代わりに導体箔のラミネートで形成する。したがって、ラミネートにより形成した導体層（第１導体層のみ、または第１、第２導体層の両者）については接合強度とエッチング性とを独立に向上させることが可能である。
【００３９】
以下に、本発明の各実施形態により２メタルテープを製造する手順を具体的に説明する。
【００４０】
〔実施形態１〕
図３を参照して、本発明による２メタルテープの製造方法の一実施形態を説明する。
【００４１】
〔工程１〕樹脂基材の準備（図３（１））
ポリイミドやアラミド等の樹脂フィルムから成る樹脂基材１０を準備する。樹脂基材１０の厚さは、例えば２５μｍ、１２．５μｍ等である。
【００４２】
〔工程２〕第１接着剤の塗布（図３（２））
樹脂基材１０の一方の面にポリイミド系等の第１接着剤１２ａ’を塗布する。塗布厚さは、例えば１０μｍ程度である。第１接着剤１２ａ’は未硬化のままとする。
【００４３】
〔工程３〕導体箔のラミネート（第１導体層形成）（図３（３））
第１接着剤１２ａ’上に第１導体層として銅箔等の導体箔１４ａをラミネートする。銅箔は例えば厚さ１８μｍである。ラミネートは例えば温度１３０℃にて行なう。これにより、第１接着剤１２ａ’が半硬化状態になり、導体箔１４ａが仮接合される。
【００４４】
〔工程４〕第１接着剤の硬化処理（第１導体層接合）（図３（４））
第１接着剤１２ａ’を硬化させる（硬化後の第１接着剤を１２ａで示す）。この硬化は、例えば１７０℃に１〜２時間加熱することにより行なう。これにより、基板１０の一方の面に第１導体層としての導体箔１４ａが接合される。
【００４５】
〔工程５〕第２接着剤の塗布（図３（５）（注：図３（４）に対して上下を逆転して図示。以下同様。））
基材１０の他方の面に、ポリイミド系等の第２接着剤１２ｂ’を塗布する。塗布厚さは、例えば１０μｍ程度である。第２接着剤１２ｂ’は未硬化のままとする。
【００４６】
〔工程６〕保護皮膜の被覆（図３（６））
導体箔１４ａの自由表面をＰＥＴ等の保護皮膜１５で被覆する。これにより、導体箔１４ａの自由表面が、以降の工程における処理の際に保護される。
【００４７】
〔工程７〕ビア穴の形成（図３（７））
第２接着剤１２ｂ’、基材１０および第１接着剤１２ａを貫通して第１導体層（導体箔）１４ａにより底部が確定されたビア穴１６’を形成する。ビア穴１６’の径は、例えば２０〜３０μｍである。
【００４８】
〔工程８〕ビア穴内のクリーニング（図３（８））
形成したビア穴１６’内をクリーニングする。このクリーニングは、ＣＯ２プラズマ処理あるいは反応性ガス（例えばＣＦ４）等によるドライデスミアによって行なう。これによりビア穴１６’内の残留物１７（図３（７））を気化させて除去する。
【００４９】
〔工程９〕ビアの形成（図３（９））
ビア穴１６’の底部に露出した第１導体層（導体箔）１４ａを給電層とする電解めっきにより、ビア穴１６’内全体に銅等の導体を充填してビア１６を形成する。電解めっきに際しては、ビア穴１６’内へ噴流、超音波等により常に新鮮なめっき液を供給する。
【００５０】
〔工程１０〕デスミアと無電解めっき（図３（１０））
未硬化第２接着剤１２ｂ’の表面およびビア１６の露出面に、酸素プラズマや反応性ガス（例えばＣＦ４）等を用いたドライデスミアによるクリーニングと、ＫＭｎＯ４水溶液に例えば１０分浸漬する等のウェットデスミアによる表面粗化とを順次行なった後に、無電解めっきにより銅等の導体の薄層１４’を形成する。
【００５１】
〔工程１１〕第２導体層の形成（図３（１１））
銅等の薄層１４’を給電層とする電解めっきにより、この薄層１４’を含めて銅等の導体から成る第２導体層１４ｂを形成する。
【００５２】
〔工程１２〕第２接着剤の硬化処理（図３（１２））
第２接着剤１２ｂ’を硬化させる（硬化後の第２接着剤を１２ｂで示す）。この硬化は、例えば１７０℃に１〜２時間加熱することにより行なう。これにより、基板の他方の面に第２導体層が接合される。
【００５３】
以上の工程により、絶縁性樹脂基材１０の両面にそれぞれ第１、第２の接着剤１２ａ、１２ｂを介して導体層１４ａ、１４ｂが接合され、導体層１４ａ、１４ｂがビア１６により電気的に接続された２メタルテープ１００（図１（１））が完成する。
【００５４】
保護皮膜１５は、途中の処理工程において導体箔１４ａの自由表面を保護するために設けたが、完成した２メタルテープを使用までの搬送等において保護するためにも利用できるので、実際に使用するまでに適宜除去すればよい。
【００５５】
〔実施形態２〕
本実施形態においては、実施形態１の工程の一部を変更して２メタルテープを製造する。
【００５６】
図３（７）のビア穴１６’を導体で充填して図３（８）のビア１６を形成する際に、実施形態１の工程〔９〕に代えて、ビア穴１６’に導電性ペーストを充填することによりビア１６を形成する。これは、はんだペーストやペースト状導電性樹脂等の導電性ペーストを、スクリーン印刷によりビア穴１６’に選択的に充填することによって行なうことができる。ビア形成以前および以後の工程、すなわち工程〔１〕〜〔８〕および工程〔１０〕〜〔１２〕は、実施形態１と同様に行なう。
【００５７】
本実施形態によっても、実施形態１と同等の作用効果が得られる。
【００５８】
〔実施形態３〕
本実施形態においても、実施形態１の工程の一部を変更して２メタルテープを製造する。
【００５９】
図３（１０）の第２導体層１４ｂを形成する際に、実施形態１の工程〔１０〕〜〔１１〕に代えて、第２接着剤１２ｂの表面およびビア１６の露出面に銅箔等の導体箔をラミネートすることにより第２導体層１４ｂを形成する。第２導体層形成以前および以後の工程、すなわち工程〔１〕〜〔９〕および工程〔１２〕は、実施形態１と同様に行なう。
【００６０】
本実施形態によっても、実施形態１と同等の作用効果が得られる。
【００６１】
図４に、実施形態１、２、３のプロセスのフローチャートを一括して示す。
【００６２】
なお、実施形態２および３の工程変更はそれぞれ単独で行なってもよいし、両者を組み合わせて行なってもよい。
【００６３】
例えば、実施形態３を採用して導体箔のラミネートにより第２導体層１４ｂを形成する場合に、それより前の工程であるビア１６の形成を、実施形態２を採用してはんだペーストやペースト状導電性樹脂等の導電性ペーストの充填により行なうことが好適である。このようにすると、導体箔をラミネートする際の加熱・加圧により、はんだペーストが溶融して導体箔と接合したり、あるいはペースト状導電性樹脂が硬化して導体箔と接合したりするので、ビアと導体箔との接合を更に良好に行なうことができる。
【００６４】
本発明によれば、上記実施形態１、２、３のいずれかにより又は実施形態２と実施形態３との組合せにより製造された２メタルテープ１００の第１、第２の導体層１４ａ、１４ｂをそれぞれパターニングすることにより配線基板を製造することができる。
【００６５】
【発明の効果】
本発明によれば、ビア内部のボイドの発生および基材と接着剤との剥離を防止し、同時に接着剤と導体層との接合強度および導体層のエッチング性を同時に向上させることができる、２メタルテープの製造方法およびこの２メタルテープを用いた配線基板の製造方法が提供される。
【図面の簡単な説明】
【図１】図１は、（１）本発明による製造対象である２メタルテープの基本構造を示す断面図および（２）２メタルテープを用いた半導体パッケージの構造例を示す断面図である。
【図２】図２は、従来法による２メタルテープの製造工程を示す断面図である。
【図３】図３は、本発明による２メタルテープの製造工程を示す断面図である。
【図４】図４は、本発明の各実施形態による２メタルテープの製造工程を示すフローチャートである。
【符号の説明】
１００…２メタルテープ
１０２…半導体パッケージ
１０４…配線基板
１０６…半導体チップ
１０…絶縁性樹脂基材
１２ａ、１２ｂ…接着剤層（硬化後）
１２ａ’、１２ｂ’…接着剤層（硬化前）
１４ａ、１４ｂ…導体層
１４Ａ、１４Ｂ…配線パターン
１４’…導体薄層（無電解めっき層）
１５…保護皮膜
１６…ビア
１６’…ビア穴
１７…残留物
１８…外部接続端子
２０…接続バンプ
２１、２２…ソルダレジスト
２４…電極端子
２６…封止樹脂[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a two-metal tape (2 metal tape) suitable for a wiring board of a semiconductor package. More specifically, the present invention relates to a method for manufacturing a first and second adhesives on both surfaces of an insulating resin base material via first and second adhesives, respectively. A two-metal tape comprising a second conductor layer, wherein the first and second conductor layers are electrically connected to each other by a via penetrating the base material and the first and second adhesives. It relates to a manufacturing method.
[0002]
The present invention further relates to a method for manufacturing a wiring board using the above-described two-metal tape.
[0003]
[Prior art]
A two-metal tape having the above structure is used for a wiring board of a semiconductor package, particularly a semiconductor package such as a CSP (chip size package) or a BGA (ball grid array).
[0004]
As shown in FIG. 1 (1), the two-metal tape 100 covers both surfaces of an insulating resin substrate 10 with conductor layers 14a and 14b via adhesive layers 12a and 12b, and places the substrate 10 at a predetermined position. The conductor layers 14a and 14b on both sides are electrically connected by a via 16 provided therethrough. The material of each component is typically a resin film such as polyimide or aramid as the resin base material 10, a polyimide adhesive as the adhesives 12a and 12b, and copper as the conductor layers 14a and 14b.
[0005]
FIG. 1B shows a structural example of a semiconductor package using a two-metal tape. The semiconductor package 102 has a configuration in which a semiconductor chip 106 is mounted on a wiring board 104 manufactured using the two-metal tape 100 of FIG. The main portion 100 ′ of the wiring board 104 has predetermined wiring patterns 14 A and 14 B formed by patterning the conductor layers 14 a and 14 b on both surfaces of the two-metal tape 100.
[0006]
A part of the wiring pattern 14B on the lower surface is formed as a terminal land, and the external connection terminal 18 is joined thereto. The entire lower surface of the wiring board 104 except the external connection terminals 18 is covered with the solder resist 21.
[0007]
A part of the wiring pattern 14A on the upper surface is formed as a connection pad, and the connection bump 20 is joined thereto. The entire upper surface of the wiring board 104 except the connection bumps 20 is covered with the solder resist 22. The semiconductor chip 106 has the electrode terminals 24 bonded to the connection bumps 20, is mounted on the wiring board 104, and is sealed with the sealing resin 26 to form the semiconductor package 102.
[0008]
Although the semiconductor package 102 shown in FIG. 1B is the simplest example of a structure in which the semiconductor chip 106 is directly mounted on the wiring board 104, a multilayer wiring is formed on the wiring board main part 100 'by built-up. There is also a semiconductor package as a circuit board as described above, and a semiconductor package further having a semiconductor chip 106 mounted thereon.
[0009]
Conventionally, the manufacture of the two-metal tape 100 has been performed by a method of sequentially performing steps 1 to 7 shown in FIG.
[0010]
[Step 1] Preparation of resin base material (FIG. 2 (1))
A resin substrate 10 made of a resin film such as polyimide or aramid is prepared. The thickness of the resin substrate 10 is, for example, 25 μm, 12.5 μm, or the like.
[0011]
[Step 2] Application of adhesive (FIG. 2 (2))
An adhesive 12a 'such as a polyimide resin is applied to one surface of the resin base material 10. The coating thickness is, for example, about 10 μm. The adhesive 12a 'remains uncured.
[0012]
[Step 3] Application of adhesive (FIG. 2 (3))
The other surface of the resin base material 10 is also coated with an adhesive 12b 'such as a polyimide-based material. The coating thickness is, for example, about 10 μm. The adhesive 12b 'is also left uncured.
[0013]
[Step 4] Curing treatment of adhesive (FIG. 2 (4))
The adhesives 12a 'and 12b' on both sides are cured (the cured adhesives are indicated by 12a and 12b). This curing is performed, for example, by heating to 100 to 150 ° C. for 1 to 2 hours.
[0014]
[Step 5] Formation of via hole (FIG. 2 (5))
Via holes 16 'as through holes are formed by laser processing or the like. The diameter of the via hole is, for example, 20 to 30 μm.
[0015]
[Step 6] Desmearing and electroless plating (Fig. 2 (6))
After sequentially performing surface cleaning by dry desmear using oxygen plasma or a reactive gas (CF 4 ) or the like, and surface roughening by wet desmear such as immersion in an aqueous KMnO 4 solution for 10 minutes, for example, electroless plating is performed. A thin copper layer 14 'is formed on the entire surface of the cured adhesives 12a and 12b and on the wall surfaces of the via holes 16'.
[0016]
[Step 7] electrolytic plating (FIG. 2 (7))
The copper conductor layers 14a, 14b and the vias 16 including the thin layer 14 'are formed on the entire surface of the hardened adhesives 12a, 12b and the entire inside of the via holes 16' by electrolytic plating using the copper thin layer 14 'as a power supply layer. Then, the two-metal tape 100 is completed.
[0017]
[Problems to be solved by the invention]
The conventional method of manufacturing a two-metal tape has the following problems.
[0018]
(1) In the above step 7, formation of the via 16 by electrolytic plating is performed by filling the conductor from both ends of the via hole 16 '. At this time, if the end of the via hole 16 ′ is closed with a conductor before the inside of the via hole 16 ′ is completely filled, an unfilled portion, that is, a void (void) occurs inside the formed via 16. I do.
[0019]
(2) In the above step 6, since the interface between the base material 10 and the adhesives 12a and 12b is exposed on the wall surface of the via hole 16 during the wet desmear treatment, the processing liquid permeates the interface, It causes peeling at the interface between the base material 10 and the adhesives 12a and 12b.
[0020]
Further, it is more advantageous to improve the following points of the conventional method.
[0021]
In the steps 6 and 7, the conductor layers 14a and 14b are formed on the surfaces of the adhesives 12a and 12b by wet desmear + conductor electroless plating + conductor electrolytic plating. In the case of such a forming method, the improvement of the bonding strength (peel strength) between the adhesives 12a and 12b and the conductor layers 14a and 14b and the improvement of the etching property of the conductor layers 14a and 14b are in a contradictory relationship. Both cannot be improved.
[0022]
Accordingly, the present invention provides a two-metal structure capable of preventing the occurrence of voids inside a via and the separation of a base material and an adhesive, and simultaneously improving the bonding strength between the adhesive and the conductive layer and the etching property of the conductive layer. An object of the present invention is to provide a method for manufacturing a tape.
[0023]
Another object of the present invention is to provide a method for manufacturing a wiring board using the above-mentioned two-metal tape.
[0024]
[Means for Solving the Problems]
In order to achieve the above object, a method for manufacturing a two-metal tape of the present invention includes first and second conductor layers on both surfaces of an insulating resin base material via first and second adhesives, respectively. In a method of manufacturing a two-metal tape in which the first and second conductor layers are electrically connected to each other by vias penetrating the base material and the first and second adhesives, the following steps are provided. [1] to [12]:
[1] a step of preparing an insulating resin substrate,
[2] a step of applying a first adhesive to one surface of the insulating resin base material,
[3] a step of laminating a conductor foil as a first conductor layer on the first adhesive;
[4] a step of bonding the conductor foil to one surface of the substrate by curing the first adhesive to form a first conductor layer;
[5] a step of applying a second adhesive to the other surface of the base material,
[6] a step of coating the free surface of the conductor foil with a protective film,
[7] a step of penetrating the second adhesive, the base material and the first adhesive to form a via hole whose bottom is defined by the conductor foil;
[8] a step of dry cleaning the inside of the via hole,
[9] a step of filling the entire inside of the via hole with a conductor by electrolytic plating using the conductor foil exposed at the bottom of the via hole as a power supply layer, and forming a via having a bottom surface defined by the conductor foil;
[10] a step of forming a thin layer of a conductor by electroless plating after performing a surface roughening treatment on the surface of the second adhesive and the exposed surface of the via;
[11] a step of forming a second conductor layer on the conductor thin layer by electrolytic plating using the conductor thin layer as a power supply layer, and [12] the other surface of the substrate by curing the second adhesive. And a step of sequentially joining the second conductor layers.
[0025]
Instead of the step [9], the via may be formed by filling the via hole with a conductive paste.
[0026]
Instead of the steps [10] and [11], the second conductor layer may be formed by laminating a conductor foil on the surface of the second adhesive and the exposed surface of the via.
[0027]
Furthermore, a wiring board can be manufactured by forming a wiring pattern by patterning the first and second conductor layers of the two-metal tape manufactured by the above method.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
According to the method for manufacturing a two-metal tape of the present invention, the problems (1) and (2) of the conventional method can be solved as follows.
[0029]
(1) Prevention of Void Generation in Vias The void (conductor unfilled portion) in the via in the conventional method is caused by the fact that the filling of the via hole with the conductor proceeds from both sides of the base material.
[0030]
On the other hand, in the method of the present invention, first, in steps [1] to [4], a conductor layer (first conductor layer formed by laminating a conductor foil) is formed only on one surface of the base material, and then in step [5]. Forming a via hole with the conductor layer as a bottom surface in [7], dry-cleaning the inside of the via hole in step [8], and then performing electrolytic plating using the conductor layer as a power supply layer in step [9]. To fill the entire via hole with a conductor to form a via.
[0031]
As described above, since the entire via hole is filled only from one side of the base material, a void due to unfilling in the via does not occur unlike the related art.
[0032]
In the method of the present invention, the formation of the via may be performed by filling the via hole with a conductive paste instead of the step [9]. Also in this case, since the conductive paste is supplied from the opening end side of the via hole into the via hole whose bottom is defined by the conductive layer (conductive foil) and filled, the inside of the via formed by filling is not filled. No voids occur.
[0033]
(2) Prevention of separation at the substrate / adhesive interface In the conventional method, the separation at the substrate / adhesive interface occurred because the filling of the via holes and the conductor layers on both surfaces were performed simultaneously by electrolytic plating from both sides of the substrate. Therefore, it is necessary to previously form a thin layer of a conductor by electroless plating as a power supply layer for electrolytic plating. This is because the wet desmear was performed while the hole was exposed on the wall surface.
[0034]
On the other hand, in the present invention, after the inside of the via hole formed in the step [7] is dry-cleaned in the step [8], in step [9], the conductive foil forming the bottom surface of the via hole is fed to the power supply layer. Fill the via hole with a conductor by plating.
[0035]
That is, since the electrolytic plating for filling the via hole with the conductor can be performed using the conductor foil on the bottom surface of the via hole as the power supply layer, it is not necessary to form the power supply layer by wet desmear and electroless plating as in the related art. No peeling at the substrate / adhesive interface due to the penetration of the treatment liquid during wet desmear does not occur. Further, since cleaning of the inside of the via hole performed before the electrolytic plating is performed by a dry method, the processing liquid does not permeate from the via hole wall surface.
[0036]
The present invention has the following advantages over the conventional method.
[0037]
That is, in the conventional method, since the conductor layers on both sides of the base material are all formed by electroplating the conductor on the adhesive, when the conductor layer is etched to form the wiring pattern, the bonding strength and the etching property by the adhesive are required. At the same time it could not be improved.
[0038]
On the other hand, in the present invention, at least one of the conductor layers on both sides of the substrate is formed by laminating a conductor foil. That is, the first conductor layer to be formed first is formed by laminating a conductor foil, and the second conductor layer to be formed later is formed by pretreatment in step [10] and electrolytic plating in step [11], or It is formed by laminating a conductor foil instead of the steps [10] and [11]. Therefore, for the conductor layer formed by lamination (only the first conductor layer or both the first and second conductor layers), it is possible to independently improve the bonding strength and the etching property.
[0039]
Hereinafter, a procedure for manufacturing a two-metal tape according to each embodiment of the present invention will be specifically described.
[0040]
[Embodiment 1]
Referring to FIG. 3, one embodiment of a method for manufacturing a two-metal tape according to the present invention will be described.
[0041]
[Step 1] Preparation of resin base material (FIG. 3 (1))
A resin substrate 10 made of a resin film such as polyimide or aramid is prepared. The thickness of the resin substrate 10 is, for example, 25 μm, 12.5 μm, or the like.
[0042]
[Step 2] Application of first adhesive (FIG. 3 (2))
A first adhesive 12a 'such as a polyimide resin is applied to one surface of the resin substrate 10. The coating thickness is, for example, about 10 μm. The first adhesive 12a 'remains uncured.
[0043]
[Step 3] Lamination of conductor foil (formation of first conductor layer) (FIG. 3 (3))
A conductive foil 14a such as a copper foil is laminated as a first conductive layer on the first adhesive 12a '. The copper foil has a thickness of, for example, 18 μm. Lamination is performed, for example, at a temperature of 130 ° C. Thereby, the first adhesive 12a 'is in a semi-cured state, and the conductor foil 14a is temporarily joined.
[0044]
[Step 4] Curing treatment of first adhesive (joining of first conductor layer) (FIG. 3 (4))
The first adhesive 12a 'is cured (the first adhesive after curing is indicated by 12a). This curing is performed, for example, by heating to 170 ° C. for 1 to 2 hours. Thereby, the conductor foil 14a as the first conductor layer is joined to one surface of the substrate 10.
[0045]
[Step 5] Application of the second adhesive (FIG. 3 (5) (note: upside down with respect to FIG. 3 (4), shown in the figure, and the same applies hereinafter))
A second adhesive 12b ′ such as a polyimide is applied to the other surface of the base material 10. The coating thickness is, for example, about 10 μm. The second adhesive 12b 'remains uncured.
[0046]
[Step 6] Coating of protective film (FIG. 3 (6))
The free surface of the conductor foil 14a is covered with a protective film 15 such as PET. Thereby, the free surface of the conductor foil 14a is protected during the processing in the subsequent steps.
[0047]
[Step 7] Formation of via hole (FIG. 3 (7))
Via holes 16 'whose bottoms are defined by the first conductor layer (conductor foil) 14a are formed through the second adhesive 12b', the base material 10, and the first adhesive 12a. The diameter of the via hole 16 ′ is, for example, 20 to 30 μm.
[0048]
[Step 8] Cleaning inside via hole (FIG. 3 (8))
The inside of the formed via hole 16 'is cleaned. This cleaning is performed by CO 2 plasma treatment or dry desmear using a reactive gas (for example, CF 4 ). Thus, the residue 17 (FIG. 3 (7)) in the via hole 16 'is vaporized and removed.
[0049]
[Step 9] Formation of via (FIG. 3 (9))
The entire via hole 16 'is filled with a conductor such as copper by electrolytic plating using the first conductor layer (conductor foil) 14a exposed at the bottom of the via hole 16' as a power supply layer to form a via 16. At the time of electrolytic plating, a fresh plating solution is always supplied into the via hole 16 'by a jet or ultrasonic waves.
[0050]
[Step 10] Desmearing and electroless plating (Fig. 3 (10))
The surface of the uncured second adhesive 12b ′ and the exposed surface of the via 16 are cleaned by dry desmear using oxygen plasma or a reactive gas (for example, CF 4 ), and immersed in an aqueous solution of KMnO 4 for 10 minutes, for example. After sequentially performing surface roughening by wet desmear, a thin layer 14 ′ of a conductor such as copper is formed by electroless plating.
[0051]
[Step 11] Formation of second conductor layer (FIG. 3 (11))
The second conductor layer 14b made of a conductor such as copper is formed by electrolytic plating using the thin layer 14 'of copper or the like as a power supply layer.
[0052]
[Step 12] Curing treatment of second adhesive (FIG. 3 (12))
The second adhesive 12b 'is cured (the second adhesive after curing is indicated by 12b). This curing is performed, for example, by heating to 170 ° C. for 1 to 2 hours. Thereby, the second conductor layer is joined to the other surface of the substrate.
[0053]
Through the above steps, the conductor layers 14a and 14b are bonded to both surfaces of the insulating resin substrate 10 via the first and second adhesives 12a and 12b, respectively, and the conductor layers 14a and 14b are electrically connected by the vias 16. The connected two-metal tape 100 (FIG. 1A) is completed.
[0054]
Although the protective film 15 is provided to protect the free surface of the conductor foil 14a in a processing step in the middle, it is actually used because it can be used to protect the completed two-metal tape during transportation until use. It may be removed by the appropriate time.
[0055]
[Embodiment 2]
In the present embodiment, a part of the process of the first embodiment is modified to manufacture a two-metal tape.
[0056]
When the via hole 16 'of FIG. 3 (7) is filled with a conductor to form the via 16 of FIG. 3 (8), the conductive paste is added to the via hole 16' instead of the step [9] of the first embodiment. Is formed to form the via 16. This can be performed by selectively filling the via hole 16 'with a conductive paste such as a solder paste or a paste-like conductive resin by screen printing. Steps before and after via formation, that is, steps [1] to [8] and steps [10] to [12] are performed in the same manner as in the first embodiment.
[0057]
According to this embodiment, the same operation and effect as those of the first embodiment can be obtained.
[0058]
[Embodiment 3]
Also in this embodiment, a part of the process of the first embodiment is changed to manufacture a two-metal tape.
[0059]
When forming the second conductor layer 14b of FIG. 3 (10), instead of the steps [10] to [11] of the first embodiment, a copper foil or the like is provided on the surface of the second adhesive 12b and the exposed surface of the via 16. Is laminated to form the second conductor layer 14b. Steps before and after the formation of the second conductor layer, that is, steps [1] to [9] and step [12] are performed in the same manner as in the first embodiment.
[0060]
According to this embodiment, the same operation and effect as those of the first embodiment can be obtained.
[0061]
FIG. 4 shows a flowchart of the processes of the first, second, and third embodiments collectively.
[0062]
It should be noted that the process changes in Embodiments 2 and 3 may be performed independently, or may be performed in combination.
[0063]
For example, in the case where the second conductor layer 14b is formed by laminating the conductor foil using the third embodiment, the formation of the via 16 which is a process before that is performed by using the second embodiment. It is preferable to carry out by filling with a conductive paste such as a conductive resin. In this case, by heating and pressing when laminating the conductor foil, the solder paste is melted and joined with the conductor foil, or the paste-like conductive resin is cured and joined with the conductor foil, The via and the conductor foil can be more preferably joined.
[0064]
According to the present invention, the first and second conductor layers 14a and 14b of the two-metal tape 100 manufactured according to any one of the first, second, and third embodiments or the combination of the second and third embodiments are used. A wiring board can be manufactured by patterning each.
[0065]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, generation | occurrence | production of the void in a via | veer and peeling of a base material and an adhesive can be prevented, and simultaneously the joint strength of an adhesive and a conductor layer and the etching property of a conductor layer can be improved simultaneously. A method for manufacturing a metal tape and a method for manufacturing a wiring board using the two-metal tape are provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing (1) a basic structure of a two-metal tape to be manufactured according to the present invention, and (2) a structural example of a semiconductor package using the two-metal tape.
FIG. 2 is a sectional view showing a manufacturing process of a two-metal tape according to a conventional method.
FIG. 3 is a sectional view showing a manufacturing process of a two-metal tape according to the present invention.
FIG. 4 is a flowchart showing a manufacturing process of a two-metal tape according to each embodiment of the present invention.
[Explanation of symbols]
100 2 metal tape 102 semiconductor package 104 wiring board 106 semiconductor chip 10 insulating resin base materials 12a and 12b adhesive layer (after curing)
12a ', 12b' ... adhesive layer (before curing)
14a, 14b ... conductor layers 14A, 14B ... wiring pattern 14 '... conductor thin layer (electroless plating layer)
15: Protective film 16: Via 16 ': Via hole 17: Residue 18: External connection terminal 20: Connection bump 21, 22 ... Solder resist 24: Electrode terminal 26: Sealing resin

Claims (4)

絶縁性樹脂基材の両面にそれぞれ第１、第２の接着剤を介して第１、第２の導体層を備え、上記基材と上記第１、第２の接着剤とを貫通するビアにより上記第１、第２の導体層が相互に電気的に接続されている２メタルテープの製造方法において、下記の工程〔１〕〜〔１２〕：
〔１〕絶縁性樹脂基材を準備する工程、
〔２〕絶縁性樹脂基材の一方の面に第１接着剤を塗布する工程、
〔３〕上記第１接着剤の上に第１導体層として導体箔をラミネートする工程、
〔４〕上記第１接着剤を硬化させることにより、上記基板の一方の面に上記第導体箔を接合して第１導体層とする工程、
〔５〕上記基材の他方の面に第２接着剤を塗布する工程、
〔６〕上記導体箔の自由表面に保護皮膜を被覆する工程、
〔７〕上記第２接着剤、上記基材および上記第１接着剤を貫通して上記導体箔により底部が確定されたビア穴を形成する工程、
〔８〕上記ビア穴の内部を乾式クリーニングする工程、
〔９〕上記ビア穴の底部に露出した上記導体箔を給電層とする電解めっきにより上記ビア穴内全体に導体を充填して、該導体箔で底面が画定されたビアを形成する工程、
〔１０〕上記第２接着剤の表面および上記ビアの露出面に、表面粗化処理を施した後に、無電解めっきにより導体の薄層を形成する工程、
〔１１〕上記導体薄層を給電層とする電解めっきにより該導体薄層上に第２導体層を形成する工程、および
〔１２〕上記第２接着剤を硬化させることにより上記基板の他方の面に上記第２導体層を接合する工程
を順次行なうことを特徴とする２メタルテープの製造方法。First and second conductor layers are provided on both surfaces of an insulating resin base material via first and second adhesives, respectively, and vias penetrate the base material and the first and second adhesives. In the method for manufacturing a two-metal tape in which the first and second conductor layers are electrically connected to each other, the following steps [1] to [12]:
[1] a step of preparing an insulating resin base material,
[2] a step of applying a first adhesive to one surface of the insulating resin base material,
[3] a step of laminating a conductor foil as a first conductor layer on the first adhesive;
[4] a step of curing the first adhesive to join the first conductor foil to one surface of the substrate to form a first conductor layer;
[5] a step of applying a second adhesive to the other surface of the base material,
[6] a step of coating the free surface of the conductor foil with a protective film,
[7] a step of penetrating the second adhesive, the base material and the first adhesive to form a via hole whose bottom is defined by the conductor foil;
[8] a step of dry cleaning the inside of the via hole,
[9] a step of filling the entire inside of the via hole with a conductor by electrolytic plating using the conductive foil exposed at the bottom of the via hole as a power supply layer, and forming a via having a bottom surface defined by the conductive foil;
[10] a step of forming a thin layer of a conductor by electroless plating after performing a surface roughening treatment on the surface of the second adhesive and the exposed surface of the via;
[11] a step of forming a second conductor layer on the conductor thin layer by electrolytic plating using the conductor thin layer as a power supply layer, and [12] the other surface of the substrate by curing the second adhesive. And a step of joining the second conductor layer to the second conductor layer sequentially. 上記工程〔９〕に代えて、上記ビア穴内に導電性ペーストを充填することにより、上記ビアを形成することを特徴とする請求項１記載の方法。2. The method according to claim 1, wherein the via is formed by filling the via hole with a conductive paste instead of the step [9]. 上記工程〔１０〕および〔１１〕に代えて、上記第２接着剤の表面および上記ビアの露出面に導体箔をラミネートすることにより、上記第２導体層を形成することを特徴とする請求項１または２記載の方法。The second conductor layer is formed by laminating a conductor foil on the surface of the second adhesive and the exposed surface of the via in place of the steps [10] and [11]. 3. The method according to 1 or 2. 請求項１から３までのいずれか１項記載の方法により製造された２メタルテープの前記第１、第２の導体層をそれぞれパターニングして配線パターンを形成することを特徴とする配線基板の製造方法。4. A method of manufacturing a wiring board, comprising: forming a wiring pattern by patterning the first and second conductor layers of a two-metal tape manufactured by the method according to claim 1. Method.
JP2002263123A 2002-09-09 2002-09-09 Method of manufacturing two metal tapes and wiring substrate Pending JP2004103798A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005335038A (en) * 2004-05-31 2005-12-08 Hitachi High-Technologies Corp Multilayered wiring board and its manufacturing method
KR100690028B1 (en) * 2005-09-23 2007-03-09 (주)한틀시스템 System for handling an envelope
CN104412720A (en) * 2012-05-02 2015-03-11 陶瓷技术有限责任公司 Method for producing ceramic circuit boards from ceramic substrates having metal-filled vias
CN112702848A (en) * 2021-03-24 2021-04-23 成都市克莱微波科技有限公司 Method for cleaning high-frequency flexible microwave printed circuit board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005335038A (en) * 2004-05-31 2005-12-08 Hitachi High-Technologies Corp Multilayered wiring board and its manufacturing method
KR100690028B1 (en) * 2005-09-23 2007-03-09 (주)한틀시스템 System for handling an envelope
CN104412720A (en) * 2012-05-02 2015-03-11 陶瓷技术有限责任公司 Method for producing ceramic circuit boards from ceramic substrates having metal-filled vias
JP2015520944A (en) * 2012-05-02 2015-07-23 セラムテック ゲゼルシャフト ミット ベシュレンクテル ハフツングＣｅｒａｍＴｅｃ ＧｍｂＨ Method for manufacturing a ceramic printed circuit board comprising a ceramic substrate having vias filled with metal
CN112702848A (en) * 2021-03-24 2021-04-23 成都市克莱微波科技有限公司 Method for cleaning high-frequency flexible microwave printed circuit board

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