JP4565861B2 - Wiring board manufacturing method - Google Patents

Wiring board manufacturing method Download PDF

Info

Publication number
JP4565861B2
JP4565861B2 JP2004053001A JP2004053001A JP4565861B2 JP 4565861 B2 JP4565861 B2 JP 4565861B2 JP 2004053001 A JP2004053001 A JP 2004053001A JP 2004053001 A JP2004053001 A JP 2004053001A JP 4565861 B2 JP4565861 B2 JP 4565861B2
Authority
JP
Japan
Prior art keywords
layer
metal foil
dielectric layer
wiring board
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004053001A
Other languages
Japanese (ja)
Other versions
JP2005243999A (en
Inventor
達也 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NGK Spark Plug Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP2004053001A priority Critical patent/JP4565861B2/en
Publication of JP2005243999A publication Critical patent/JP2005243999A/en
Application granted granted Critical
Publication of JP4565861B2 publication Critical patent/JP4565861B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

本発明は、コア基板を有さない配線基板の製造方法に関する。   The present invention relates to a method for manufacturing a wiring board having no core substrate.

近年、電子機器における高機能化並びに軽薄短小化の要求により、ＩＣチップやＬＳＩ等の電子部品では高密度集積化が急速に進んでおり、これに伴い、電子部品を搭載するパッケージ基板には、従来にも増して高密度配線化及び多端子化が求められている。   In recent years, due to the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration has rapidly progressed in electronic components such as IC chips and LSIs. There is a demand for higher-density wiring and multi-terminals than ever before.

このようなパッケージ基板としては、現状において、ビルドアップ多層配線基板が採用されている。ビルドアップ多層配線基板とは、補強繊維に樹脂を含浸させた絶縁性のコア基板（ＦＲ−４等のガラスエポキシ基板）のリジッド性を利用し、その両主表面上に、高分子材料からなる誘電体層と導体層とが交互に配されたビルドアップ層を形成したものである。このようなビルドアップ多層配線基板では、ビルドアップ層において高密度配線化が実現されており、一方、コア基板は補強の役割を果たす。そのため、コア基板は、ビルドアップ層と比べて非常に厚く構成され、またその内部にはそれぞれの主表面に配されたビルドアップ層間の導通を図るための配線（スルーホール導体と呼ばれる）が厚さ方向に貫通形成されている。ところが、使用する信号周波数が１ＧＨｚを超える高周波帯域となってきた現在では、そのような厚いコア基板を貫通する配線は、大きなインダクタンスとして寄与してしまうという問題があった。   As such a package substrate, a build-up multilayer wiring substrate is currently used. The build-up multilayer wiring board uses a rigid property of an insulating core substrate (glass epoxy substrate such as FR-4) in which a reinforcing fiber is impregnated with a resin, and is made of a polymer material on both main surfaces thereof. A build-up layer in which dielectric layers and conductor layers are alternately arranged is formed. In such a build-up multilayer wiring board, high-density wiring is realized in the build-up layer, while the core board plays a reinforcing role. For this reason, the core substrate is configured to be very thick compared to the build-up layer, and the wiring (called a through-hole conductor) for establishing electrical conduction between the build-up layers arranged on the respective main surfaces is thick inside the core substrate. It penetrates in the vertical direction. However, at the present time when the signal frequency to be used has become a high frequency band exceeding 1 GHz, there is a problem that the wiring penetrating such a thick core substrate contributes as a large inductance.

そこで、そのような問題を解決するため、特許文献１に示されるような、コア基板を有さず、高密度配線化が可能なビルドアップ層を主体とした配線基板が提案されている。このような配線基板では、コア基板が省略されているため、全体の配線長が短く構成され、高周波用途に供するのに好適である。このような配線基板を製造するためには、特許文献１の段落００１２〜００２９及び図１〜４に記載されているように、金属板上にビルドアップ層を形成した後、該金属板をエッチングすることにより薄膜のビルドアップ層のみを得る。そして、このビルドアップ層が配線基板とされる。   Therefore, in order to solve such a problem, there has been proposed a wiring board mainly composed of a build-up layer that does not have a core board and can be formed with high density wiring, as shown in Patent Document 1. In such a wiring board, since the core board is omitted, the entire wiring length is short, which is suitable for high-frequency applications. In order to manufacture such a wiring board, as described in paragraphs 0012 to 0029 and FIGS. 1 to 4 of Patent Document 1, after forming a build-up layer on the metal plate, the metal plate is etched. By doing so, only the thin film build-up layer is obtained. This build-up layer is used as a wiring board.

特開２００２−２６１７１号公報JP 2002-26171 A

しかし、特許文献１に記載された製造方法の場合、ビルドアップ層が形成される金属板は、製造時における補強の役割を担うことが可能な程度の厚さ（例えば、銅板にして０．８ｍｍ程度）に設定されるが、ビルドアップ層を形成後にそれを全てエッチングすることは、時間が掛かり過ぎる（例えば、銅板０．８ｍｍに対して３０分程度）など工程上の無駄が多いという問題があった。   However, in the case of the manufacturing method described in Patent Document 1, the metal plate on which the build-up layer is formed has a thickness that can play a reinforcing role at the time of manufacturing (for example, 0.8 mm in the case of a copper plate). However, it takes too much time (for example, about 30 minutes for a copper plate of 0.8 mm) to etch all of the build-up layer after forming it. there were.

そこで、本発明では、コア基板を有さず、高分子材料からなる誘電体層と導体層とが交互に積層された配線基板を容易に得ることが可能な製造方法を提供することを課題とする。   Therefore, the present invention has an object to provide a manufacturing method capable of easily obtaining a wiring substrate in which dielectric layers and conductor layers made of a polymer material are alternately laminated without having a core substrate. To do.

課題を解決するための手段・発明の効果Means for solving the problems / effects of the invention

上記課題を解決するため、本発明の配線基板の製造方法では、
コア基板を有さず、かつ両主表面が誘電体層にて構成されるように、高分子材料からなる誘電体層と導体層とが交互に積層され、前記主表面の一方に、電子部品と接続するためのハンダで構成された金属端子を有する配線基板を製造するために、
製造時における補強のための支持基板上に下地誘電体層を介して加熱により接着力が低下する、基材シートに固定される加熱剥離性接着層を、前記基材シートが前記下地誘電体層側とされるように配し、該加熱剥離性接着層と前記誘電体層との間に金属箔層を介して前記配線基板となるべき配線積層部を積層形成した後、前記誘電体層の硬化温度よりも高温で、且つ、前記金属端子のハンダの融点よりも低温で剥離用加熱処理を行い、前記配線積層部の前記金属箔層と前記加熱剥離性接着層との界面から剥離した後、前記金属箔層を除去することを特徴とする。 In order to solve the above problems, in the method for manufacturing a wiring board of the present invention,
A dielectric layer made of a polymer material and a conductor layer are alternately laminated so as not to have a core substrate and both main surfaces are composed of dielectric layers, and an electronic component is formed on one of the main surfaces. In order to manufacture a wiring board having metal terminals composed of solder for connecting with
A heat-peelable adhesive layer fixed to a base material sheet whose adhesive strength is reduced by heating on a support substrate for reinforcement during manufacture, which is fixed to the base material sheet, wherein the base material sheet is the base dielectric layer. A wiring laminated portion to be the wiring board is interposed between the heat-peelable adhesive layer and the dielectric layer via a metal foil layer, and then the dielectric layer After performing heat treatment for peeling at a temperature higher than the curing temperature and lower than the melting point of the solder of the metal terminal, after peeling from the interface between the metal foil layer and the heat-peelable adhesive layer of the wiring laminated portion The metal foil layer is removed .

上記本発明によると、配線基板となるべき配線積層部の積層形成に際して、配線積層部と支持基板との間に加熱により接着力が低下する加熱剥離性接着層を介在させている。これにより、配線積層部と支持基板との界面において、誘電体層の膨れや剥れを生じさせることなく、配線積層部を積層形成することができる。そしてその後、剥離用加熱処理を行うことで、配線積層部を支持基板から容易に剥離することができる。つまり、このように構成することにより、密着性が要求される配線積層部の積層形成と、剥離容易性が要求される配線積層部の分離とを、どちらも良好に行うことが可能となるのである。
また、金属箔層と加熱剥離性接着層との界面を剥離界面とすることで剥離性が向上するとともに、金属箔層を介すことで剥離の際に加熱剥離性接着層の一部が誘電体層に付着するのを防止することができる。また、誘電体層の硬化温度よりも剥離用加熱処理温度が低温であれば、配線積層部の積層形成途中に加熱剥離性接着層の接着性が低下していく惧れが生じる。例えば、エポキシ樹脂の硬化温度は１７０℃程度であるので、誘電体層がエポキシ樹脂にて構成されている場合には、剥離用加熱処理は１７０℃以上の温度で行われることが好ましい。
また、前記金属箔層と前記加熱剥離性接着層との界面からの剥離は、前記金属箔層に積層される前記誘電体層における積層面と反対側の表面上に導体層をパターン形成するように配線積層部の形成を行った後に行い、その後、前記金属箔層を除去した後、前記誘電体層を穿孔した個所に前記導体層と接続される金属端子を形成してもよい。
また、前記金属箔層に積層される誘電体層において、前記金属箔層に接続されるように導体充填材を形成した後、前記誘電体層における前記金属箔層との積層面と反対側の表面上に導体層をパターン形成するように配線積層部の形成を行った後、前記金属箔層と前記加熱剥離性接着層との界面にて剥離を行い、その後、金属箔層を除去することにより、その除去面に前記パターン形成される前記導体層と接続された前記導体充填材が現れ、そこに前記金属端子を形成するようにしてもよい。
また、前記金属端子を有する前記主表面には、補強枠が設置されるとしてもよい、また、前記金属端子を有する誘導体層を、他の誘電体層よりも熱膨張率の小さい材料にて構成するとしてもよい。 According to the present invention, when the wiring laminated portion to be the wiring substrate is laminated, the heat-peelable adhesive layer whose adhesive force is reduced by heating is interposed between the wiring laminated portion and the support substrate. As a result, the wiring laminated portion can be laminated and formed without causing the dielectric layer to swell or peel off at the interface between the wiring laminated portion and the support substrate. Then, by performing a heat treatment for peeling, the wiring laminated portion can be easily peeled from the support substrate. In other words, with this configuration, it is possible to satisfactorily perform both the lamination formation of the wiring lamination portion requiring adhesion and the separation of the wiring lamination portion requiring ease of peeling. is there.
In addition, the peelability is improved by setting the interface between the metal foil layer and the heat-peelable adhesive layer as a peel interface, and part of the heat-peelable adhesive layer is dielectric when peeled via the metal foil layer. It can prevent adhering to the body layer. Further, if the heat treatment temperature for peeling is lower than the curing temperature of the dielectric layer, there is a concern that the adhesiveness of the heat-peelable adhesive layer may be lowered during the formation of the wiring laminated portion. For example, since the curing temperature of the epoxy resin is about 170 ° C., when the dielectric layer is made of an epoxy resin, the heat treatment for peeling is preferably performed at a temperature of 170 ° C. or higher.
The peeling from the interface between the metal foil layer and the heat-peelable adhesive layer may be performed by patterning a conductor layer on the surface opposite to the laminated surface of the dielectric layer laminated on the metal foil layer. After forming the wiring laminated portion, after removing the metal foil layer, a metal terminal connected to the conductor layer may be formed at a location where the dielectric layer is perforated.
Further, in the dielectric layer laminated on the metal foil layer, after forming a conductor filler so as to be connected to the metal foil layer, the dielectric layer on the side opposite to the lamination surface with the metal foil layer is formed . After forming the wiring laminated portion so as to pattern the conductor layer on the surface, peeling off at the interface between the metal foil layer and the heat-peelable adhesive layer, and then removing the metal foil layer Thus, the conductor filler connected to the conductor layer to be patterned may appear on the removal surface, and the metal terminal may be formed there .
Further, a reinforcing frame may be provided on the main surface having the metal terminal, and the dielectric layer having the metal terminal is made of a material having a smaller coefficient of thermal expansion than other dielectric layers. You may do that.

以下、本発明の実施の形態について、図面を参照して説明する。
図４は、本発明の配線基板１の断面構造の概略を表す図である。配線基板１は、高分子材料からなる誘電体層（Ｂ１〜Ｂ３、ＳＲ）と導体層（Ｍ１、Ｍ２、ＰＤ）とが交互に積層された構造を有する。その第一主表面ＭＰ１は電子部品を搭載するための搭載面とされ、主表面をなす第一誘電体層Ｂ１には、電子部品と接続するための、周知のハンダで構成された突起状の金属端子（ハンダバンプ）ＦＢが形成されている。また、第二主表面ＭＰ２は、外部基板へ接続するための接続面とされ、主表面をなす誘電体層（ソルダーレジスト層）ＳＲには開口が形成されており、該開口内には外部基板への接続を担うハンダボール（後述）を設置するための金属端子（金属パッド）ＰＤが露出している。 Embodiments of the present invention will be described below with reference to the drawings.
FIG. 4 is a diagram showing an outline of a cross-sectional structure of the wiring board 1 of the present invention. The wiring substrate 1 has a structure in which dielectric layers (B1 to B3, SR) made of a polymer material and conductor layers (M1, M2, PD) are alternately stacked. The first main surface MP1 is a mounting surface for mounting an electronic component, and the first dielectric layer B1 forming the main surface has a protruding shape made of a well-known solder for connecting to the electronic component. Metal terminals (solder bumps) FB are formed. The second main surface MP2 is a connection surface for connecting to an external substrate, and an opening is formed in the dielectric layer (solder resist layer) SR forming the main surface, and the external substrate is in the opening. A metal terminal (metal pad) PD for installing a solder ball (described later) that bears the connection to is exposed.

また、金属層Ｍ１、Ｍ２において配線ＣＬが形成されており、誘電体層Ｂ１〜Ｂ３内には該配線ＣＬに接続されるビア導体ＶＡが埋設形成されている。そして、配線ＣＬ及びビア導体ＶＡにより、電気導通路（例えばハンダバンプＦＢから金属パッドＰＤへの）が形成される。なお、配線ＣＬ、ビア導体ＶＡ及び金属パッドＰＤは、例えば銅を主成分とする材料にて構成することができる。また、金属パッドＰＤは、その表面に例えばＮｉ−Ａｕメッキによる表面メッキを施すことができる。   A wiring CL is formed in the metal layers M1 and M2, and a via conductor VA connected to the wiring CL is embedded in the dielectric layers B1 to B3. An electric conduction path (for example, from the solder bump FB to the metal pad PD) is formed by the wiring CL and the via conductor VA. Note that the wiring CL, the via conductor VA, and the metal pad PD can be made of, for example, a material mainly composed of copper. Further, the surface of the metal pad PD can be subjected to surface plating by Ni—Au plating, for example.

以上のような配線基板１は、図５に示すように、第二主表面ＭＰ２の金属パッドＰＤに外部基板への接続を担うハンダボールＳＢが設置され、一方、第一主表面ＭＰ１には、補強枠（スティフナー）ＳＴが設置されるとともに、電子部品ＩＣがハンダバンプＦＢにフリップチップ接続され、また電子部品ＩＣ下の隙間がアンダーフィル材ＵＦにて充填されることで、半導体装置３００となる。   As shown in FIG. 5, the wiring board 1 as described above is provided with solder balls SB that are connected to an external substrate on the metal pad PD of the second main surface MP2, while the first main surface MP1 has The reinforcing frame (stiffener) ST is installed, the electronic component IC is flip-chip connected to the solder bump FB, and the gap under the electronic component IC is filled with the underfill material UF, so that the semiconductor device 300 is obtained.

なお、配線基板１では、電子部品ＩＣとハンダバンプＦＢとの接続信頼性を上げるため、第一主表面ＭＰ１をなす第一誘電体層Ｂ１を、他の誘電体層Ｂ２、Ｂ３、ＳＲよりも熱膨張率の小さい材料にて構成することができる。すなわち、配線基板１では、コア基板を有さず、かつ両主表面が誘電体層にて構成されるよう、高分子材料からなる誘電体層と導体層とが交互に積層され、かつ第一主表面ＭＰ１が電子部品を搭載するための搭載面とされるとともに、誘電体層Ｂ１〜Ｂ３、ＳＲのうち、該第一主表面ＭＰ１を構成する誘電体層Ｂ１は、他の誘電体層Ｂ２、Ｂ３、ＳＲよりも熱膨張係数の低い材料にて構成することができる。   In the wiring board 1, in order to increase the connection reliability between the electronic component IC and the solder bump FB, the first dielectric layer B1 forming the first main surface MP1 is heated more than the other dielectric layers B2, B3, SR. It can be made of a material having a small expansion coefficient. That is, in the wiring board 1, the dielectric layers made of a polymer material and the conductor layers are alternately laminated so as not to have a core substrate and both main surfaces are constituted by dielectric layers, and the first The main surface MP1 is used as a mounting surface for mounting electronic components, and among the dielectric layers B1 to B3, SR, the dielectric layer B1 constituting the first main surface MP1 is another dielectric layer B2. , B3, SR, and a material having a lower thermal expansion coefficient.

また、配線基板１では、電子部品ＩＣとハンダバンプＦＢとの接続信頼性を上げるため、第一主表面ＭＰ１をなす第一誘電体層Ｂ１を、他の誘電体層Ｂ２、Ｂ３、ＳＲよりもヤング率の小さい材料にて構成することができる。すなわち、配線基板１では、コア基板を有さず、かつ両主表面が誘電体層にて構成されるよう、高分子材料からなる誘電体層と導体層とが交互に積層され、かつ第一主表面ＭＰ１が電子部品を搭載するための搭載面とされるとともに、誘電体層Ｂ１〜Ｂ３、ＳＲのうち、該第一主表面ＭＰ１を構成する誘電体層Ｂ１は、他の誘電体層Ｂ２、Ｂ３、ＳＲよりもヤング率の低い材料にて構成することができる。   Further, in the wiring board 1, in order to increase the connection reliability between the electronic component IC and the solder bump FB, the first dielectric layer B1 forming the first main surface MP1 is made younger than the other dielectric layers B2, B3, SR. It can be made of a material with a low rate. That is, in the wiring board 1, the dielectric layers made of a polymer material and the conductor layers are alternately laminated so as not to have a core substrate and both main surfaces are constituted by dielectric layers, and the first The main surface MP1 is used as a mounting surface for mounting electronic components, and among the dielectric layers B1 to B3, SR, the dielectric layer B1 constituting the first main surface MP1 is another dielectric layer B2. , B3, and SR can be made of a material having a lower Young's modulus.

以上の条件を満たす組み合わせとしては、例えば、他の誘電体層Ｂ２、Ｂ３、ＳＲがエポキシ樹脂を主成分として構成されている場合、第一主表面ＭＰ１に形成される誘電体層Ｂ１を例えば、ポリイミド、アラミド、ポリエチレン、ポリプロピレン、ポリエチレンテレフタレート、ポリテトラフルオロエチレン等を主成分として構成することができる。   As a combination that satisfies the above conditions, for example, when the other dielectric layers B2, B3, and SR are mainly composed of an epoxy resin, the dielectric layer B1 formed on the first main surface MP1 is, for example, Polyimide, aramid, polyethylene, polypropylene, polyethylene terephthalate, polytetrafluoroethylene, or the like can be used as a main component.

以下、本発明の実施形態である配線基板の製造方法の一例を説明する。図１〜図３は製造工程を表す図である。工程１〜５に示す支持基板２０上に配線積層部１００を形成していく工程は、周知のビルドアップ法等により行うことができる。まず、図１の工程１に示すように、製造時における補強のための支持基板２０上に下地誘電体層２１を形成する。支持基板２０は、特には限定されないが、例えばＦＲ−４等のガラスエポキシ基板（上述のようにコア基板に用いられる材料である）にて構成することができる。また、下地誘電体層２１は、後述する複層シート５を密着させるためのものであり、例えばエポキシ樹脂を主成分とする材料にて構成することができる。   Hereinafter, an example of the manufacturing method of the wiring board which is embodiment of this invention is demonstrated. 1 to 3 are diagrams showing a manufacturing process. The step of forming the wiring laminated portion 100 on the support substrate 20 shown in steps 1 to 5 can be performed by a known build-up method or the like. First, as shown in step 1 of FIG. 1, a base dielectric layer 21 is formed on a support substrate 20 for reinforcement during manufacturing. Although it does not specifically limit, the support substrate 20 can be comprised with glass epoxy substrates (it is a material used for a core board | substrate as mentioned above), such as FR-4, for example. Moreover, the base dielectric layer 21 is for making the multilayer sheet 5 mentioned later contact | adhere, for example, can be comprised with the material which has an epoxy resin as a main component.

次に、工程２に示すよう、下地誘電体層２１上に加熱剥離性接着層５１を介して第一誘電体層１１を配す。加熱剥離性接着層５１と第一誘電体層１１とは密着しており、この界面が後の剥離工程（工程６）の際の剥離界面となる。具体的には、加熱剥離性接着層５１の土台となる基材シート５２と、加熱剥離性接着層５１と、第一誘電体層１１とがこの順に積層された複層シート５を用いることができる。加熱剥離性接着層５１は、基材シート５２に固定されており、剥離の際には、第一誘電体層１１と、加熱剥離性接着層５１及び基材シート５２とに分離する。なお、複層シート５は、半硬化状態の下地誘電体層２１上に配すようにすることができる。これにより、以降の工程で複層シート５が下地誘電体層２１から剥れない程度の密着性が得られやすくなる。また、第一誘電体層１１は、例えば、ポリイミド、アラミド、ポリエチレン、ポリプロピレン、ポリエチレンテレフタレート、ポリテトラフルオロエチレン等にて構成される樹脂フィルムを用いることができる。   Next, as shown in step 2, the first dielectric layer 11 is disposed on the base dielectric layer 21 via the heat-peelable adhesive layer 51. The heat-peelable adhesive layer 51 and the first dielectric layer 11 are in close contact with each other, and this interface serves as a peeling interface in the subsequent peeling step (step 6). Specifically, it is possible to use a multilayer sheet 5 in which a base sheet 52 as a base of the heat-peelable adhesive layer 51, the heat-peelable adhesive layer 51, and the first dielectric layer 11 are laminated in this order. it can. The heat-peelable adhesive layer 51 is fixed to the base material sheet 52, and is separated into the first dielectric layer 11, the heat-peelable adhesive layer 51, and the base material sheet 52 at the time of peeling. The multilayer sheet 5 can be disposed on the semi-cured base dielectric layer 21. Thereby, it becomes easy to obtain adhesiveness to such an extent that the multilayer sheet 5 does not peel from the underlying dielectric layer 21 in the subsequent steps. The first dielectric layer 11 may be a resin film made of, for example, polyimide, aramid, polyethylene, polypropylene, polyethylene terephthalate, polytetrafluoroethylene, or the like.

次に、工程３に示すように、第一誘電体層１１上に第一導体層３１を形成する。そして、図２の工程４に示すように、第一誘電体層１１及び第一導体層３１上に第二誘電体層１２を形成し、その後、第二誘電体層１２内に第二ビア導体４２、第二誘電体層１２上に第二導体層３２を形成する。なお、第二誘電体層１２以降の誘電体層の形成は、例えば周知の真空ラミネーション法を用いることができる。導体層の形成は、例えば周知のセミアディティブ法により形成することができる。また、ビア導体は、例えば周知のフォトビアプロセスによりビア孔を形成し、該ビア孔を、上記セミアディティブ法における無電解メッキによって充填することにより得ることができる。   Next, as shown in step 3, the first conductor layer 31 is formed on the first dielectric layer 11. Then, as shown in Step 4 of FIG. 2, the second dielectric layer 12 is formed on the first dielectric layer 11 and the first conductor layer 31, and then the second via conductor is formed in the second dielectric layer 12. 42, the second conductor layer 32 is formed on the second dielectric layer 12. For example, a known vacuum lamination method can be used to form the dielectric layers after the second dielectric layer 12. The conductor layer can be formed, for example, by a known semi-additive method. The via conductor can be obtained, for example, by forming a via hole by a well-known photo via process and filling the via hole by electroless plating in the semi-additive method.

そして、同様の工程を繰り返して、誘電体層１３、１４、ビア導体４３、導体層３３を第二誘電体層１２上に形成し、工程５に示すような配線積層部１００を形成する。なお、本実施形態では、配線積層部１００を構成する誘電体層は誘電体層１１〜１４の４層であるが、これに限られることはない。以上により、支持基板２０上に、加熱により接着力が低下する加熱剥離性接着層５１を介して上述の配線基板となるべき配線積層部１００が形成される。なお、誘電体層１２〜１４は、エポキシを主成分とする材料にて構成することができる。また、導体層３１〜３３とビア導体４２、４３は銅を主成分として構成することができる。   Then, the same steps are repeated to form the dielectric layers 13 and 14, the via conductors 43, and the conductor layers 33 on the second dielectric layer 12, thereby forming the wiring laminated portion 100 as shown in step 5. In the present embodiment, the dielectric layers constituting the wiring laminated portion 100 are the four layers of the dielectric layers 11 to 14, but are not limited to this. As described above, the wiring laminated portion 100 to be the above-described wiring substrate is formed on the support substrate 20 via the heat-peelable adhesive layer 51 whose adhesive strength is reduced by heating. The dielectric layers 12 to 14 can be made of a material mainly composed of epoxy. The conductor layers 31 to 33 and the via conductors 42 and 43 can be composed mainly of copper.

また、本実施形態では第一誘電体層１１を、第二〜第四誘電体層を構成する材料よりも熱膨張係数及びヤング率の低い樹脂フィルムにて構成しているが、これに限らず、例えば支持基板２０上に加熱剥離性接着層５１を単独（もしくは基材シート５２と）で配し、その上に同一材料（例えば、エポキシを主成分とする材料）からなる誘電体層１１〜１４を例えば周知の真空ラミネーション法により形成することも可能である。   In the present embodiment, the first dielectric layer 11 is composed of a resin film having a lower coefficient of thermal expansion and Young's modulus than the material constituting the second to fourth dielectric layers, but is not limited thereto. For example, the heat-peelable adhesive layer 51 is arranged alone (or with the base material sheet 52) on the support substrate 20, and the dielectric layers 11 to 11 made of the same material (for example, a material mainly composed of epoxy) are provided thereon. 14 can be formed by, for example, a known vacuum lamination method.

また、本実施形態では、配線積層部１００の上側の露出した主表面が、図４に示す配線基板１の第二主表面ＭＰ２となるように形成されている。したがって、配線積層部１００の上側主表面をなす誘電体層１４は、図４の配線基板１のソルダーレジスト層ＳＲに該当し、またその開口１４ａ内に露出する導体層３３は、図４の配線基板１の金属パッドＰＤに該当する。なお、これとは反対に上側主表面を、図４に示す配線基板１の第一主表面ＭＰ１とすることもできる。その場合は、上側主表面をなす誘電体層１４に、図４に示すハンダバンプＦＢを形成する。   In the present embodiment, the exposed main surface on the upper side of the wiring laminated portion 100 is formed to be the second main surface MP2 of the wiring board 1 shown in FIG. Therefore, the dielectric layer 14 forming the upper main surface of the wiring laminated portion 100 corresponds to the solder resist layer SR of the wiring substrate 1 of FIG. 4, and the conductor layer 33 exposed in the opening 14a is the wiring layer of FIG. This corresponds to the metal pad PD of the substrate 1. On the other hand, the upper main surface can be the first main surface MP1 of the wiring board 1 shown in FIG. In that case, the solder bump FB shown in FIG. 4 is formed on the dielectric layer 14 forming the upper main surface.

次に、剥離用加熱処理を行い、工程６に示すように、配線積層部１００を支持基板２０から、第一誘電体層１１と加熱剥離性接着層５１との界面にて剥離する。この際、加熱剥離性接着層５１は、基材シート５２側に残る。そして、配線積層部１００を支持基板２０から剥離した後に、該配線積層部１００の主表面を構成する第一誘電体層１１を穿孔し（図３の工程７）、該主表面に内部の導体層３１と接続された金属端子８（図４の配線基板１ではハンダバンプＦＢ）を形成する（工程８）ことで配線基板１が完成する。なお、工程１１において、第一誘電体層１１を穿孔することによる開口１１ａの形成は、例えば、ＵＶレーザーやＹＡＧレーザー等の周知のレーザーを用いて行うことができる。   Next, a heat treatment for peeling is performed, and as shown in Step 6, the wiring laminated portion 100 is peeled from the support substrate 20 at the interface between the first dielectric layer 11 and the heat-peelable adhesive layer 51. At this time, the heat-peelable adhesive layer 51 remains on the substrate sheet 52 side. Then, after the wiring laminated portion 100 is peeled from the support substrate 20, the first dielectric layer 11 constituting the main surface of the wiring laminated portion 100 is drilled (step 7 in FIG. 3), and an internal conductor is formed on the main surface. By forming metal terminals 8 (solder bumps FB in the wiring substrate 1 of FIG. 4) connected to the layer 31 (step 8), the wiring substrate 1 is completed. In step 11, the opening 11a can be formed by perforating the first dielectric layer 11, for example, using a known laser such as a UV laser or a YAG laser.

また、工程８において、金属端子８を形成する際、開口１１ａの深さ（第一誘電体層１１の厚み）によっては、導体層３１と直接接続することが困難な場合があるので、その間に例えばハンダよりなる導体充填材４１を介在させることが可能である。   Further, in forming the metal terminal 8 in the step 8, depending on the depth of the opening 11a (the thickness of the first dielectric layer 11), it may be difficult to directly connect to the conductor layer 31. For example, it is possible to interpose a conductor filler 41 made of solder.

加熱剥離性接着層５１は、発泡剤を含有し、剥離用加熱処理により当該発泡剤が膨脹ないし発泡することにより接着力が低下するものを用いることができる。発泡剤としては有機系や無機系の適宜なものを用いることができる。一般に用いられる無機系発泡剤の代表例としては、炭酸アンモニウム、炭酸水素アンモニウム、炭酸水素ナトリウム、亜硝酸アンモニウム、水素化ホウ素ナトリウム、アジド類などが挙げられる。有機系発泡剤の代表例としては、トリクロロモノフルオロメタンやジクロロモノフルオロメタンの如きフッ化アルカン、アゾビスイソブチロニトリルやアゾジカルボンアミド、バリウムアゾジカルボキシレートの如きアゾ系化合物、パラトルエンスルホニルヒドラジドやジフェニルスルホン−３，３'−ジスルホニルヒドラジド、４，４'−オキシビス（ベンゼンスルホニルヒドラジド）、アリルビス（スルホニルヒドラジド）の如きヒドラジン系化合物、ρ−トルイレンスルホニルセミカルバジドや４，４'−オキシビス（ベンゼンスルホニルセミカルバジド）の如きセミカルバジド系化合物、５−モルホリル−１，２，３，４−チアトリアゾールの如きトリアゾール系化合物、Ｎ，Ｎ'−ジニトロソペンタメチレンテトラミンやＮ，Ｎ'−ジメチル−Ｎ，Ｎ'−ジニトロソテレフタルアミドの如きＮ−ニトロソ系化合物などが挙げられる。また、加熱剥離性接着層５１に接着力を付与するために含有させる接着性付与樹脂としては、例えばロジンやその誘導体類、ポリテルペン類、石油系樹脂やその水添物類、シクロペンタジエン系石油樹脂類、スチレン系石油樹脂類、クマロンインデン系樹脂類などの適宜なものを用いることができる。   The heat-peelable adhesive layer 51 may contain a foaming agent, and the adhesive strength is reduced when the foaming agent expands or foams by the heat treatment for peeling. As the foaming agent, appropriate organic or inorganic materials can be used. Representative examples of commonly used inorganic foaming agents include ammonium carbonate, ammonium hydrogen carbonate, sodium hydrogen carbonate, ammonium nitrite, sodium borohydride, azides and the like. Representative examples of organic foaming agents include fluorinated alkanes such as trichloromonofluoromethane and dichloromonofluoromethane, azo compounds such as azobisisobutyronitrile, azodicarbonamide, barium azodicarboxylate, and paratoluenesulfonyl. Hydrazine compounds such as hydrazide, diphenylsulfone-3,3′-disulfonylhydrazide, 4,4′-oxybis (benzenesulfonylhydrazide), allylbis (sulfonylhydrazide), ρ-toluylenesulfonyl semicarbazide and 4,4′-oxybis Semicarbazide compounds such as (benzenesulfonyl semicarbazide), triazole compounds such as 5-morpholyl-1,2,3,4-thiatriazole, N, N′-dinitrosopentamethylenetetramine and N, N′-dimethyl. And N-nitroso compounds such as ru-N, N′-dinitrosotephthalamide. Examples of the adhesion-imparting resin to be included for imparting adhesive force to the heat-peelable adhesive layer 51 include rosin and derivatives thereof, polyterpenes, petroleum resins and hydrogenated products thereof, and cyclopentadiene petroleum resins. , Styrene-based petroleum resins, coumarone-indene-based resins, and the like can be used.

また、加熱剥離性接着層５１は、接着時の接着力が３５０（N/20mm）以上４５０（N/20mm）以下であることが好ましい。誘電体層１１との界面で膨れや剥れを生じることなく配線積層部１００を積層形成するためには、接着時の接着力が３５０（N/20mm）以上であることが好ましい。一方、４５０（N/20mm）を超えるとその効果は飽和するので上限を４５０（N/20mm）とする。さらには、接着時の接着力が３７０（N/20mm）以上４００（N/20mm）以下である場合がより好ましい。   The heat-peelable adhesive layer 51 preferably has an adhesive force of 350 (N / 20 mm) or more and 450 (N / 20 mm) or less during bonding. In order to laminate and form the wiring laminate 100 without causing swelling or peeling at the interface with the dielectric layer 11, it is preferable that the adhesive force during adhesion is 350 (N / 20 mm) or more. On the other hand, if it exceeds 450 (N / 20 mm), the effect is saturated, so the upper limit is set to 450 (N / 20 mm). Furthermore, the case where the adhesive force at the time of adhesion is 370 (N / 20 mm) or more and 400 (N / 20 mm) or less is more preferable.

また、剥離用加熱処理は、誘電体層１１〜１４の硬化（キュア）温度よりも高温で、且つ、配線基板１の接続端子８（図４の配線基板１及び図３の工程８参照）として用いられるハンダの融点よりも低温で行われることが好ましい。誘電体層１１〜１４の形成は、周知の真空ラミネーション法を用いる場合、半硬化状態で配された後に硬化（キュア）のための熱処理が行われる。したがって、誘電体層１１〜１４の硬化（キュア）温度よりも剥離用加熱処理温度が低温であれば、配線積層部１００の積層形成途中に加熱剥離性接着層５１の接着性が低下していく惧れが生じる。例えば、エポキシ樹脂の硬化（キュア）温度は１７０℃程度であるので、誘電体層１１〜１４（もしくは１２〜１４）がエポキシ樹脂にて構成されている場合には、剥離用加熱処理は１７０℃以上の温度で行われることが好ましい。一方、剥離用加熱処理が過度に高温の場合は、誘電体層１１〜１４の特性に変質をきたすことがあるので、製造工程において配線積層部１００に印加される温度の中で最も高い温度、すなわち接続端子８の形成工程時の温度（ハンダ溶融温度）よりも低温であることが好ましい。具体的には、Ｓｎ−Ｐｂ共晶ハンダでは融点が２１０℃程度、Ｓｎ−Ａｇ共晶ハンダでは融点が２５０℃程度である。   Further, the heat treatment for peeling is higher than the curing (curing) temperature of the dielectric layers 11 to 14 and as connection terminals 8 of the wiring board 1 (see the wiring board 1 in FIG. 4 and the step 8 in FIG. 3). It is preferable to be performed at a temperature lower than the melting point of the solder used. When the well-known vacuum lamination method is used to form the dielectric layers 11 to 14, a heat treatment for curing is performed after being disposed in a semi-cured state. Accordingly, when the heat treatment temperature for peeling is lower than the curing (curing) temperature of the dielectric layers 11 to 14, the adhesiveness of the heat-peelable adhesive layer 51 is lowered during the lamination of the wiring laminated portion 100. A fear arises. For example, since the curing (curing) temperature of the epoxy resin is about 170 ° C., when the dielectric layers 11 to 14 (or 12 to 14) are made of epoxy resin, the heat treatment for peeling is 170 ° C. It is preferable to carry out at the above temperature. On the other hand, when the heat treatment for peeling is excessively high, the characteristics of the dielectric layers 11 to 14 may be deteriorated. Therefore, the highest temperature among the temperatures applied to the wiring laminated portion 100 in the manufacturing process, That is, the temperature is preferably lower than the temperature (solder melting temperature) at the time of forming the connection terminal 8. Specifically, the melting point of Sn—Pb eutectic solder is about 210 ° C., and the melting point of Sn—Ag eutectic solder is about 250 ° C.

なお、以上の製造工程では、図６に示すように、配線積層部１００は、一つの配線基板に対応する個体１００´が複数連結されたもの、つまり、配線基板１の多数個取りワーク基板として構成することができる。   In the above manufacturing process, as shown in FIG. 6, the wiring stacking unit 100 is formed by connecting a plurality of individual pieces 100 ′ corresponding to one wiring board, that is, as a multi-piece work board of the wiring board 1. Can be configured.

以上の実施例では加熱剥離性接着層５１と第一誘電体層１１とが密着していたが、図７または図８に示すように、加熱剥離性接着層５１と第一誘電体層１１との間に金属箔層５３を介挿させることもできる。この場合、配線積層部１００は、当該金属箔層５３と加熱剥離性接着層５１との界面にて支持基板２０から剥離される。なお、金属箔層５３は、剥離後に除去されることとなる。このように金属箔層５３と加熱剥離性接着層５１との界面を剥離界面とすることで剥離性が向上するとともに、金属箔層５３を介すことで剥離の際に加熱剥離性接着層５１の一部が第一誘電体層１１に付着するのを防止することができる。   In the above embodiment, the heat-peelable adhesive layer 51 and the first dielectric layer 11 are in close contact, but as shown in FIG. 7 or FIG. 8, the heat-peelable adhesive layer 51 and the first dielectric layer 11 The metal foil layer 53 can be interposed between the two. In this case, the wiring laminated portion 100 is peeled from the support substrate 20 at the interface between the metal foil layer 53 and the heat-peelable adhesive layer 51. The metal foil layer 53 is removed after peeling. In this way, the peelability is improved by setting the interface between the metal foil layer 53 and the heat-peelable adhesive layer 51 as the peel interface, and the heat-peelable adhesive layer 51 is peeled off when the metal foil layer 53 is interposed. Can be prevented from adhering to the first dielectric layer 11.

具体的には、加熱剥離性接着層５１の土台となる基材シート５２と、加熱剥離性接着層５１と、金属箔層５３と、第一誘電体層１１とがこの順に積層された複層シート５´を用いることができる。該複層シート５´は、上記実施形態と同様に支持基板２０上に配される。   Specifically, a multi-layer in which a base sheet 52 as a base of the heat-peelable adhesive layer 51, the heat-peelable adhesive layer 51, the metal foil layer 53, and the first dielectric layer 11 are laminated in this order. A sheet 5 'can be used. The multilayer sheet 5 ′ is disposed on the support substrate 20 in the same manner as in the above embodiment.

このような複層シート５´を用いた場合、上述した図１〜１０の工程１〜１１の製造工程は、以下のように変形することができる。なお、異なる部分のみ抜粋して説明する。図７の工程３´ａに示すように、支持基板２０に形成された下地誘電体層２１上に、第一誘電体層１１が上側となるように複層シート５´を配し、該第一誘電体層１１の主表面上に第一導体層３１をパターン形成する。その後図２の工程４及び５のごとく配線積層部１００の形成を行った後、図７の工程６´ａ（１）に示すように、金属箔層５３と加熱剥離性接着層５１との界面にて剥離を行う。すなわち、配線積層部１００は金属箔層５３が付随した状態で剥離される。金属箔層５３は、工程６´ａ（２）に示すように、エッチング等によって除去される。その後、図３に示すように、配線積層部１００の主表面を構成する第一誘電体層１１を穿孔し、該主表面に内部の導体層３１と接続された金属端子８を形成することで配線基板１が完成する。   When such a multilayer sheet 5 ′ is used, the above-described manufacturing steps 1 to 11 in FIGS. 1 to 10 can be modified as follows. Only the different parts are extracted and described. As shown in Step 3′a of FIG. 7, a multilayer sheet 5 ′ is arranged on the base dielectric layer 21 formed on the support substrate 20 so that the first dielectric layer 11 is on the upper side. The first conductor layer 31 is patterned on the main surface of the dielectric layer 11. Then, after forming the wiring laminated portion 100 as in steps 4 and 5 of FIG. 2, as shown in step 6′a (1) of FIG. 7, the interface between the metal foil layer 53 and the heat-peelable adhesive layer 51 is formed. Strip with. That is, the wiring laminated portion 100 is peeled off with the metal foil layer 53 attached. The metal foil layer 53 is removed by etching or the like as shown in Step 6′a (2). Thereafter, as shown in FIG. 3, the first dielectric layer 11 constituting the main surface of the wiring laminated portion 100 is perforated, and the metal terminal 8 connected to the internal conductor layer 31 is formed on the main surface. The wiring board 1 is completed.

また、図８の工程３´ｂに示すように、第一誘電体層１１において、金属箔層５３に接続されるよう第一ビア導体４１（上記導体充填材４１に当たる）を形成し、その後第一導体層３１を形成することができる。この場合、剥離後に金属箔層５３を除去する際、工程６´ｂ（２）に示すように、除去面に第一導体層３１と接続された第一ビア導体４１を有する開口１１ａが現れ、そこに金属端子８を直接形成することができる。これにより、剥離後の薄く軟らかい配線積層部１００に対して、第一誘電体層１１´の穿孔したり、その孔を導体（例えば、予備ハンダ）で充填する等の作業を行うことなく金属端子８を形成することが可能となる。   Further, as shown in Step 3′b of FIG. 8, in the first dielectric layer 11, the first via conductor 41 (which hits the conductor filler 41) is formed so as to be connected to the metal foil layer 53, and then the first One conductor layer 31 can be formed. In this case, when removing the metal foil layer 53 after peeling, as shown in step 6′b (2), the opening 11a having the first via conductor 41 connected to the first conductor layer 31 appears on the removal surface, The metal terminal 8 can be directly formed there. As a result, the metal terminal can be formed without performing operations such as perforating the first dielectric layer 11 ′ and filling the hole with a conductor (for example, spare solder) in the thin and soft wiring laminated portion 100 after peeling. 8 can be formed.

なお、金属箔層５３の除去を化学エッチング処理により行う場合、該金属箔層５３と第一ビア導体４１とが異なる金属にて構成され、かつエッチング液が金属箔５３のみを選択的に除去することが可能な組み合わせであれば、金属箔５３の除去後、開口１１ａの上端（主表面位置）まで第一ビア導体４１を形成した状態とすることが可能となり、金属端子８の形成がより容易となる。   When the metal foil layer 53 is removed by chemical etching, the metal foil layer 53 and the first via conductor 41 are made of different metals, and the etching solution selectively removes only the metal foil 53. If the combination is possible, the first via conductor 41 can be formed up to the upper end (main surface position) of the opening 11a after the metal foil 53 is removed, and the metal terminal 8 can be formed more easily. It becomes.

本発明の配線基板の製造方法の工程を表す図。The figure showing the process of the manufacturing method of the wiring board of this invention. 図１に続く図。The figure following FIG. 図２に続く図。The figure following FIG. 本発明の一実施形態である配線基板の断面構造の概略を表す図。The figure showing the outline of the cross-sectional structure of the wiring board which is one Embodiment of this invention. 図４の配線基板１を用いた半導体装置を表す図。The figure showing the semiconductor device using the wiring board 1 of FIG. 多数個取りワーク基板とされた配線積層部１００を上部より見た図。The figure which looked at the wiring lamination | stacking part 100 made into the multi-piece work board | substrate from the upper part. 本発明の配線基板の製造方法の工程の第一変形例を表す図。The figure showing the 1st modification of the process of the manufacturing method of the wiring board of this invention. 本発明の配線基板の製造方法の工程の第二変形例を表す図。The figure showing the 2nd modification of the process of the manufacturing method of the wiring board of this invention.

符号の説明Explanation of symbols

１ 配線基板
１１ 第一誘電体層
１２ 第二誘電体層
２０ 支持基板
２１ 下地誘電体層
５ 複層シート
５１ 加熱剥離性接着層
５２ シート基材
１００ 配線積層部 DESCRIPTION OF SYMBOLS 1 Wiring board 11 1st dielectric material layer 12 2nd dielectric material layer 20 Supporting substrate 21 Base dielectric layer 5 Multi-layer sheet 51 Heat-peelable adhesive layer 52 Sheet base material 100 Wiring laminated part

Claims (5)

コア基板を有さず、かつ両主表面が誘電体層にて構成されるように、高分子材料からなる誘電体層と導体層とが交互に積層され、前記主表面の一方に、電子部品と接続するためのハンダで構成された金属端子を有する配線基板を製造するために、
製造時における補強のための支持基板上に下地誘電体層を介して加熱により接着力が低下する、基材シートに固定される加熱剥離性接着層を、前記基材シートが前記下地誘電体層側とされるように配し、該加熱剥離性接着層と前記誘電体層との間に金属箔層を介して前記配線基板となるべき配線積層部を積層形成した後、前記誘電体層の硬化温度よりも高温で、且つ、前記金属端子のハンダの融点よりも低温で剥離用加熱処理を行い、前記配線積層部の前記金属箔層と前記加熱剥離性接着層との界面から剥離した後、前記金属箔層を除去することを特徴とする配線基板の製造方法。 A dielectric layer made of a polymer material and a conductor layer are alternately laminated so as not to have a core substrate and both main surfaces are composed of dielectric layers, and an electronic component is formed on one of the main surfaces. In order to manufacture a wiring board having metal terminals composed of solder for connecting with
A heat-peelable adhesive layer fixed to a base material sheet whose adhesive strength is reduced by heating on a support substrate for reinforcement during manufacture, which is fixed to the base material sheet, wherein the base material sheet is the base dielectric layer. A wiring laminated portion to be the wiring board is interposed between the heat-peelable adhesive layer and the dielectric layer via a metal foil layer, and then the dielectric layer After performing heat treatment for peeling at a temperature higher than the curing temperature and lower than the melting point of the solder of the metal terminal, after peeling from the interface between the metal foil layer and the heat-peelable adhesive layer of the wiring laminated portion The method for producing a wiring board , wherein the metal foil layer is removed . 前記金属箔層と前記加熱剥離性接着層との界面からの剥離は、前記金属箔層に積層される前記誘電体層における積層面と反対側の表面上に導体層をパターン形成するように配線積層部の形成を行った後に行い、その後、前記金属箔層を除去した後、前記誘電体層を穿孔した個所に前記導体層と接続される金属端子を形成することを特徴とする請求項１に記載の配線基板の製造方法。   Peeling from the interface between the metal foil layer and the heat-peelable adhesive layer is performed by patterning a conductor layer on the surface opposite to the laminated surface of the dielectric layer laminated on the metal foil layer. The metal terminal connected to the conductor layer is formed at a location where the dielectric layer is perforated after the metal foil layer is removed after forming the laminated portion. The manufacturing method of the wiring board as described in 2 .. 前記金属箔層に積層される誘電体層において、前記金属箔層に接続されるように導体充填材を形成した後、前記誘電体層における前記金属箔層との積層面と反対側の表面上に導体層をパターン形成するように配線積層部の形成を行った後、前記金属箔層と前記加熱剥離性接着層との界面にて剥離を行い、その後、金属箔層を除去することにより、その除去面に前記パターン形成される前記導体層と接続された前記導体充填材が現れ、そこに前記金属端子を形成するようにすることを特徴とする請求項１に記載の配線基板の製造方法。 In the dielectric layer laminated on the metal foil layer, after forming a conductor filler so as to be connected to the metal foil layer, on the surface of the dielectric layer opposite to the lamination surface with the metal foil layer After forming the wiring laminated portion so as to pattern the conductor layer, peeling off at the interface between the metal foil layer and the heat-peelable adhesive layer, and then removing the metal foil layer, 2. The method of manufacturing a wiring board according to claim 1, wherein the conductor filler connected to the conductor layer to be patterned appears on the removal surface, and the metal terminal is formed there. . 前記金属端子を有する前記主表面には、補強枠が設置されることを特徴とする請求項１ないし３のいずれか１項に記載の配線基板の製造方法。   The wiring board manufacturing method according to claim 1, wherein a reinforcing frame is installed on the main surface having the metal terminals. 前記金属端子を有する誘導体層を、他の誘電体層よりも熱膨張率の小さい材料にて構成することを特徴とする請求項１ないし４のいずれか１項に記載の配線基板の製造方法。   5. The method of manufacturing a wiring board according to claim 1, wherein the dielectric layer having the metal terminal is made of a material having a smaller coefficient of thermal expansion than other dielectric layers.
JP2004053001A 2004-02-27 2004-02-27 Wiring board manufacturing method Expired - Fee Related JP4565861B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004053001A JP4565861B2 (en) 2004-02-27 2004-02-27 Wiring board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004053001A JP4565861B2 (en) 2004-02-27 2004-02-27 Wiring board manufacturing method

Publications (2)

Publication Number Publication Date
JP2005243999A JP2005243999A (en) 2005-09-08
JP4565861B2 true JP4565861B2 (en) 2010-10-20

Family

ID=35025400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004053001A Expired - Fee Related JP4565861B2 (en) 2004-02-27 2004-02-27 Wiring board manufacturing method

Country Status (1)

Country Link
JP (1) JP4565861B2 (en)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4621049B2 (en) * 2005-03-25 2011-01-26 富士通株式会社 Wiring board manufacturing method
US8188375B2 (en) 2005-11-29 2012-05-29 Tok Corporation Multilayer circuit board and method for manufacturing the same
JP2007188986A (en) * 2006-01-12 2007-07-26 Tdk Corp Multilayer circuit board, and method of manufacturing same
JP4835124B2 (en) * 2005-11-29 2011-12-14 Ｔｄｋ株式会社 Semiconductor IC-embedded substrate and manufacturing method thereof
JP5042495B2 (en) * 2005-12-26 2012-10-03 京セラＳｌｃテクノロジー株式会社 Wiring board manufacturing method
TWI337059B (en) 2007-06-22 2011-02-01 Princo Corp Multi-layer substrate and manufacture method thereof
EP2190273B1 (en) * 2007-07-12 2012-09-26 Princo Corp. Multi-layer baseboard and manufacturing method thereof
JP4888736B2 (en) 2008-08-29 2012-02-29 Ｔｄｋ株式会社 Wiring board manufacturing method
JP5328281B2 (en) * 2008-10-03 2013-10-30 三井金属鉱業株式会社 Manufacturing method of multilayer printed wiring board and multilayer printed wiring board obtained by using the method
KR101095211B1 (en) 2008-12-17 2011-12-16 삼성전기주식회사 A carrier member for manufacturing a substrate and a fabricating method of substrate using the same
KR101140882B1 (en) * 2009-08-31 2012-05-03 삼성전기주식회사 A printed circuit board having a bump and a method of manufacturing the same
KR101022873B1 (en) * 2009-09-14 2011-03-16 삼성전기주식회사 A fabricating method of a printed circuit board
KR101044197B1 (en) 2009-11-12 2011-06-28 삼성전기주식회사 A method of manufacturing a printed circuit board
KR101055455B1 (en) 2009-11-30 2011-08-08 삼성전기주식회사 Carrier member for substrate manufacturing and method for manufacturing substrate using same
KR101101496B1 (en) 2009-11-30 2012-01-03 삼성전기주식회사 carrier for manufacturing wiring substrate and method of manufacturing wiring substrate using the same
KR101077340B1 (en) * 2009-12-15 2011-10-26 삼성전기주식회사 A carrier member for manufacturing a substrate and a method of manufacturing a substrate using the same
KR101055488B1 (en) 2009-12-16 2011-08-08 삼성전기주식회사 Carrier for manufacturing printed circuit board, manufacturing method thereof and manufacturing method of printed circuit board using same
KR20110077403A (en) * 2009-12-30 2011-07-07 삼성전기주식회사 A carrier member for manufacturing a substrate and a method of manufacturing a substrate using the same
KR101156776B1 (en) * 2010-12-21 2012-06-18 삼성전기주식회사 A method of manufacturing a printed circuit board
US8946884B2 (en) * 2013-03-08 2015-02-03 Xilinx, Inc. Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product
KR101731700B1 (en) * 2015-03-18 2017-04-28 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
KR101807621B1 (en) * 2016-03-25 2017-12-12 주식회사 심텍 Printed circuit board using carrier substrate and method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000196243A (en) * 1998-12-28 2000-07-14 Fujitsu Ltd Manufacture of flexible multilayer circuit board
JP2002094236A (en) * 2000-09-11 2002-03-29 Ibiden Co Ltd Method for manufacturing multilayer circuit board
JP2002164467A (en) * 2000-09-14 2002-06-07 Sony Corp Circuit block body, its manufacturing method, wiring circuit device, its manufacturing method, semiconductor device and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000196243A (en) * 1998-12-28 2000-07-14 Fujitsu Ltd Manufacture of flexible multilayer circuit board
JP2002094236A (en) * 2000-09-11 2002-03-29 Ibiden Co Ltd Method for manufacturing multilayer circuit board
JP2002164467A (en) * 2000-09-14 2002-06-07 Sony Corp Circuit block body, its manufacturing method, wiring circuit device, its manufacturing method, semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
JP2005243999A (en) 2005-09-08

Similar Documents

Publication Publication Date Title
JP4565861B2 (en) Wiring board manufacturing method
JP4767269B2 (en) Method for manufacturing printed circuit board
JP4538373B2 (en) Manufacturing method of coreless wiring substrate and manufacturing method of electronic device having the coreless wiring substrate
US11152293B2 (en) Wiring board having two insulating films and hole penetrating therethrough
JP2001028483A (en) Wiring board, multilayer wiring board, circuit component package, and manufacturing method of wiring board
US8347493B2 (en) Wiring board with built-in electronic component and method of manufacturing same
US20020150838A1 (en) Structure and method for forming a multilayered structure
WO2004014114A1 (en) Method for manufacturing board with built-in device and board with built-in device, and method for manufacturing printed wiring board and printed wiring board
JP2008124398A (en) Semiconductor package and its manufacturing method
JP6510884B2 (en) Wiring board, method of manufacturing the same and electronic component device
JP2008300819A (en) Printed circuit board and method for manufacturing the same
JP5176676B2 (en) Manufacturing method of component-embedded substrate
JP4520606B2 (en) Multilayer circuit board manufacturing method
JP5861400B2 (en) Semiconductor mounting materials
JP3935456B2 (en) Wiring board manufacturing method
JP4282161B2 (en) Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
JP2009164492A (en) Manufacturing method of wiring substrate
JP4549692B2 (en) Wiring board manufacturing method
JP3608559B2 (en) Method for manufacturing element-embedded substrate
JP4549693B2 (en) Wiring board manufacturing method
JP2005063987A (en) Wiring board and its manufacturing method
JP3107535B2 (en) Wiring board, circuit component mounted body, and method of manufacturing wiring board
JP4549691B2 (en) Wiring board manufacturing method
JP2004103798A (en) Method of manufacturing two metal tapes and wiring substrate
JP2009164491A (en) Manufacturing method of wiring substrate

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070219

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090805

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090807

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091005

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100331

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100531

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100707

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100803

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130813

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130813

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees