JP2003347157A - Thin film electronic component - Google Patents
Thin film electronic componentInfo
- Publication number
- JP2003347157A JP2003347157A JP2002158225A JP2002158225A JP2003347157A JP 2003347157 A JP2003347157 A JP 2003347157A JP 2002158225 A JP2002158225 A JP 2002158225A JP 2002158225 A JP2002158225 A JP 2002158225A JP 2003347157 A JP2003347157 A JP 2003347157A
- Authority
- JP
- Japan
- Prior art keywords
- protective layer
- layer
- thin film
- thin
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は薄膜電子部品に関
し、例えば、薄膜コンデンサ、薄膜フィルタ等に好適に
用いられる高周波用途の薄膜電子部品に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin-film electronic component, and more particularly to a thin-film electronic component suitably used for high-frequency applications, such as a thin-film capacitor and a thin-film filter.
【０００２】[0002]
【従来技術】近年、電子機器の小型化、高機能化に伴
い、電子機器内に設置される電子部品にも小型化、薄型
化、高周波対応などの要求が強くなってきている。2. Description of the Related Art In recent years, as electronic devices have become smaller and more sophisticated, there has been a growing demand for electronic components installed in electronic devices to be smaller, thinner, and compatible with high frequencies.
【０００３】例えば、大量の情報を高速に処理するコン
ピュータでは、ＣＰＵチップをドライブするクロック周
波数が１ＧＨｚを超え、チップ間バスのクロック周波数
も１３３ＭＨｚから更なる高速化が追求されている。For example, in a computer for processing a large amount of information at a high speed, a clock frequency for driving a CPU chip exceeds 1 GHz, and a clock frequency of a bus between chips is further increased from 133 MHz.
【０００４】また、ＬＳＩの集積度が高まるとともにチ
ップからの発熱を抑えるために電源電圧を低くし、消費
電力の低減を図る傾向にある。これら集積回路の高速
化、高密度化、低電圧化に伴い、コンデンサ等の受動部
品も小型大容量化と併せて、高周波もしくは高速パルス
に対して優れた特性を示すものが要求されてきている。In addition, as the degree of integration of LSIs increases, there is a tendency that the power supply voltage is lowered in order to suppress heat generation from the chip, thereby reducing power consumption. As the speed, density, and voltage of these integrated circuits have increased, passive components such as capacitors have also been required to exhibit excellent characteristics with respect to high-frequency or high-speed pulses, in addition to increasing the size and capacitance. .
【０００５】動作周波数が高くなるにつれ、素子の持つ
抵抗やインダクタンスがロジック回路側の電源電圧の瞬
時低下や新たな電圧ノイズを発生させ、このノイズはロ
ジック回路にエラーを引き起こす原因となる。加えて、
最近のＬＳＩは総素子数の増大による消費電力増大を低
減し、発熱を抑えるために電源電圧を低くしているの
で、電源電圧の許容変動幅も小さくなっている。今後、
さらに素子数の増大と動作周波数の増加を行うために
は、実装部分の抵抗、インダクタンス成分の影響を少な
くする対策が必要となる。[0005] As the operating frequency increases, the resistance and inductance of the elements cause an instantaneous drop of the power supply voltage on the logic circuit side and new voltage noise, and this noise causes errors in the logic circuit. in addition,
In recent LSIs, since the power supply voltage is reduced in order to reduce power consumption due to an increase in the total number of elements and to suppress heat generation, the allowable fluctuation range of the power supply voltage is also reduced. from now on,
Further, in order to increase the number of elements and increase the operating frequency, it is necessary to take measures to reduce the influence of the resistance and inductance components of the mounting part.
【０００６】また、素子数の増大に伴う実装精度の向上
や、部品実装に伴うリフロー耐性の向上等、前述した受
動素子自身の電気的な特性だけではなく、実装に関する
特性（実装精度、実装信頼性）や耐湿信頼性など高いレ
ベルで要求されるようになってきている。[0006] In addition to the above-described electrical characteristics of the passive element itself, such as improvement in mounting accuracy due to an increase in the number of elements and improvement in reflow resistance due to component mounting, characteristics relating to mounting (mounting accuracy, mounting reliability). ) And moisture resistance reliability.
【０００７】このような要求に対して、ＵＳＰ４，４３
９，８１３には、支持基板上に、下部電極、誘電体層、
上部電極及び保護層を順次設け、Ｔｉ／Ｗ、Ｔａまたは
Ａｌ、Ｃｕからなる下部電極からの電気信号を最短距離
で得るため、誘電体層、上部電極及び保護層に貫通孔を
設け、この貫通孔内壁にＣｒ／Ｃｕ／ＡｕからなるＢＬ
Ｍ層を形成した後、このＢＬＭ層上に半田バンプを形成
してなる薄膜デカップリングコンデンサが開示されてい
る。In response to such demands, US Pat.
9, 813, a lower electrode, a dielectric layer,
An upper electrode and a protective layer are sequentially provided, and a through hole is provided in the dielectric layer, the upper electrode, and the protective layer in order to obtain an electric signal from the lower electrode made of Ti / W, Ta, Al, or Cu at the shortest distance. BL made of Cr / Cu / Au on the inner wall of the hole
A thin film decoupling capacitor is disclosed in which an M layer is formed and then a solder bump is formed on the BLM layer.
【０００８】この薄膜デカップリングコンデンサは、実
装基体の表面に形成された所定配線に薄膜デカップリン
グコンデンサの半田バンプを位置合わせし、リフロー
（加熱）処理することにより実装される。This thin-film decoupling capacitor is mounted by aligning solder bumps of the thin-film decoupling capacitor with predetermined wiring formed on the surface of the mounting substrate and performing a reflow (heating) process.
【０００９】また、この薄膜デカップリングコンデンサ
は低インダクタンス構造としており、配置もＬＳＩチッ
プ近辺に配置できるようにし、全体のインダクタンスを
低くしてＬＳＩチップの高周波動作に伴う問題を解決し
ようとするものである。Further, the thin-film decoupling capacitor has a low inductance structure. The thin-film decoupling capacitor can be arranged in the vicinity of the LSI chip. is there.
【００１０】[0010]
【発明が解決しようとする課題】しかしながら、上記従
来技術の薄膜コンデンサでは、保護層に設けられた貫通
孔内に半田バンプが形成されているため、半田バンプ形
成時または実装基板への実装時に熱の印加により、半田
バンプが収縮して、半田バンプが形成される貫通孔を持
つ保護層に負荷がかかる。そのため、保護層と保護層と
接する薄膜コンデンサの層の界面(上部電極層)が剥離し
たり、保護層自体にクラックが入り、耐湿性を劣化して
しまうという問題があった。本発明は、上述の問題点に
鑑み案出されたものであり、その目的は保護膜がもつ耐
湿性を十分に発揮することができる薄膜電子部品を提供
することである。However, in the above-mentioned thin film capacitor of the prior art, since the solder bump is formed in the through hole provided in the protective layer, heat is not generated when forming the solder bump or mounting on the mounting board. Is applied, the solder bump shrinks, and a load is applied to the protective layer having a through hole in which the solder bump is formed. Therefore, there has been a problem that the interface (upper electrode layer) between the protective layer and the layer of the thin film capacitor in contact with the protective layer is peeled off, or the protective layer itself is cracked, thereby deteriorating the moisture resistance. The present invention has been made in view of the above problems, and an object of the present invention is to provide a thin-film electronic component that can sufficiently exhibit the moisture resistance of a protective film.
【００１１】[0011]
【課題を解決するための手段】本発明の薄膜電子部品
は、支持基板上に、下部電極層、誘電体層及び上部電極
層を順次積層した薄膜素子と、前記電極層と電気的に接
続する端子電極と、該端子電極を露出するように薄膜素
子を被覆する第１保護層及び該第１保護層を被覆する第
２保護層とから成る薄膜電子部品であって、第１保護層
の熱膨張係数が１．０×１０-7℃- 1以上 １．０×１０
-5℃- 1未満であり、第２保護層の熱膨張係数が１．０×
１０-5℃- 1以上 １.０×１０-3℃- 1未満に設定したも
のである。According to the present invention, there is provided a thin film electronic component in which a lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially laminated on a supporting substrate, and the thin film electronic component is electrically connected to the electrode layer. A thin-film electronic component comprising: a terminal electrode; a first protective layer that covers the thin-film element so as to expose the terminal electrode; and a second protective layer that covers the first protective layer. expansion coefficient of 1.0 × 10 -7 ° C. - 1 or 1.0 × 10
-5 ° C - 1 and the thermal expansion coefficient of the second protective layer is 1.0 ×
10 -5 ° C. - 1 or 1.0 × 10 -3 ℃ - is obtained by setting to less than 1.
【００１２】このような構成を採用することにより、端
子電極上に半田バンプなどの外部端子を形成する際、若
しくは薄膜電子部品を実装基板に実装したときのように
外部端子を介して端子電極に熱が加わった場合、仮に外
部端子電極に熱収縮が起きても、第２保護層の方が第１
保護層よりも熱膨張係数が大きいため、外部端子または
端子電極の熱収縮の影響は第２保護層に留まり、第１保
護層は外部端子の熱収縮の影響を受けにくく、第１保護
層と第１保護層と接する薄膜素子との界面が剥離した
り、第１保護層にクラックが入ったりすることが無く、
第１保護層は本来の機能すなわち耐湿性向上の機能を果
たすことができ、もって薄膜電子部品の耐湿性を向上さ
せることができる。By adopting such a configuration, when external terminals such as solder bumps are formed on the terminal electrodes, or when the thin-film electronic components are mounted on a mounting substrate, the terminal electrodes are connected to the terminal electrodes. When heat is applied, even if the external terminal electrode undergoes thermal shrinkage, the second protective layer is
Since the thermal expansion coefficient is larger than that of the protective layer, the influence of the thermal shrinkage of the external terminal or the terminal electrode remains in the second protective layer, and the first protective layer is hardly affected by the thermal shrinkage of the external terminal. The interface between the thin film element in contact with the first protective layer does not peel off, and the first protective layer does not crack.
The first protective layer can fulfill its original function, that is, the function of improving moisture resistance, and thus can improve the moisture resistance of the thin-film electronic component.
【００１３】さらに、端子電極の周囲には１０μｍ以上
の間隙をもって第１保護層が形成されている。これによ
って外部端子の熱収縮の影響による、第１保護層への影
響を少なくでき、第１保護層の本来の機能を果たすこと
ができる。Further, a first protective layer is formed around the terminal electrode with a gap of 10 μm or more. Thereby, the influence of the heat shrinkage of the external terminals on the first protective layer can be reduced, and the original function of the first protective layer can be achieved.
【００１４】[0014]
【発明の実施の形態】以下本発明の薄膜電子部品を図面
に基づいて詳説する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A thin film electronic component according to the present invention will be described below in detail with reference to the drawings.
【００１５】図１は、薄膜電子部品の一例である薄膜コ
ンデンサの断面図である。図１に示す薄膜コンデンサ
は、支持基板１上に下部電極層５ａおよびその延出部５
ｂからなる下側電極層５と、前記下部電極層５ａ上に形
成された誘電体層３と、該誘電体層３上に形成された上
部電極層７ａおよびその延出部７ｂからなる上側電極層
７とが順次被着形成されている。尚、下部電極層５ａ、
誘電体層３、上部電極層７ａで所定容量が発生する薄膜
素子Ａが構成されている。また、必要に応じて支持基板
１上に複数の薄膜素子Ａを併設しても良い。FIG. 1 is a sectional view of a thin film capacitor which is an example of a thin film electronic component. The thin film capacitor shown in FIG. 1 has a lower electrode layer 5 a and an extension 5 on a support substrate 1.
b, a lower electrode layer 5 formed on the lower electrode layer 5a, an upper electrode layer 7a formed on the dielectric layer 3 and an upper electrode The layers 7 are sequentially formed. The lower electrode layer 5a,
The thin film element A in which a predetermined capacitance is generated by the dielectric layer 3 and the upper electrode layer 7a is formed. Further, a plurality of thin film elements A may be provided on the support substrate 1 as needed.
【００１６】下側電極層５は、上部電極層７ａの延出部
７ｂが形成される領域に応じて環状にエッチングされて
いる。また、下部電極層５は、容量を形成する下部電極
層５ａと容量を形成しない延出部５ｂ(端子電極が形成
される領域)とに区分されている。The lower electrode layer 5 is circularly etched in accordance with the region where the extension 7b of the upper electrode layer 7a is formed. The lower electrode layer 5 is divided into a lower electrode layer 5a forming a capacitor and an extension 5b (a region where a terminal electrode is formed) not forming a capacitor.
【００１７】また、上側電極層７は、下部電極層５ａを
露出するようにエッチングされ、容量を形成する上部電
極層７ａと容量を形成しないその延出部７ｂとに区分さ
れている。The upper electrode layer 7 is etched so as to expose the lower electrode layer 5a, and is divided into an upper electrode layer 7a forming a capacitor and an extension 7b not forming a capacitor.
【００１８】また少なくとも上部電極層７ａの延出部７
ｂおよび下部電極層５ａの延出部５ｂには、半田拡散防
止層１７が形成されており、この半田拡散防止層１７上
には、端子電極となる半田密着層１８が形成されてい
る。この半田密着層１８を介して半田ボールなどの外部
端子１１ａ、１１ｂが設けられている。Also, at least the extension 7 of the upper electrode layer 7a
b and the extension 5b of the lower electrode layer 5a, a solder diffusion preventing layer 17 is formed. On the solder diffusion preventing layer 17, a solder adhesion layer 18 serving as a terminal electrode is formed. External terminals 11 a and 11 b such as solder balls are provided via the solder adhesion layer 18.
【００１９】支持基板１としては、アルミナ、サファイ
ア、窒化アルミ、酸化マグネシウム単結晶、チタン酸ス
トロンチウム単結晶、表面酸化シリコン、ガラス、石英
等から選択されるもので特に限定されない。電極層５、
７の材質は、薄膜電子部品の用途、及び各部位の使用目
的によって限定され、例えば高速信号回路に用いられる
場合は、電気抵抗の低いものが良く、Ｃｕ、Ａｕ、Ａ
ｇ、Ｐｔなどが例示できる。The support substrate 1 is selected from alumina, sapphire, aluminum nitride, magnesium oxide single crystal, strontium titanate single crystal, surface silicon oxide, glass, quartz, etc., and is not particularly limited. Electrode layer 5,
The material of 7 is limited depending on the use of the thin film electronic component and the purpose of use of each part. For example, when used for a high-speed signal circuit, a material having a low electric resistance is preferable, and Cu, Au, A
g, Pt, etc. can be illustrated.
【００２０】誘電体層３の材料には、チタン酸ベリリウ
ム、チタン酸ストロンチウム、チタン酸ストロンチウム
ベリリウムなどが用いられるが、比誘電率がある程度高
く、電荷を大量に蓄積できる、具体的には比誘電率が７
０以上の材料で構成される。As the material of the dielectric layer 3, beryllium titanate, strontium titanate, strontium beryllium titanate, etc. are used. The dielectric constant is high to some extent, and a large amount of electric charges can be accumulated. Rate 7
It is composed of zero or more materials.
【００２１】半田拡散防止層１７は、Ｔｉ、Ｃｒ、Ｎ
ｉ、Ｃｕ、Ｐｄ、Ｐｔ、またはこれらの金属から選ばれ
る２種以上からなる合金のうちいずれかからなり、スパ
ッタ、蒸着、メッキ等で形成可能であれば良い。半田拡
散防止層１７の厚みは、半田バリアとしての機能を発現
するためには０．３μｍ以上の厚みであれば良い。The solder diffusion preventing layer 17 is made of Ti, Cr, N
It may be made of any one of i, Cu, Pd, Pt, or an alloy of two or more kinds selected from these metals, as long as it can be formed by sputtering, vapor deposition, plating, or the like. The thickness of the solder diffusion preventing layer 17 may be 0.3 μm or more in order to exhibit a function as a solder barrier.
【００２２】また、半田密着層１８は半田濡れ性の良好
な材料であることが望ましく、前記材料として、Ｎｉ−
Ｃｒ、Ａｕ等があり、特にＡｕが望ましい。更に、半田
拡散防止層１７と例えばからなる電極層５、７との密着
性を向上させるため、これらの間に公知の密着材料であ
るＴｉやＣｒを介在させても良い。The solder adhesion layer 18 is preferably made of a material having good solder wettability.
There are Cr, Au and the like, and Au is particularly desirable. Further, in order to improve the adhesion between the solder diffusion preventing layer 17 and the electrode layers 5 and 7 made of, for example, a known adhesion material such as Ti or Cr may be interposed between them.
【００２３】そして、本発明の薄膜コンデンサは、第１
保護層１３により少なくとも薄膜素子Ａが被覆され、誘
電体層非形成領域Bにおける第１保護層１３には貫通孔
２３a、２３ｂが形成され、貫通孔２３a、２３ｂの底面
には半田密着層１８が露出している。また、第１保護層
１３および貫通孔２３ａ、２３ｂの内壁を覆うように第
２保護層１４が形成されている。すなわち誘電体層非形
成領域Bにおける第２保護層１４には、第１保護層１３
に形成した貫通孔２３a、２３ｂよりも小さな貫通孔２
５a、２５ｂが形成され、貫通孔２５a、２５ｂの底面に
は半田密着層１８が露出して端子電極となる。つまり、
第１保護層１３の形成領域よりも第２保護層１４の方が
広く形成されている。The thin-film capacitor of the present invention has a first
At least the thin film element A is covered with the protective layer 13, through holes 23 a and 23 b are formed in the first protective layer 13 in the dielectric layer non-formed area B, and a solder adhesion layer 18 is provided on the bottom surface of the through holes 23 a and 23 b. It is exposed. Also, a second protective layer 14 is formed so as to cover the first protective layer 13 and the inner walls of the through holes 23a and 23b. That is, the second protective layer 14 in the dielectric layer non-formation region B is provided with the first protective layer 13
Hole 2 smaller than through holes 23a and 23b formed in
5a and 25b are formed, and the solder adhesion layer 18 is exposed on the bottom surfaces of the through holes 25a and 25b to serve as terminal electrodes. That is,
The second protective layer 14 is formed wider than the region where the first protective layer 13 is formed.
【００２４】図２は、第１保護層１３の形成領域と第２
保護層１４の形成領域の関係を示した平面図である。実
線は第１保護層１３の形成領域を示しており、点線は第
２保護層１４の形成領域を示している。貫通孔２３、２
５においては、第１保護層１３の貫通孔２３a、２３ｂ
よりも、第２保護層１４の貫通孔２５a、２５ｂを小さ
くすることで、第１保護層１３の形成領域よりも第２保
護層１４の形成領域を広くしている。更に言えば、この
貫通孔２５ａ、２５ｂの周囲には１０μｍ以上の第１保
護層の非形成領域(間隙ｄ)が形成され、この間隙ｄが第
２保護層１４によって被覆されている。尚、図２に示す
ように、外周部においても第１保護層１３よりも第２保
護層１４の方を広く形成しても良い。FIG. 2 shows the region where the first protective layer 13 is formed and the second protective layer 13.
FIG. 3 is a plan view showing a relationship between formation regions of a protection layer. A solid line indicates a region where the first protective layer 13 is formed, and a dotted line indicates a region where the second protective layer 14 is formed. Through hole 23, 2
5, the through holes 23a, 23b of the first protective layer 13
By making the through holes 25 a and 25 b of the second protective layer 14 smaller than that, the formation region of the second protection layer 14 is made wider than the formation region of the first protection layer 13. More specifically, a non-formation region (gap d) of the first protection layer of 10 μm or more is formed around the through holes 25a and 25b, and the gap d is covered with the second protection layer. Note that, as shown in FIG. 2, the second protective layer 14 may be formed wider than the first protective layer 13 also in the outer peripheral portion.
【００２５】第１保護層１３は耐湿性の高い材料からな
ることが望ましく、例えば、窒化珪素やシリカなどの無
機材料が特に望ましい。また、これらの材料を２種以上
用いた積層構造であっても良い。これらの無機材料で構
成した第１保護層１３は、その熱膨張係数は１．０×１
０-7℃― 1以上 １．０×１０-5℃― 1未満となる。The first protective layer 13 is desirably made of a material having high moisture resistance. For example, an inorganic material such as silicon nitride or silica is particularly desirable. Further, a laminated structure using two or more of these materials may be used. The first protective layer 13 made of these inorganic materials has a thermal expansion coefficient of 1.0 × 1.
0 -7 ° C - 1 or more and less than 1.0 × 10 -5 ° C - 1
【００２６】また、第２保護層１４の材料は特に限定さ
れるものではなく、前記に述べたような無機材料であっ
ても良いし、ポリイミドやベンゾシクロブテン（ＢＣ
Ｂ）などの有機材料であっても良い。また、これらの材
料を２種以上用いた積層構造であっても良い。これら材
料はその熱膨張係数が第１保護層の熱膨張係数よりも大
きく、例えば１．０×１０-5℃― 1以上 １．０×１０
-3℃― 1未満としている。The material of the second protective layer 14 is not particularly limited, and may be the inorganic material described above, or may be polyimide or benzocyclobutene (BC).
Organic materials such as B) may be used. Further, a laminated structure using two or more of these materials may be used. These materials have a thermal expansion coefficient larger than that of the first protective layer, for example, 1.0 × 10 −5 ° C. - 1 or more.
-3 ° C. - is less than 1.
【００２７】従って、保護層全体でみると、保護層の外
部側から第２および第１保護層１４、１３の熱膨張係数
が、薄膜素子に向かって暫時小さくなるように設定され
ている。Accordingly, when viewed as a whole of the protective layer, the thermal expansion coefficients of the second and first protective layers 14 and 13 from the outside of the protective layer are set so as to gradually decrease toward the thin film element.
【００２８】そして、第２保護層１４の貫通孔２５a、
２５ｂ内には、外部端子１１a、１１ｂが形成される。Then, the through-hole 25a of the second protective layer 14,
External terminals 11a and 11b are formed in 25b.
【００２９】外部端子１１ａ、１１ｂは、形状的には、
ボール状、バンプ状、箔状、板状、線状、ペースト状な
どがあり、特に限定されるものではなく、複数の形状を
組み合わせても良い。また、材質はＰｂ、Ｓｎ、Ａｕ、
Ｐｔ、Ｐｄ、Ａｌ、Ｎｉ、Ａｇ、Ｉｎ、Ｃｕ、Ｂｉ、Ｓ
ｂおよびＺｎなどがあり、導電性のものであれば良く、
複数の材料を組み合わせても良い。The external terminals 11a, 11b are
There are a ball shape, a bump shape, a foil shape, a plate shape, a line shape, a paste shape and the like, and there is no particular limitation, and a plurality of shapes may be combined. The material is Pb, Sn, Au,
Pt, Pd, Al, Ni, Ag, In, Cu, Bi, S
b and Zn, etc., as long as they are conductive,
A plurality of materials may be combined.
【００３０】上記のような薄膜コンデンサ４３は、図３
に示すように、実装基板４０の表面に形成された所定配
線４１ａ、４１ｂに、外部端子１１ａ、１１ｂを位置決
めした後、リフロー処理することにより接合して実装さ
れる。The thin film capacitor 43 as described above is similar to that shown in FIG.
As shown in (2), after the external terminals 11a and 11b are positioned on the predetermined wirings 41a and 41b formed on the surface of the mounting board 40, the external terminals 11a and 11b are bonded and mounted by reflow processing.
【００３１】図１に示す薄膜電子部品の場合には、例え
ば、外部端子１１ａ、１１ｂを半田ボールより構成する
場合、公知の技術であるスクリーン印刷やボールマウン
ターを用いて、半田密着層１８上に外部端子１１ａ、１
１ｂを設けた後、リフロー処理することにより実装基板
４０の所定配線４１ａ、４１ｂに接合され、実装され
る。In the case of the thin-film electronic component shown in FIG. 1, for example, when the external terminals 11a and 11b are formed of solder balls, the external terminals 11a and 11b are formed on the solder adhesion layer 18 by using a screen printing or a ball mounter, which is a known technique. External terminals 11a, 1
After the 1b is provided, it is bonded to the predetermined wirings 41a and 41b of the mounting board 40 by performing a reflow process and mounted.
【００３２】以上のように構成された薄膜コンデンサで
は、第１保護層１３の形成領域よりも、第２保護層１４
の形成領域のほうが広いため、第２保護層１４の貫通孔
２５a、２５ｂ内に外部端子１１a、１１ｂを形成した
り、薄膜コンデンサを実装基板４０に実装する際の、外
部端子１１a、１１ｂの熱収縮の影響、具体的には外部
端子１１ａ、１１ｂから直接または間接的に半田密着層
１８である端子電極に熱応力の影響がかかろうとして
も、第２保護層１４の熱膨張係数が、第１保護層１３の
熱膨張係数よりも大きいため、その応力を第２保護層１
４で吸収しやすくなる。これにより、第１保護層１３と
第１保護層１３と接する層の界面や第１保護層１３と上
部電極層７ａとの界面が剥離したり、第１保護層１３に
クラックが入ることが無く、第１保護層１３の持つ本来
の機能を果たすことができる。そのため、薄膜コンデン
サの耐湿性を向上させることができる。In the thin-film capacitor configured as described above, the second protective layer 14 is formed more than the region where the first protective layer 13 is formed.
Since the formation region of the external terminals 11a and 11b is larger in the through holes 25a and 25b of the second protective layer 14 and when the thin film capacitor is mounted on the mounting substrate 40, the heat generated by the external terminals 11a and 11b is larger. Even if the influence of shrinkage, specifically, whether the external electrodes 11a and 11b are directly or indirectly affected by the thermal stress on the terminal electrode serving as the solder adhesion layer 18, the thermal expansion coefficient of the second protective layer 14 is Since the thermal expansion coefficient of the first protective layer 13 is larger than that of the second protective layer 1,
4 makes it easier to absorb. Thereby, the interface between the first protective layer 13 and the layer in contact with the first protective layer 13 or the interface between the first protective layer 13 and the upper electrode layer 7a does not peel off, and the first protective layer 13 is not cracked. Thus, the primary function of the first protective layer 13 can be achieved. Therefore, the moisture resistance of the thin film capacitor can be improved.
【００３３】尚、本発明の薄膜電子部品として薄膜コン
デンサを例に説明したが、本発明では上記例に限定され
るものではなく、例えば、薄膜ＬＣフィルタ、あるいは
薄膜ＲＣ部品などの薄膜複合部品に本発明を適用しても
良いことは勿論である。Although a thin film capacitor has been described as an example of the thin film electronic component of the present invention, the present invention is not limited to the above example. For example, a thin film composite component such as a thin film LC filter or a thin film RC component may be used. Of course, the present invention may be applied.
【００３４】[0034]
【実施例】下側電極層５、上側電極層７および半田拡散
防止層１７および半田密着層１８の形成はＤＣスパッタ
法を、誘電体層３（誘電体薄膜）はRFスパッタ法にて作
製した。EXAMPLE The lower electrode layer 5, upper electrode layer 7, solder diffusion preventing layer 17 and solder adhesion layer 18 were formed by DC sputtering, and the dielectric layer 3 (dielectric thin film) was formed by RF sputtering. .
【００３５】先ず、サファイアからなる支持基板１上に
ＴｉＯ2からなる３０ｎｍの密着層を形成し、この密着
層の上面に、３０ｎｍのＡｕ層を形成し、下側電極層５
とした。First, a 30 nm adhesion layer made of TiO 2 is formed on a support substrate 1 made of sapphire, a 30 nm Au layer is formed on the upper surface of this adhesion layer, and a lower electrode layer 5 is formed.
And
【００３６】フォトリソグラフィ技術を用いて、下側電
極層５をパターン加工した。加工された下側電極層５
に、ＲＦスパッタ法にて膜厚０．５μｍのＢａ（Ｓｒ
1/3Ｔｉ2 /3）Ｏ3からなる誘電体層３を形成した。その
後フォトリソグラフィ技術を用いて、誘電体層３をパタ
ーン加工した。The lower electrode layer 5 was patterned by photolithography. Processed lower electrode layer 5
Then, a 0.5 μm-thick Ba (Sr
1/3 Ti 2/3) to form a O 3 dielectric layer 3 made of. After that, the dielectric layer 3 was patterned using a photolithography technique.
【００３７】次に、誘電体層３および誘電体層３から露
出する下側電極層５上に、膜厚３０ｎｍのＡｕからなる
上側電極層と、膜厚１．０μｍのＮｉからなる半田拡散
防止層１７と、膜厚０．１ｕｍのＡｕからなる半田密着
層１８を順次形成した。その後、フォトリソグラフィ技
術を用いて、先ず、半田密着層１８を直径１００μｍの
形状に加工し、その後半田拡散防止層１７を直径２００
μｍの形状に加工し、その後、上側電極７をパターン加
工した。Next, on the dielectric layer 3 and on the lower electrode layer 5 exposed from the dielectric layer 3, an upper electrode layer made of Au having a thickness of 30 nm and a solder diffusion prevention made of Ni having a thickness of 1.0 μm are formed. A layer 17 and a solder adhesion layer 18 made of Au having a thickness of 0.1 μm were sequentially formed. Thereafter, first, the solder adhesion layer 18 is processed into a shape having a diameter of 100 μm by using a photolithography technique.
Then, the upper electrode 7 was patterned.
【００３８】この後、ＣＶＤ法を用いて、厚さ５．０μ
ｍのＳｉＯ2を形成し、Ａｕからなる半田密着層１８が
露出するように、直径１２０μｍ、深さ５．０μｍの貫
通孔２３ａ、２３ｂを有する第１保護層を形成した。こ
のとき、ＳｉＯ2からなる第１保護層の形成領域は、縦
２．０ｍｍ横１．８ｍｍであり、その熱膨張係数は１．
０×１０-6℃― 1であった。Thereafter, a thickness of 5.0 μm was formed by CVD.
m of SiO 2 was formed, and a first protective layer having through holes 23 a and 23 b having a diameter of 120 μm and a depth of 5.0 μm was formed so that the solder adhesion layer 18 made of Au was exposed. At this time, the formation region of the first protective layer made of SiO 2 is 2.0 mm in length and 1.8 mm in width, and its thermal expansion coefficient is 1.
It was 0 × 10 −6 ° C. - 1 .
【００３９】この後、光感光性ＢＣＢを塗布し、露光、
現像を行い、Ａｕからなる半田密着層１８が露出するよ
うに、直径８０μｍ、深さ１μｍの貫通孔２５ａ、２５
ｂを有する第２保護層１４を形成した。このときのＢＣ
Ｂからなる第２保護層１４の形成領域は、縦２．０４ｍ
ｍ横２．０２ｍｍであった。この時、第２保護層１４の
熱膨張係数は１．０×１０-6℃― 1よりも下回るように
樹脂成分を調整して１．０×１０-4℃― 1とした。Thereafter, a photosensitive BCB is applied, exposed,
The through-holes 25a, 25m having a diameter of 80 μm and a depth of 1 μm are developed so that the solder adhesion layer 18 made of Au is exposed.
The second protective layer 14 having b was formed. BC at this time
The formation area of the second protective layer 14 made of B is 2.04 m long.
m 2.02 mm. At this time, the resin component was adjusted so that the coefficient of thermal expansion of the second protective layer 14 was lower than 1.0 × 10 −6 ° C. - 1 to 1.0 × 10 −4 ° C. - 1 .
【００４０】また、第１保護層の貫通孔と、第２保護層
の貫通孔の差、即ち、間隙(以下、貫通孔の差Ｄと言う)
を、２０μｍとした。The difference between the through hole of the first protective layer and the through hole of the second protective layer, that is, the gap (hereinafter referred to as the difference D between the through holes).
Was set to 20 μm.
【００４１】最後に、スクリーン印刷を用いて、貫通孔
内２５ａ、２５ｂの半田密着層１８の上にＰｂが６３重
量％、Ｓｎが３７重量％からなる共晶半田ペーストを転
写し、リフローを行い、半田バンプを形成し、図１に示
したような薄膜コンデンサを得た。Finally, a eutectic solder paste consisting of 63% by weight of Pb and 37% by weight of Sn is transferred onto the solder adhesive layers 18 in the through holes 25a and 25b by screen printing, and reflowed. Then, solder bumps were formed to obtain a thin film capacitor as shown in FIG.
【００４２】得られた薄膜コンデンサの有効電極面積は
１．８ｍｍ2であり、周波数１ＭＨｚでの静電容量は約
３０ｎＦであり、実装基板４０に実装しても一切、第１
保護層１３の剥離および第１保護層１３のクラックが皆
無となった。The effective electrode area of the obtained thin film capacitor is 1.8 mm 2 , and the capacitance at a frequency of 1 MHz is about 30 nF.
Peeling of the protective layer 13 and cracking of the first protective layer 13 were completely absent.
【００４３】また、第１保護層１３の形成領域のみを変
更することで、上述の貫通孔の差Ｄのみを変更し、その
他は上記と同様に作製した数種の薄膜コンデンサを得
た。そしてこれらの薄膜コンデンサを槽内温度８５℃、
槽内相対湿度８５％Ｒ．Ｈ．の試験槽内にて、印加電圧
２．０Ｖを連続負荷したときの絶縁抵抗値の時間変化を
観測した。図４にその結果を示す。図４をみると、上述
の貫通孔の差Ｄが１０μｍ以上では、５００時間以上経
過しても絶縁抵抗値が初期値に対して変化していない。
一方で、貫通孔の差Ｄが１０μｍを下回ると、時間経過
とともに絶縁抵抗値が初期値に対して劣化しており、そ
の差Ｄが小さいほど劣化するのが早くなっているのが分
かる。Also, by changing only the formation region of the first protective layer 13, only the difference D between the through holes described above was changed, and several other thin film capacitors manufactured in the same manner as above were obtained. And these thin-film capacitors were heated at 85 ° C
Relative humidity 85% R. H. Of the insulation resistance value when a voltage of 2.0 V was continuously applied in the test tank was observed. FIG. 4 shows the result. Referring to FIG. 4, when the difference D between the through holes is 10 μm or more, the insulation resistance does not change from the initial value even after 500 hours or more.
On the other hand, when the difference D between the through holes is less than 10 μm, the insulation resistance value is deteriorated with respect to the initial value with the passage of time, and it can be seen that the smaller the difference D is, the faster the deterioration is.
【００４４】尚、本発明者は、第１保護層１３の材料を
種々変更して、その熱膨張係数を１．０×１０-7℃- 1以
上 １．０×１０-5℃- 1未満に設定し、第２保護層の材
料を種々変更して、その熱膨張係数を、第１の熱膨張係
数よりも下回るように１．０×１０-5℃- 1以上 １.０
×１０-3℃- 1未満の範囲に設定しても、同様の効果を確
認した。逆、熱膨張係数を第１保護層と第２保護層とで
逆転させると、第１保護層と第２保護層との界面に熱処
理による応力が集中し、界面での隔離や第１保護層、第
２保護層にクラックが発生してしまい、保護層本来の機
能を発揮できなくなり、薄膜コンデンサの耐湿性が大き
く劣化してしまう。The inventor of the present invention changed the material of the first protective layer 13 in various ways, and set the thermal expansion coefficient of the first protective layer 13 to 1.0 × 10 −7 ° C. - 1 or more and less than 1.0 × 10 −5 ° C. - 1. And the material of the second protective layer is variously changed, and its thermal expansion coefficient is set to 1.0 × 10 −5 ° C. - 1 or more so as to be lower than the first thermal expansion coefficient.
× 10 -3 ° C. - be set to less than 1 range, was confirmed similar effects. Conversely, when the coefficient of thermal expansion is reversed between the first protective layer and the second protective layer, stress due to the heat treatment concentrates on the interface between the first protective layer and the second protective layer, and the isolation at the interface and the first protective layer In addition, cracks occur in the second protective layer, so that the original function of the protective layer cannot be exhibited, and the moisture resistance of the thin film capacitor is greatly deteriorated.
【００４５】[0045]
【発明の効果】以上に詳述したように、本発明によれ
ば、薄膜電子部品を実装する際若しくは薄膜電子部品の
外部端子を形成する際に生じる外部端子の熱収縮の影
響、応力が、第２保護層に留まり、第１保護層自体にク
ラックが入ったり、第１保護層と、第１保護層と接する
薄膜電子部品の層の界面が剥離することが無いため、第
１保護層の持つ本来の機能を十分に果たすことができ、
薄膜電子部品の耐湿性が向上する。As described above in detail, according to the present invention, the influence of the thermal shrinkage of the external terminals and the stress generated when mounting the thin-film electronic component or forming the external terminal of the thin-film electronic component are reduced. Since the first protective layer itself does not remain in the second protective layer and is not cracked or the interface between the first protective layer and the layer of the thin-film electronic component in contact with the first protective layer does not peel off, the first protective layer has It can fully fulfill its original function,
The moisture resistance of the thin film electronic component is improved.
【図１】本発明の薄膜電子部品の一例である薄膜コンデ
ンサの断面図である。FIG. 1 is a cross-sectional view of a thin-film capacitor as an example of a thin-film electronic component of the present invention.
【図２】第１保護層と第２保護層の形成領域の関係を示
す平面図である。FIG. 2 is a plan view illustrating a relationship between formation regions of a first protective layer and a second protective layer.
【図３】本発明の薄膜電子部品の一例である薄膜コンデ
ンサの実装状態を示す断面図である。FIG. 3 is a cross-sectional view showing a mounted state of a thin film capacitor which is an example of the thin film electronic component of the present invention.
【図４】試験槽温度８５℃、槽内相対湿度８５％Ｒ．
Ｈ．の試験環境における２．０Ｖ連続負荷したときの、
初期値に対する絶縁抵抗値の時間変化を示した特性図で
ある。FIG. 4 shows a test tank temperature of 85 ° C. and a relative humidity of 85% R.R.
H. Under a continuous load of 2.0 V in the test environment of
FIG. 4 is a characteristic diagram illustrating a temporal change of an insulation resistance value with respect to an initial value.
１・・・支持基板 ３・・・絶縁体層 ５ ・・・下側電極層 ５ａ・・・下部電極層 ７ ・・・上側電極層 ７ａ・・・上部電極層 １１ａ、１１ｂ・・・外部端子 １８・・・半田密着層（端子電極） １３・・・第１保護層 １４・・・第２保護層 ２３ａ、２３ｂ・・・第１保護層に形成した貫通孔 ２５ａ、２５ｂ・・・第２保護層に形成した貫通孔 Ａ・・・薄膜素子 1 ... Support substrate 3 ... Insulator layer 5 ... lower electrode layer 5a: Lower electrode layer 7 ... upper electrode layer 7a: Upper electrode layer 11a, 11b ... external terminals 18 ... Solder adhesion layer (terminal electrode) 13 First protective layer 14 second protective layer 23a, 23b ... through holes formed in the first protective layer 25a, 25b ... through holes formed in the second protective layer A: Thin film element
Claims (2)
上部電極層を順次積層した薄膜素子と、前記電極層と電
気的に接続する端子電極と、該端子電極を露出するよう
に薄膜素子を被覆する第１保護層及び該第１保護層を被
覆する第２保護層とから成る薄膜電子部品であって、前
記第１保護層の熱膨張係数が１．０×１０-7℃- 1以上、
１．０×１０-5℃- 1未満、第２保護層の熱膨張係数が
１．０×１０-5℃- 1以上、１.０×１０-3℃- 1未満とし
たことを特徴とする薄膜電子部品。1. A thin-film device comprising a support substrate, on which a lower electrode layer, a dielectric layer and an upper electrode layer are sequentially laminated, a terminal electrode electrically connected to the electrode layer, and a terminal electrode which is exposed. A thin-film electronic component comprising a first protective layer covering a thin-film element and a second protective layer covering the first protective layer, wherein the first protective layer has a coefficient of thermal expansion of 1.0 × 10 -7 ° C. - one or more,
1.0 × 10 -5 ℃ - less than 1, the thermal expansion coefficient of the second protective layer is 1.0 × 10 -5 ℃ - 1 or more, 1.0 × 10 -3 ℃ - and characterized in that less than 1 Thin-film electronic components.
隙を有して前記第1保護層が形成されているとともに、
前記間隙が第２保護層によって被覆されていることを特
徴とする請求項１記載の薄膜電子部品。2. The method according to claim 1, wherein the first protective layer is formed around the terminal electrode with a gap of 10 μm or more.
The thin-film electronic component according to claim 1, wherein the gap is covered with a second protective layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002158225A JP3967964B2 (en) | 2002-05-30 | 2002-05-30 | Thin film electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002158225A JP3967964B2 (en) | 2002-05-30 | 2002-05-30 | Thin film electronic components |
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| JP2003347157A true JP2003347157A (en) | 2003-12-05 |
| JP3967964B2 JP3967964B2 (en) | 2007-08-29 |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006032900A (en) * | 2004-06-14 | 2006-02-02 | Fuji Xerox Co Ltd | Piezoelectric element, ink jet recording head, and ink jet recording device |
| US7064925B2 (en) * | 2002-12-06 | 2006-06-20 | Hitachi Global Storage Technologies Japan, Ltd. | Magnetic head for reducing projection of retrieving and writing unit from float surface, and magnetic recording/retrieving apparatus using the same |
| JP2007081325A (en) * | 2005-09-16 | 2007-03-29 | Murata Mfg Co Ltd | Thin film capacitor |
| JP2011040571A (en) * | 2009-08-11 | 2011-02-24 | Murata Mfg Co Ltd | Dielectric thin film element |
| JP2013258376A (en) * | 2012-06-14 | 2013-12-26 | Mitsubishi Electric Corp | Semiconductor device |
| US9711283B2 (en) | 2014-05-12 | 2017-07-18 | Tdk Corporation | Thin film capacitor |
| US9831039B2 (en) | 2014-12-05 | 2017-11-28 | Tdk Corporation | Thin film capacitor |
-
2002
- 2002-05-30 JP JP2002158225A patent/JP3967964B2/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7064925B2 (en) * | 2002-12-06 | 2006-06-20 | Hitachi Global Storage Technologies Japan, Ltd. | Magnetic head for reducing projection of retrieving and writing unit from float surface, and magnetic recording/retrieving apparatus using the same |
| US7460335B2 (en) | 2002-12-06 | 2008-12-02 | Hitachi Global Technologies Japan, Ltd. | Magnetic head having first and second protective films with different coefficients of linear expansion |
| JP2006032900A (en) * | 2004-06-14 | 2006-02-02 | Fuji Xerox Co Ltd | Piezoelectric element, ink jet recording head, and ink jet recording device |
| JP2007081325A (en) * | 2005-09-16 | 2007-03-29 | Murata Mfg Co Ltd | Thin film capacitor |
| JP2011040571A (en) * | 2009-08-11 | 2011-02-24 | Murata Mfg Co Ltd | Dielectric thin film element |
| JP2013258376A (en) * | 2012-06-14 | 2013-12-26 | Mitsubishi Electric Corp | Semiconductor device |
| US9711283B2 (en) | 2014-05-12 | 2017-07-18 | Tdk Corporation | Thin film capacitor |
| US9831039B2 (en) | 2014-12-05 | 2017-11-28 | Tdk Corporation | Thin film capacitor |
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| Publication number | Publication date |
|---|---|
| JP3967964B2 (en) | 2007-08-29 |
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