JP2003324275A - Method of manufacturing wiring board - Google Patents
Method of manufacturing wiring boardInfo
- Publication number
- JP2003324275A JP2003324275A JP2002128992A JP2002128992A JP2003324275A JP 2003324275 A JP2003324275 A JP 2003324275A JP 2002128992 A JP2002128992 A JP 2002128992A JP 2002128992 A JP2002128992 A JP 2002128992A JP 2003324275 A JP2003324275 A JP 2003324275A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- back surface
- core
- wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、表面と裏面との間
にスルーホールなどが貫通するコア基板と、かかるコア
基板の表面上のビルドアップ層とを有する配線基板の製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a wiring board having a core substrate having through holes and the like penetrating between a front surface and a back surface thereof and a buildup layer on the front surface of the core substrate.
【０００２】[0002]
【従来の技術】近年、低コスト化の要請に応じ、表面と
裏面との間を貫通するスルーホールなどを有するコア基
板の表面(片面)上方にのみ複数の絶縁層および複数の配
線層を交互に積層したビルドアップ層を形成する配線基
板が提案されている。従来における上記配線基板の製造
方法は、メタルマスクを用いてコア基板のスルーホール
内に導電性または非導電性の樹脂を印刷により充填し且
つこれにキュア処理を行った後、スルーホールの端面を
蓋メッキし、更にコア基板の表面上方に絶縁層と配線層
とを交互に複数形成するビルドアップ工程を行ってい
た。2. Description of the Related Art In recent years, in response to a demand for cost reduction, a plurality of insulating layers and a plurality of wiring layers are alternately arranged only above the front surface (one surface) of a core substrate having a through hole penetrating between the front surface and the back surface. There has been proposed a wiring board that forms a buildup layer laminated on the substrate. In the conventional method for manufacturing the above wiring board, a conductive or non-conductive resin is filled by printing into the through holes of the core board by using a metal mask, and after this is cured, the end surfaces of the through holes are removed. There is a build-up process in which a lid is plated and a plurality of insulating layers and wiring layers are alternately formed above the surface of the core substrate.
【０００３】[0003]
【発明が解決すべき課題】しかしながら、上述したよう
な従来の製造方法では、スルーホールの穴埋め工程に長
時間を要すると共に、別途にビルドアップ工程を行うた
め、多くの工数を必要とし且つコストアップになる、と
いう問題点を有していた。本発明は、前記従来の製造方
法の問題点を解決し、スルーホールなどを有するコア基
板の表面上方にビルドアップ層を有する配線基板を、少
ない工数により確実且つ安価に製造できる配線基板の製
造方法を提供する、ことを課題とする。However, in the conventional manufacturing method as described above, it takes a long time to fill the through holes, and a separate build-up step is required, which requires a lot of man-hours and a cost increase. It had the problem of becoming. The present invention solves the problems of the conventional manufacturing method described above, and can manufacture a wiring board having a build-up layer above the surface of a core board having through holes etc. reliably and inexpensively with a small number of steps. The challenge is to provide.
【０００４】[0004]
【課題を解決するための手段】本発明は、上記課題を解
決するため、スルーホールの穴埋め工程とコア基板の裏
面に形成するソルダーレジスト層の形成工程とを同時に
行う、ことに着想して成されたものである。即ち、本発
明における第１の配線基板の製造方法(請求項１)は、表
面および裏面を有するコア基板において、かかる表面と
裏面との間を貫通するスルーホールを形成し、且つ少な
くともかかる裏面に裏面配線層を形成する工程と、上記
コア基板の裏面に接着層を形成した一対のコア基板を、
それぞれの接着層を対向させ且つ離型シートを介して積
層し、加圧および加熱することにより、上記接着層の一
部を上記スルーホールに充填する積層工程と、を含む、
ことを特徴とする。In order to solve the above-mentioned problems, the present invention is conceived to perform the step of filling the through holes and the step of forming the solder resist layer formed on the back surface of the core substrate at the same time. It was done. That is, the first wiring board manufacturing method (Claim 1) according to the present invention provides a core substrate having a front surface and a back surface with a through hole penetrating between the front surface and the back surface, and at least the back surface. A step of forming a backside wiring layer, and a pair of core substrates having an adhesive layer formed on the backside of the core substrate,
Laminating step in which the respective adhesive layers are opposed to each other and laminated via a release sheet, and the through holes are partially filled with the adhesive layers by applying pressure and heating,
It is characterized by
【０００５】これによれば、裏面に接着層をそれぞれ形
成した一対のコア基板を積層し、且つこれらを加圧およ
び加熱することにより、スルーホールの穴埋めおよびコ
ア基板の裏面に位置する所要厚さのソルダーレジスト層
を同時に形成することが、２枚のコア基板に対して行え
る。従って、工数を低減し且つ安価な配線基板を製造す
ることが可能となる。尚、上記コア基板には、単一の絶
縁層の形態の他、複数の絶縁層とそれらの間に形成した
配線層とを有する多層基板の形態も含まれる。また、か
かるコア基板の表面にも、表面配線層を形成しても良
い。更に、上記配線基板には、上記コア基板の表面およ
び裏面の間を貫通する貫通孔内またはコア基板の裏面側
に開口する凹部内に電子部品を実装または内蔵する形態
も含まれる。また、上記離型シートには、クッション材
を含む絶縁性のシートが用いられる。加えて、一対のコ
ア基板に対する加圧は、例えばホットプレスを用いても
良く、その加熱によりスルーホールの穴埋めを促進する
ことが可能となる。According to this, by laminating a pair of core substrates each having an adhesive layer formed on the back surface thereof, and pressing and heating them, the through holes are filled and the required thickness positioned on the back surface of the core substrate is obtained. It is possible to simultaneously form the solder resist layer for the two core substrates. Therefore, it is possible to reduce the number of steps and manufacture an inexpensive wiring board. The core substrate includes not only a single insulating layer but also a multilayer substrate having a plurality of insulating layers and a wiring layer formed between them. Also, a surface wiring layer may be formed on the surface of the core substrate. Further, the wiring board includes a mode in which an electronic component is mounted or built in a through hole penetrating between the front surface and the back surface of the core board or a recess opening on the back surface side of the core board. An insulating sheet including a cushion material is used as the release sheet. In addition, the pair of core substrates may be pressed by using, for example, a hot press, and the heating can accelerate the filling of the through holes.
【０００６】また、本発明における第２の配線基板の製
造方法(請求項２)は、表面および裏面を有するコア基板
において、少なくとも裏面に裏面配線層を形成すると共
に、上記表面と裏面との間を貫通し且つ上記裏面配線層
と接続するスルーホール導体を形成する工程と、上記コ
ア基板の裏面に接着層を形成した一対のコア基板を、そ
れぞれの接着層を対向させ且つ離型シートを介して積層
し、加圧および加熱することにより、上記接着層の一部
を上記スルーホール導体の内側に位置する中空部に充填
する積層工程と、を含む、ことを特徴とする。これによ
っても、裏面に接着層をそれぞれ形成した一対のコア基
板を積層し、且つこれらを加圧および加熱することによ
り、スルーホール導体内側の中空部の穴埋めおよびコア
基板の裏面に位置する所要厚さのソルダーレジスト層を
同時に形成することが、２枚のコア基板に対して行え
る。従って、工数を低減し且つ安価な配線基板を製造す
ることが可能となる。A second method for manufacturing a wiring board according to the present invention (claim 2) is a core board having a front surface and a back surface, in which a back surface wiring layer is formed on at least the back surface, and a space between the front surface and the back surface is formed. A step of forming a through-hole conductor that penetrates through and connects to the back surface wiring layer; and a pair of core substrates having an adhesive layer formed on the back surface of the core substrate, with the respective adhesive layers facing each other and via a release sheet. Laminating, and applying pressure and heat to fill a part of the adhesive layer into the hollow portion located inside the through-hole conductor. Also by this, by stacking a pair of core boards each having an adhesive layer formed on the back surface, and pressing and heating these, the hollow portion inside the through-hole conductor is filled with the required thickness on the back surface of the core board. It is possible to simultaneously form the solder resist layer on the two core substrates. Therefore, it is possible to reduce the number of steps and manufacture an inexpensive wiring board.
【０００７】更に、本発明には、前記接着層は、紙、ガ
ラスクロス、ガラス不織布、または合成繊維を含む樹脂
である、配線基板の製造方法(請求項３)も含まれる。こ
れによれば、前記コア基板の裏面およびスルーホールま
たはスルーホール導体の中空部に、それらの内径や内壁
面の形態に応じて、所望の流動性、接着性、強度、およ
び絶縁性を有する接着層(プリフレグ)を、容易にコア基
板の裏面に形成し且つスルーホールなどの穴埋めするこ
とが可能となる。尚、上記樹脂には、エポキシ、ビスマ
レイミド・トリアジン、フェノール、ポリイミド、およ
びポリエステルなどが含まれる。Further, the present invention also includes a method for manufacturing a wiring board (claim 3), wherein the adhesive layer is paper, glass cloth, glass non-woven fabric, or resin containing synthetic fibers. According to this, an adhesive having desired fluidity, adhesiveness, strength, and insulating properties on the back surface of the core substrate and the hollow portion of the through hole or the through hole conductor depending on the shape of the inner diameter and inner wall surface of the through hole or the through hole conductor. It becomes possible to easily form a layer (prefreg) on the back surface of the core substrate and fill holes such as through holes. The above resins include epoxy, bismaleimide / triazine, phenol, polyimide, polyester and the like.
【０００８】また、本発明には、前記積層工程の後に、
前記一対のコア基板の表面上方に、複数の絶縁層および
複数の配線層を含むビルドアップ層を形成するビルドア
ップ工程を有する、配線基板の製造方法(請求項４)も含
まれる。これによれば、前記スルーホールまたはスルー
ホール導体の中空部の穴埋めが成された後に、ビルドア
ップ層を形成するため、平坦な絶縁層および配線層を形
成できると共に、かかる配線層をファインパターンとす
ることも容易となる。尚、本発明は、積層工程とビルド
アップ工程との間に、前記スルーホールまたはスルーホ
ール導体の中空部におけるコア基板の表面側を閉塞する
蓋メッキ、およびコア基板の表面に表面配線層を形成す
る工程を有する製造方法、とすることもできる。また、
上記蓋メッキに先立ち、スルーホールまたはスルーホー
ル導体内側の中空部に充填した接着層(充填樹脂)の先端
部を平坦に研磨する工程を含めることもできる。According to the present invention, after the laminating step,
A wiring board manufacturing method (claim 4) including a build-up step of forming a build-up layer including a plurality of insulating layers and a plurality of wiring layers above the surfaces of the pair of core boards is also included. According to this, since the build-up layer is formed after the filling of the through hole or the hollow portion of the through hole conductor, a flat insulating layer and a wiring layer can be formed, and the wiring layer can be formed into a fine pattern. It is also easy to do. According to the present invention, between the stacking step and the build-up step, a lid plating for closing the surface side of the core substrate in the hollow portion of the through hole or the through hole conductor, and forming a surface wiring layer on the surface of the core substrate. A manufacturing method having a step of Also,
Prior to the lid plating, a step of flattening the tip of the adhesive layer (filling resin) filling the through hole or the hollow portion inside the through hole conductor may be included.
【０００９】加えて、本発明には、前記積層工程および
前記ビルドアップ工程の少なくとも一方は、前記コア基
板をそれぞれ複数有する一対のパネルを用いて行われ
る、配線基板の製造方法(請求項５)も含まれる。これに
よれば、スルーホールまたはスルーホール導体内側の中
空部の穴埋めおよびコア基板の裏面に位置する所要厚さ
のソルダーレジスト層を同時に形成する積層工程、ある
いはこの積層工程とビルドアップ工程とを多数個取り用
の一対のパネルにおいて、行うことができる。従って、
スルーホールなどを有するコア基板の表面上方にビルド
アップ層を有する配線基板を、一層効率良く低コストで
製造することが可能となる。In addition, according to the present invention, at least one of the stacking step and the build-up step is carried out using a pair of panels each having a plurality of the core boards (claim 5). Is also included. According to this, a lamination step of filling a through hole or a hollow portion inside the through hole conductor and a solder resist layer of a required thickness located on the back surface of the core substrate at the same time, or a large number of this lamination step and build-up steps. This can be done with a pair of individual panels. Therefore,
It is possible to manufacture a wiring board having a build-up layer above the surface of a core board having through holes and the like more efficiently and at low cost.
【００１０】[0010]
【発明の実施の形態】以下において、本発明の実施に好
適な形態を図面と共に説明する。図１〜図４は、本発明
により得られる配線基板１の製造方法に関する。図１
(Ａ)に示すコア基板２は、厚みが約８００μｍのガラス
−エポキシ樹脂系の複合材料からなり、その表面２ａに
銅箔３を、その裏面２ｂには銅箔４を予め貼り付けてい
る。尚、裏面２ｂの銅箔４は、表面２ａの銅箔３よりも
厚肉としたり、その表面粗さを表面２ａの銅箔３よりも
粗くしても良い。上記コア基板２の所定の位置にレーザ
を照射するか、細径のドリルにて穿孔する。その結果、
図１(Ｂ)に示すように、コア基板２における表面２ａと
裏面２ｂとの間を貫通し且つ内径が約１００μｍのスル
ーホール５が複数形成される。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments for carrying out the present invention will be described with reference to the drawings. 1 to 4 relate to a method for manufacturing a wiring board 1 obtained by the present invention. Figure 1
The core substrate 2 shown in (A) is made of a glass-epoxy resin-based composite material having a thickness of about 800 μm, and a copper foil 3 is attached to its front surface 2a and a copper foil 4 is attached to its back surface 2b in advance. The copper foil 4 on the back surface 2b may be thicker than the copper foil 3 on the front surface 2a, or its surface roughness may be rougher than that of the copper foil 3 on the front surface 2a. A predetermined position on the core substrate 2 is irradiated with a laser or is drilled with a small-diameter drill. as a result,
As shown in FIG. 1B, a plurality of through holes 5 penetrating between the front surface 2a and the back surface 2b of the core substrate 2 and having an inner diameter of about 100 μm are formed.
【００１１】次に、複数のスルーホール５を有するコア
基板２の全面に対し、無電解銅メッキおよび電解銅メッ
キを施す。尚、各スルーホール５の内壁には、予めＰｄ
などを含むメッキ触媒を塗布しておく。また、上記スル
ーホール５の穿孔および銅メッキは、複数のコア基板２
(製品単位)を含むパネル(多数個取りの基板)の状態で行
っても良い。その結果、図１(Ｃ)に示すように、各スル
ーホール５の内壁表面に沿って厚みが約１５μｍのスル
ーホール導体６がそれぞれ形成される。また、銅箔３，
４は、厚めの銅メッキ層３ａ，４ａ(便宜上厚みは銅箔
３，４と同じとする)となる。Next, electroless copper plating and electrolytic copper plating are applied to the entire surface of the core substrate 2 having a plurality of through holes 5. In addition, the inner wall of each through hole 5 has Pd in advance.
Apply a plating catalyst containing the above. In addition, the through holes 5 and the copper plating are used for the plurality of core substrates 2
It may be performed in the state of a panel (a substrate of a large number) including (product unit). As a result, as shown in FIG. 1C, through-hole conductors 6 having a thickness of about 15 μm are formed along the inner wall surface of each through-hole 5. Also, copper foil 3,
4 is thicker copper plating layers 3a and 4a (the thickness is the same as that of the copper foils 3 and 4 for convenience).
【００１２】次いで、コア基板２の裏面２ｂに位置する
銅メッキ層４ａの下に、所定のパターンを有する図示し
ないエッチングレジストを形成し、かかるレジストのパ
ターン間から露出する銅メッキ層４ａをエッチングす
る。その結果、図１(Ｄ)に示すように、前記銅メッキ層
４ａは、上記レジストのパターンに倣った裏面配線層９
となる。Next, an etching resist (not shown) having a predetermined pattern is formed under the copper plating layer 4a located on the back surface 2b of the core substrate 2, and the copper plating layer 4a exposed between the resist patterns is etched. . As a result, as shown in FIG. 1D, the copper plating layer 4a is formed on the back surface wiring layer 9 following the pattern of the resist.
Becomes
【００１３】ここで、図２(Ａ)に示すように、接着層
(プリプレグ)１１および離型層ｒを用意する。接着層１
１は、エポキシ、ビスマレイミド・トリアジン、フェノ
ール、ポリイミド、またはポリエステルなどの樹脂から
なり、且つその内部には、フィラ状の紙片、ガラスクロ
ス、ガラス不織布、合成繊維、またはシリカフィラなど
の無機フィラを含んでいる。また、離型層ｒは、例えば
一対のフィルム間に熱可塑性樹脂からなるクッション材
を挟み且つその周縁で上記フィルムにより密封したシー
ト状のものである。尚、上記クッション材には、柔軟性
(弱い弾性)を有する熱可塑性樹脂(商品名：パコタンプ
ラス)が用いられる。あるいは、かかるクッション材に
は、ＰＥＴフィルムや、フッ素樹脂(登録商標：テフロ
ン)シートなどを使用しても良い。Here, as shown in FIG. 2A, the adhesive layer
(Prepreg) 11 and release layer r are prepared. Adhesive layer 1
1 is made of a resin such as epoxy, bismaleimide / triazine, phenol, polyimide, or polyester, and inside thereof is a filler of a paper filler, glass cloth, glass non-woven fabric, synthetic fiber, or an inorganic filler such as silica filler. Contains. Further, the release layer r is, for example, a sheet shape in which a cushion material made of a thermoplastic resin is sandwiched between a pair of films and the periphery of the cushion material is sealed with the film. In addition, the above cushion material has flexibility
A thermoplastic resin (brand name: Pacotan Plus) having (weak elasticity) is used. Alternatively, a PET film, a fluororesin (registered trademark: Teflon) sheet, or the like may be used as the cushion material.
【００１４】図２(Ａ)に示すように、接着層１１を一対
のコア基板２の裏面２ｂおよび裏面配線線層９の下に個
別に形成し、これら接着層１１，１１間に離型層ｒを配
置する。尚、接着層１１，１１を離型層ｒの両面に予め
形成しても良い。次に、図２(Ａ)中の矢印で示すよう
に、裏面２ｂに接着層１１を形成した一対のコア基板
２，２を、それぞれの接着層１１を対向させ且つ離型シ
ートｒを介して積層すると共に、図示しないホットプレ
スを用いて、コア基板２，２の厚み方向に沿って加圧し
且つ加熱する(積層工程)。かかる積層工程は、複数のコ
ア基板２(製品単位)を含む一対のパネル(多数個取りの
基板)を用いて行っても良い。As shown in FIG. 2A, an adhesive layer 11 is individually formed under the back surface 2b and the back surface wiring line layer 9 of the pair of core substrates 2, and a release layer is provided between the adhesive layers 11 and 11. Place r. The adhesive layers 11 and 11 may be formed in advance on both surfaces of the release layer r. Next, as shown by the arrow in FIG. 2 (A), the pair of core substrates 2 and 2 having the adhesive layer 11 formed on the back surface 2b are made to face each other with the adhesive layers 11 facing each other and the release sheet r interposed therebetween. Along with stacking, a hot press (not shown) is used to apply pressure and heat along the thickness direction of the core substrates 2 and 2 (stacking step). This stacking step may be performed using a pair of panels (a plurality of boards) including a plurality of core boards 2 (product units).
【００１５】その結果、図２(Ｂ)に示すように、接着層
１１，１１は、コア基板２，２の裏面２ｂに所要の厚み
で接着され、ソルダーレジスト層(絶縁層)１１となる。
同時に、接着層１１，１１の一部は、各コア基板２のス
ルーホール導体６，６内側の中空部内に充填され、充填
樹脂７，７となる。かかる充填樹脂７およびソルダーレ
ジスト層１１をキュア処理して硬化する。また、各コア
基板２の表面２ａ側に突出する充填樹脂７の先端部７ａ
は、研磨により平坦化される。As a result, as shown in FIG. 2B, the adhesive layers 11 and 11 are adhered to the back surfaces 2b of the core substrates 2 and 2 with a required thickness to form the solder resist layer (insulating layer) 11.
At the same time, a part of the adhesive layers 11 and 11 is filled in the hollow portions inside the through-hole conductors 6 and 6 of each core substrate 2 to become the filling resins 7 and 7. The filling resin 7 and the solder resist layer 11 are cured and cured. Further, the tip end portion 7a of the filling resin 7 protruding toward the front surface 2a side of each core substrate 2
Are flattened by polishing.
【００１６】次いで、図３(Ａ)に示すように、各コア基
板２の表面２ａ側における銅メッキ層３ａの上に更に銅
メッキを施して、厚めの銅メッキ層３ｂとし、且つ各充
填樹脂７の先端部(上端部)を蓋メッキする。更に、各コ
ア基板２の表面２ａ側における銅メッキ層３ｂの上に、
所定のパターンを有する図示しないエッチングレジスト
を形成し、かかるレジストのパターン間から露出する銅
メッキ層３ｂをエッチングする。その結果、図３(Ｂ)に
示すように、各コア基板２の表面２ａには、上記レジス
トのパターンに倣った表面配線層８が形成される。Next, as shown in FIG. 3 (A), copper plating is further applied on the copper plating layer 3a on the surface 2a side of each core substrate 2 to form a thick copper plating layer 3b and each filling resin. The tip (upper end) of 7 is plated with a lid. Furthermore, on the copper plating layer 3b on the surface 2a side of each core substrate 2,
An etching resist (not shown) having a predetermined pattern is formed, and the copper plating layer 3b exposed between the resist patterns is etched. As a result, as shown in FIG. 3B, the surface wiring layer 8 following the resist pattern is formed on the surface 2a of each core substrate 2.
【００１７】次に、図４(Ａ)に示すように、何れかのコ
ア基板２の表面２ａおよび表面配線層８の上に、絶縁層
１０を形成し且つ表面配線層８上の所定の位置にフィル
ドビア導体１２を形成する。これ以降は、絶縁層１０な
ど共にビルドアップ層ＢＵを形成する絶縁層１６、配線
層１４，２０、フィルドビア導体１８、ソルダーレジス
ト層２２を公知のビルドアップ工程(セミアディティブ
法、フルアディティブ法、サブトラクティブ法、フィル
ム状樹脂材料のラミネートによる絶縁層の形成、フォト
リソグラフィ技術など)により形成する(ビルドアップ工
程)。尚、絶縁層１０などは、厚みが約３０μｍでシリ
カフィラなどの無機フィラを含むエポキシ樹脂であり、
ソルダーレジスト層２２の厚みは約２５μｍである。か
かるビルドアップ工程も、複数のコア基板２(製品単位)
を含む一対のパネル(多数個取りの基板)を用いて行って
も良い。Next, as shown in FIG. 4 (A), an insulating layer 10 is formed on the surface 2a of any of the core substrates 2 and the surface wiring layer 8 and at a predetermined position on the surface wiring layer 8. The filled via conductor 12 is formed on the. After that, the insulating layer 16, the wiring layers 14 and 20, the filled via conductors 18, and the solder resist layer 22 that together form the build-up layer BU, such as the insulating layer 10, are formed by a known build-up process (semi-additive method, full-additive method, sub-trapping method). Active layer, an insulating layer is formed by laminating a film-shaped resin material, a photolithography technique, etc.) (build-up process). The insulating layer 10 and the like are epoxy resin having a thickness of about 30 μm and containing an inorganic filler such as silica filler,
The thickness of the solder resist layer 22 is about 25 μm. This build-up process also includes multiple core substrates 2 (product units)
It is also possible to use a pair of panels (including a large number of substrates) including the above.
【００１８】また、配線層２０上には、第１主面２４よ
りも高く突出するハンダバンプ２６を複数形成する。か
かるハンダバンプ２６は、Ｓｎ−Ａｇ系、Ｐｂ−Ｓｎ
系、Ｓｎ−Ａｇ−Ｃｕ系、Ｓｎ−Ｃｕ系、Ｓｎ−Ｚｎ系
など(本実施形態ではＳｎ−Ａｇ系)の低融点合金からな
り、第１主面２４上に実装される図示しないＩＣチップ
の接続端子との接続に活用される。尚、残りのコア基板
２の表面２ａの上方にも、上記と同様にしてビルドアッ
プ層ＢＵなどを形成する。Further, a plurality of solder bumps 26 projecting higher than the first main surface 24 are formed on the wiring layer 20. The solder bumps 26 are made of Sn-Ag type, Pb-Sn type.
IC chip (not shown) made of a low melting point alloy such as Sn-Ag-Cu-based, Sn-Cu-based, Sn-Zn-based, etc. (Sn-Ag-based in this embodiment) and mounted on the first main surface 24. It is used to connect with the connection terminal of. A buildup layer BU and the like are formed above the surface 2a of the remaining core substrate 2 in the same manner as above.
【００１９】そして、図４(Ｂ)に示すように、離型シー
トｒを除去して個別に分離したビルドアップ層ＢＵなど
を有するコア基板２の裏面２ｂ側のソルダーレジスト層
(接着層)１１に、レーザ加工などにより所定の位置に開
口部１３を形成する。裏面配線層９から延び且つ開口部
１３内から第２主面１７側に露出する配線１５は、その
表面にＮｉメッキ膜およびＡｕメッキ膜が被覆され、当
該配線基板１自体を搭載する図示しないマザーボードな
どのプリント基板との接続端子となる。この結果、図４
(Ｂ)に示すように、ＩＣチップなどの半導体素子を実装
する直前の配線基板１を得ることができる。尚、複数の
ハンダバンプ２６と第１主面２４に実装する図示しない
ＩＣチップの接続端子とは、アンダーフィル材(図示せ
ず)により埋設され且つ保護される。Then, as shown in FIG. 4 (B), the solder resist layer on the back surface 2b side of the core substrate 2 having the build-up layer BU and the like separated by removing the release sheet r.
An opening 13 is formed in the (adhesive layer) 11 at a predetermined position by laser processing or the like. The wiring 15 extending from the back surface wiring layer 9 and exposed from the inside of the opening 13 to the second main surface 17 side is covered with a Ni plating film and an Au plating film on its surface, and the wiring board 1 itself is mounted on the motherboard (not shown). It becomes a connection terminal with the printed circuit board. As a result,
As shown in (B), it is possible to obtain the wiring board 1 immediately before mounting a semiconductor element such as an IC chip. The solder bumps 26 and the connection terminals of the IC chip (not shown) mounted on the first main surface 24 are buried and protected by an underfill material (not shown).
【００２０】以上の配線基板１の製造方法によれば、ス
ルーホール導体６および裏面配線層９を有する一対のコ
ア基板２，２を、離型シートｒを介してかかるコア基板
２の裏面２ｂに形成した接着層１１同士を対向させた状
態で積層し加圧および加熱する積層工程により、充填樹
脂７とソルダーレジスト層１１とが同時に形成できる。
しかも、各コア基板２の表面２ａ側では、充填樹脂７の
先端部７ａを研磨により平坦化して蓋メッキ３ｂした後
に、ビルドアップ層ＢＵを形成するため、絶縁層１０，
１６および配線層１４，２０を平坦に形成できる共に、
配線層１４などをファインパターンにして形成すること
も容易となる。従って、少ない工数により信頼性を有す
る配線基板１を安価に提供することができる。尚、コア
基板２の裏面２ｂに貼り付ける前記銅箔４を、表面２ａ
の銅箔３よりも厚肉としたり、その表面粗さを表面２ａ
の銅箔３よりも粗くした場合には、配線基板１がビルド
アップ層ＢＵ寄りに凹む反り変形を防止または抑制する
ことが可能となる。According to the method of manufacturing the wiring board 1 described above, the pair of core boards 2 and 2 having the through-hole conductor 6 and the back surface wiring layer 9 are provided on the back surface 2b of the core board 2 via the release sheet r. The filling resin 7 and the solder resist layer 11 can be simultaneously formed by a laminating step in which the formed adhesive layers 11 are laminated in a state of being opposed to each other, and pressure and heat are applied.
Moreover, on the front surface 2a side of each core substrate 2, since the tip portion 7a of the filling resin 7 is flattened by polishing and the lid plating 3b is performed, the buildup layer BU is formed, the insulating layer 10,
16 and the wiring layers 14 and 20 can be formed flat,
It is also easy to form the wiring layer 14 and the like in a fine pattern. Therefore, the wiring board 1 having reliability can be provided at a low cost with a small number of steps. The copper foil 4 attached to the back surface 2b of the core substrate 2 is attached to the front surface 2a.
Thicker than the copper foil 3 of, or the surface roughness of the surface 2a
When the wiring board 1 is rougher than the copper foil 3, it is possible to prevent or suppress the warp deformation in which the wiring board 1 is recessed toward the buildup layer BU.
【００２１】次に、異なる形態の配線基板３０の製造方
法を、図５〜図７により説明する。図５(Ａ)は、多層基
板のコア基板Ｋの断面を示し、図示のように、絶縁層３
１と、その表面３２および裏面３３上に形成した配線層
３４，３５と、これらの上に形成した絶縁層３６，３７
とからなる。かかる絶縁層３６，３７の表面３８，３９
には、前記同様の銅箔４０，４１が予め貼り付けられて
いる。尚、表面３８はコア基板Ｋの表面でもあり、表面
３９はコア基板Ｋの裏面でもある。上記絶縁層３１は、
平面視がほぼ正方形で且つ厚みが５００μｍ未満のガラ
スクロスまたはガラス繊維入りのエポキシ樹脂からな
る。また、配線層３４，３５は、厚さ１０数μｍの銅メ
ッキ層であり、絶縁層３６，３７は、ガラスフィラなど
の無機フィラを含む厚さ数１０μｍのエポキシ系樹脂か
らなる。かかるコア基板Ｋの全体の厚みは、約６００〜
８００μｍである。Next, a method of manufacturing the wiring board 30 having a different form will be described with reference to FIGS. FIG. 5A shows a cross section of the core substrate K of the multi-layer substrate, and as shown, the insulating layer 3
1, wiring layers 34 and 35 formed on the front surface 32 and the back surface 33, and insulating layers 36 and 37 formed on the wiring layers 34 and 35.
Consists of. Surfaces 38, 39 of such insulating layers 36, 37
Copper foils 40 and 41 similar to the above are previously attached to the. The front surface 38 is also the front surface of the core substrate K, and the front surface 39 is also the rear surface of the core substrate K. The insulating layer 31 is
It is made of glass cloth or glass fiber-containing epoxy resin having a substantially square shape in plan view and a thickness of less than 500 μm. The wiring layers 34 and 35 are copper-plated layers having a thickness of several tens of μm, and the insulating layers 36 and 37 are made of an epoxy resin having a thickness of several tens of μm and containing an inorganic filler such as a glass filler. The overall thickness of the core substrate K is about 600 to
It is 800 μm.
【００２２】上記コア基板Ｋの所定の位置にレーザを照
射するか、細径のドリルにて穿孔する。その結果、図５
(Ｂ)に示すように、コア基板Ｋにおける表面３８と裏面
３９との間を貫通し且つ内径が約１００μｍのスルーホ
ール４３が複数形成される。かかるスルーホール４３
は、その途中で配線層３４，３５の一部を貫通する。次
に、複数のスルーホール４３を有するコア基板Ｋの全面
に対し、無電解銅メッキおよび電解銅メッキを施す。
尚、各スルーホール４３の内壁には、予めＰｄなどを含
むメッキ触媒を塗布しておく。その結果、図５(Ｃ)に示
すように、各スルーホール４３の内壁表面に沿って厚み
が約１５μｍのスルーホール導体４４がそれぞれ形成さ
れ、それらの中間で配線層３４，３５と接続される。ま
た、銅箔４０，４１は、厚めの銅メッキ層４０ａ，４１
ａ(便宜上厚みは銅箔４０，４１と同じとする)となる。A predetermined position on the core substrate K is irradiated with a laser or is drilled with a small diameter drill. As a result,
As shown in (B), a plurality of through holes 43 penetrating between the front surface 38 and the back surface 39 of the core substrate K and having an inner diameter of about 100 μm are formed. Such through hole 43
Penetrates part of the wiring layers 34 and 35 in the middle. Next, electroless copper plating and electrolytic copper plating are applied to the entire surface of the core substrate K having the plurality of through holes 43.
A plating catalyst containing Pd or the like is previously applied to the inner wall of each through hole 43. As a result, as shown in FIG. 5C, through-hole conductors 44 each having a thickness of about 15 μm are formed along the inner wall surface of each through-hole 43, and are connected to the wiring layers 34 and 35 in the middle thereof. . In addition, the copper foils 40 and 41 are thicker copper plating layers 40a and 41.
a (for convenience, the thickness is the same as that of the copper foils 40 and 41).
【００２３】次いで、図６(Ａ)に示すように、コア基板
Ｋの裏面３９の銅メッキ層４１ａを、前記同様の方法に
より、所定パターンの裏面配線層４６とする。更に、コ
ア基板Ｋの裏面３９における銅メッキ層４１ａおよび裏
面配線層４６の下に、前記同様の接着層(プリフレグ)４
７を形成した後、図６(Ｂ)に示すように、離型シートｒ
を挟んで一対のコア基板Ｋの接着層４７，４７を対向し
て積層し、図６(Ｂ)中の矢印で示すように、コア基板
Ｋ，Ｋの厚み方向に沿って、図示しないホットプレスに
より加圧し且つ加熱する(積層工程)。Next, as shown in FIG. 6A, the copper plating layer 41a on the back surface 39 of the core substrate K is formed into a back wiring layer 46 having a predetermined pattern by the same method as described above. Further, below the copper plating layer 41a and the back surface wiring layer 46 on the back surface 39 of the core substrate K, the same adhesive layer (prefreg) 4 as described above is provided.
After forming 7, as shown in FIG. 6 (B), the release sheet r
The adhesive layers 47, 47 of the pair of core substrates K are laminated so as to face each other with the core sandwiched therebetween, and a hot press (not shown) is provided along the thickness direction of the core substrates K, K as shown by the arrow in FIG. 6 (B). And pressurize and heat (laminating step).
【００２４】その結果、図６(Ｂ)に示すように、各コア
基板Ｋの接着層４７は、所定の厚みを有するソルダーレ
ジスト層４７になると共に、各接着層４７の一部は、各
コア基板Ｋのスルーホール導体４４内側の中空部に充填
され、充填樹脂４５となる。かかる充填樹脂４５の先端
部４５ａは、前記同様の研磨により平坦化される。ま
た、各コア基板Ｋの表面３８の銅メッキ層４０ａは、前
記と同様に充填樹脂４５の先端部を蓋メッキされた後、
図７(Ａ)に示すように、所定パターンの表面配線層４８
とされる。As a result, as shown in FIG. 6 (B), the adhesive layer 47 of each core substrate K becomes a solder resist layer 47 having a predetermined thickness, and a part of each adhesive layer 47 partially covers each core. The resin is filled in the hollow portion inside the through-hole conductor 44 of the substrate K and becomes the filling resin 45. The tip portion 45a of the filling resin 45 is flattened by the same polishing as described above. Further, the copper plating layer 40a on the surface 38 of each core substrate K is capped with the tip portion of the filling resin 45 in the same manner as described above,
As shown in FIG. 7A, the surface wiring layer 48 having a predetermined pattern is formed.
It is said that
【００２５】次に、図７(Ａ)に示すように、何れかコア
基板Ｋの表面３８および表面配線層４８の上に、前記同
様の絶縁層５０，５６と配線層５４，６０と含むビルド
アップ層ＢＵを、前記同様の方法により形成する(ビル
ドアップ工程)。表面配線層４８、配線層５４，６０の
相互間には、前記同様のフィルドビア導体５２，５８が
形成され、最上層のソルダーレジスト層(絶縁層)６２に
は、配線層６０上から立設し且つ第１主面６４よりも高
く突出する前記同様のハンダバンプ６６が複数形成され
る。尚、残りのコア基板Ｋの表面３８の上方にも、上記
と同様にしてビルドアップ層ＢＵなどを形成する。Next, as shown in FIG. 7 (A), a build including the same insulating layers 50 and 56 and wiring layers 54 and 60 on the surface 38 and the surface wiring layer 48 of either core substrate K. The up layer BU is formed by the same method as described above (buildup process). Filled via conductors 52 and 58 similar to the above are formed between the surface wiring layer 48 and the wiring layers 54 and 60, and the uppermost solder resist layer (insulating layer) 62 is erected from above the wiring layer 60. In addition, a plurality of solder bumps 66 similar to the above that project higher than the first main surface 64 are formed. The buildup layer BU and the like are formed above the surface 38 of the remaining core substrate K in the same manner as above.
【００２６】そして、図７(Ｂ)に示すように、離型シー
トｒを除去して個別に分離したビルドアップ層ＢＵなど
を有するコア基板Ｋの裏面３９側のソルダーレジスト層
４７に、レーザ加工などにより所定の位置に開口部４９
を形成する。裏面配線層４６から延び且つ開口部４９内
から第２主面５３側に露出する配線５１は、その表面に
Ｎｉメッキ膜およびＡｕメッキ膜が被覆され、当該配線
基板３０自体を搭載する図示しないマザーボードなどの
プリント基板との接続端子となる。この結果、図７(Ｂ)
に示すように、ＩＣチップなどの半導体素子を実装する
直前の配線基板３０を得ることができる。Then, as shown in FIG. 7B, the solder resist layer 47 on the back surface 39 side of the core substrate K having the build-up layer BU and the like separated by removing the release sheet r is laser-processed. The opening 49 is put in place by
To form. The wiring 51 extending from the back surface wiring layer 46 and exposed from the opening 49 to the second main surface 53 side is covered with a Ni plating film and an Au plating film on the surface thereof, and the wiring board 30 itself is mounted on a mother board (not shown). It becomes a connection terminal with the printed circuit board. As a result, FIG. 7 (B)
As shown in, it is possible to obtain the wiring board 30 immediately before mounting a semiconductor element such as an IC chip.
【００２７】以上のような配線基板３０の製造方法によ
っても、スルーホール導体４４および裏面配線層４６を
有する一対のコア基板Ｋ，Ｋを、離型シートｒを介して
各コア基板Ｋの裏面３９に形成した接着層４７同士を対
向させて積層し加圧および加熱する積層工程により、充
填樹脂４５とソルダーレジスト層４７とが同時に形成で
きる。しかも、各コア基板Ｋの表面３８側では、充填樹
脂４５の先端部４５ａを研磨により平坦化し且つ蓋メッ
キした後に、ビルドアップ層ＢＵを形成するため、絶縁
層５０，５６および配線層５４，６０を平坦に形成でき
る共に、配線層５４などをファインパターンにして形成
することも容易となる。更に、コア基板Ｋ内にもスルー
ホール導体４４に接続する配線層３４，３５が形成され
ているため、配線の高密度化にも対応することができ
る。従って、少ない工数により信頼性を有する配線基板
３０を安価に提供することができる。Also by the method of manufacturing the wiring board 30 as described above, the pair of core boards K, K having the through-hole conductors 44 and the back surface wiring layer 46, the back surface 39 of each core board K via the release sheet r. The filling resin 45 and the solder resist layer 47 can be formed at the same time by the laminating step in which the adhesive layers 47 formed in the above are laminated so as to face each other and are pressed and heated. Moreover, on the surface 38 side of each core substrate K, the insulating layers 50 and 56 and the wiring layers 54 and 60 are formed in order to form the buildup layer BU after flattening the tip end portion 45a of the filling resin 45 by polishing and performing lid plating. Can be formed flat and the wiring layer 54 and the like can be easily formed in a fine pattern. Furthermore, since the wiring layers 34 and 35 connected to the through-hole conductors 44 are also formed in the core substrate K, it is possible to cope with high density wiring. Therefore, the wiring board 30 having reliability can be provided at a low cost with a small number of steps.
【００２８】本発明は以上において説明した形態に限定
されるものではない。本発明の製造方法には、前記接着
層１１，４７をコア基板２，Ｋのスルーホール５，４３
に直に充填する形態も含まれる。前記コア基板２，Ｋ
は、その裏面側に開口する凹部をルータ(座ぐり)加工に
より形成し、かかる凹部にチップコンデンサなどの電子
部品を実装したり、埋め込み樹脂により上記電子部品を
埋設して内蔵したものとしても良い。The present invention is not limited to the form described above. In the manufacturing method of the present invention, the adhesive layers 11 and 47 are provided in the through holes 5 and 43 of the core substrate 2 and K.
It also includes a form of directly filling. The core substrate 2, K
May have a recess opening on the back side thereof formed by router (counterbore) processing, and an electronic component such as a chip capacitor may be mounted in the recess, or the above electronic component may be embedded and embedded by an embedded resin. .
【００２９】前記コア基板２やコア基板Ｋの絶縁層３
１，３６などの材質は、前記ガラス−エポキシ樹脂系の
複合材料の他、ビスマレイミド・トリアジン(ＢＴ)樹
脂、エポキシ樹脂、同様の耐熱性、機械強度、可撓性、
加工容易性などを有するガラス織布や、ガラス織布など
のガラス繊維とエポキシ樹脂、ポリイミド樹脂、または
ＢＴ樹脂などの樹脂との複合材料であるガラス繊維−樹
脂系の複合材料を用いても良い。あるいは、ポリイミド
繊維などの有機繊維と樹脂との複合材料や、連続気孔を
有するＰＴＦＥなど３次元網目構造のフッ素系樹脂にエ
ポキシ樹脂などの樹脂を含浸させた樹脂−樹脂系の複合
材料などを用いることも可能である。また、前記表面配
線層８などやスルーホール導体６などの材質は、前記Ｃ
ｕの他、Ａｇ、Ｎｉ、Ｎｉ−Ａｕ系合金などにしても良
く、あるいは、これら金属のメッキ層を用いず、導電性
樹脂を塗布するなどの方法により形成しても良い。Insulating layer 3 of the core substrate 2 or core substrate K
The materials such as 1,36 are bismaleimide triazine (BT) resin, epoxy resin, similar heat resistance, mechanical strength, flexibility, in addition to the glass-epoxy resin-based composite material.
A glass woven fabric having easy processability, or a glass fiber-resin-based composite material which is a composite material of glass fibers such as a glass woven fabric and a resin such as an epoxy resin, a polyimide resin, or a BT resin may be used. . Alternatively, a composite material of an organic fiber such as a polyimide fiber and a resin, or a resin-resin composite material obtained by impregnating a fluorine-based resin having a three-dimensional network structure such as PTFE having continuous pores with a resin such as an epoxy resin is used. It is also possible. The material of the surface wiring layer 8 and the through hole conductor 6 is C
In addition to u, Ag, Ni, a Ni-Au alloy, or the like may be used, or a method of applying a conductive resin without using a plating layer of these metals may be used.
【００３０】更に、前記絶縁層１０，１６などの材質
は、前記エポキシ樹脂を主成分とするもののほか、同様
の耐熱性、パターン成形性などを有するポリイミド樹
脂、ＢＴ樹脂、ＰＰＥ樹脂、あるいは、連続気孔を有す
るＰＴＦＥなど３次元網目構造のフッ素系樹脂にエポキ
シ樹脂などの樹脂を含浸させた樹脂−樹脂系の複合材料
などを用いることもできる。尚、絶縁層の形成には、絶
縁性の樹脂フィルムを熱圧着する方法のほか、液状の樹
脂をロールコータにより塗布する方法を用いることもで
きる。尚また、絶縁層に混入するガラス布またはガラス
フィラの組成は、Ｅガラス、Ｄガラス、Ｑガラス、Ｓガ
ラスの何れか、またはこれらのうちの２種類以上を併用
したものとしても良い。また、ビア導体は、前記フィル
ドビア導体１２などでなく、内部が完全に導体で埋まっ
てない逆円錐形状のコンフォーマルビア導体とすること
もできる。あるいは、各ビア導体の軸心をずらしつつ積
み重ねるスタッガードの形態でも良いし、途中で平面方
向に延びる配線層が介在する形態としても良い。Further, the insulating layers 10 and 16 and the like are made of the above-mentioned epoxy resin as a main component, and also have polyimide resin, BT resin, PPE resin, or continuous resin having similar heat resistance and pattern formability. It is also possible to use a resin-resin-based composite material obtained by impregnating a resin such as epoxy resin with a fluorine-based resin having a three-dimensional network structure such as PTFE having pores. In addition to the method of thermocompression bonding the insulating resin film, a method of applying a liquid resin by a roll coater can be used for forming the insulating layer. The composition of the glass cloth or glass filler mixed in the insulating layer may be any one of E glass, D glass, Q glass, S glass, or a combination of two or more thereof. Further, the via conductor may be not the filled via conductor 12 or the like, but an inverted conical conformal via conductor whose inside is not completely filled with the conductor. Alternatively, the via conductors may be stacked in such a manner that the axial centers of the via conductors are displaced from each other, or a wiring layer extending in the planar direction may be interposed therebetween.
【００３１】[0031]
【発明の効果】本発明における第１の配線基板の製造方
法(請求項１)によれば、裏面に接着層を形成した一対の
コア基板を積層し加圧および加熱することで、２枚のコ
ア基板におけるスルーホールの穴埋めおよびコア基板の
裏面に位置するソルダーレジスト層を同時に形成できる
ため、工数を低減し且つ安価な配線基板を製造できる。
また、第２の配線基板の製造方法(請求項２)によれば、
裏面に接着層を形成した一対のコア基板を積層し加圧お
よび加熱することで、２枚のコア基板におけるスルーホ
ール導体内側の中空部の穴埋めおよびコア基板の裏面に
位置する所要厚さのソルダーレジスト層を同時に形成で
きる。従って、工数を低減し且つ安価な配線基板を確実
に製造することが可能となる。According to the first method of manufacturing a wiring board of the present invention (claim 1), a pair of core boards having an adhesive layer formed on the back surface thereof are laminated, and pressed and heated to form two wiring boards. Since it is possible to fill the through holes in the core substrate and form the solder resist layer located on the back surface of the core substrate at the same time, it is possible to reduce the number of steps and manufacture an inexpensive wiring substrate.
According to the second wiring board manufacturing method (claim 2),
By stacking a pair of core substrates having an adhesive layer formed on the back faces thereof, and applying pressure and heat, the hollow portions inside the through-hole conductors of the two core substrates are filled, and the solder of a required thickness located on the back faces of the core substrates. The resist layer can be formed at the same time. Therefore, it is possible to reduce the number of steps and reliably manufacture an inexpensive wiring board.
【００３２】更に、請求項３の配線基板の製造方法によ
れば、コア基板の裏面およびスルーホールまたはスルー
ホール導体の中空部に、それらの内径や内壁面の形態に
応じて、所望の流動性、接着性、強度、絶縁性などを有
する接着層(プリフレグ)を、容易にコア基板の裏面に形
成し且つスルーホールなどの穴埋めが行える。また、請
求項４の配線基板の製造方法によれば、スルーホールま
たはスルーホール導体内側の中空部の穴埋めが成された
後に、ビルドアップ層を形成するため、平坦な絶縁層お
よび配線層を形成できると共に、かかる配線層をファイ
ンパターンとすることもできる。加えて、請求項５の配
線基板の製造方法によれば、スルーホールなどを有する
コア基板の表面上方にビルドアップ層を有する配線基板
を、一層効率良く低コストで製造することが可能とな
る。Further, according to the method of manufacturing a wiring board of claim 3, desired fluidity is provided in the back surface of the core board and the hollow portion of the through hole or the through hole conductor depending on the shape of the inner diameter and the inner wall surface thereof. It is possible to easily form an adhesive layer (prefreg) having adhesiveness, strength, insulation, etc. on the back surface of the core substrate and fill holes such as through holes. Further, according to the method of manufacturing a wiring board of claim 4, since the build-up layer is formed after the through hole or the hollow portion inside the through hole conductor is filled, the flat insulating layer and the wiring layer are formed. At the same time, the wiring layer can have a fine pattern. In addition, according to the wiring board manufacturing method of the fifth aspect, it is possible to manufacture the wiring board having the buildup layer above the surface of the core substrate having the through holes and the like more efficiently and at low cost.
【図１】(Ａ)〜(Ｄ)は本発明の配線基板の製造方法にお
ける各工程を示す概略図。1A to 1D are schematic views showing each step in a method for manufacturing a wiring board according to the present invention.
【図２】(Ａ)，(Ｂ)は図１(Ｄ)に続く本発明の製造工程
を示す概略図。2 (A) and 2 (B) are schematic views showing the manufacturing process of the present invention following FIG. 1 (D).
【図３】(Ａ)，(Ｂ)は図２(Ｂ)に続く本発明の製造工程
を示す概略図。3 (A) and 3 (B) are schematic views showing the manufacturing process of the present invention following FIG. 2 (B).
【図４】(Ａ)，(Ｂ)は図３(Ｂ)に続く製造工程または得
られた配線基板を示す概略図。4 (A) and 4 (B) are schematic views showing a manufacturing process subsequent to FIG. 3 (B) or a wiring board obtained.
【図５】(Ａ)〜(Ｃ)は異なる形態の配線基板の製造方法
における各工程を示す概略図。5A to 5C are schematic views showing each step in a method of manufacturing a wiring board having a different form.
【図６】(Ａ)，(Ｂ)は図５(Ｃ)に続く本発明の製造工程
を示す概略図。6 (A) and 6 (B) are schematic views showing the manufacturing process of the present invention following FIG. 5 (C).
【図７】(Ａ)，(Ｂ)は図６(Ｂ)に続く製造工程または得
られた配線基板を示す概略図。7A and 7B are schematic views showing a manufacturing process subsequent to FIG. 6B or a wiring board obtained.
１，３０……………………配線基板 ２，Ｋ………………………コア基板 ２ａ，３８…………………表面 ２ｂ，３９…………………裏面 ５，４３……………………スルーホール ６，４４……………………スルーホール導体 ９，４６……………………裏面配線層 １１，４７…………………接着層 １０，１６，５０，５６…絶縁層 １４，２０，５４，６０…配線層 ＢＵ…………………………ビルドアップ層 ｒ……………………………離型シート 1,30 …………………… Wiring board 2, K ……………………………… Core substrate 2a, 38 …………………… The surface 2b, 39 …………………… Back side 5,43 …………………… Through hole 6,44 ………………………… Through hole conductor 9,46 …………………… Backside wiring layer 11,47 …………………… Adhesive layer 10, 16, 50, 56 ... Insulating layer 14, 20, 54, 60 ... Wiring layer BU ……………………………… Build-up layer r …………………………… Release sheet
Claims (5)
て、かかる表面と裏面との間を貫通するスルーホールを
形成し、且つ少なくともかかる裏面に裏面配線層を形成
する工程と、 上記コア基板の裏面に接着層を形成した一対のコア基板
を、それぞれの接着層を対向させ且つ離型シートを介し
て積層し、加圧および加熱することにより、上記接着層
の一部を上記スルーホールに充填する積層工程と、を含
む、 ことを特徴とする配線基板の製造方法。1. A core substrate having a front surface and a back surface, a step of forming a through hole penetrating between the front surface and the back surface, and forming a back wiring layer on at least the back surface, and a back surface of the core substrate. Lamination in which a pair of core substrates having an adhesive layer formed thereon are laminated with the respective adhesive layers facing each other and with a release sheet interposed therebetween, and by pressing and heating, a part of the adhesive layer is filled in the through hole. A method of manufacturing a wiring board, comprising:
て、少なくとも裏面に裏面配線層を形成すると共に、上
記表面と裏面との間を貫通し且つ上記裏面配線層と接続
するスルーホール導体を形成する工程と、 上記コア基板の裏面に接着層を形成した一対のコア基板
を、それぞれの接着層を対向させ且つ離型シートを介し
て積層し、加圧および加熱することにより、上記接着層
の一部を上記スルーホール導体の内側に位置する中空部
に充填する積層工程と、を含む、ことを特徴とする配線
基板の製造方法。2. A core substrate having a front surface and a back surface, wherein a back wiring layer is formed on at least the back surface, and a through hole conductor penetrating between the front surface and the back surface and connecting to the back wiring layer is formed. And a pair of core substrates each having an adhesive layer formed on the back surface of the core substrate, the adhesive layers facing each other and laminated via a release sheet, and pressed and heated to form a part of the adhesive layer. And a stacking step of filling the hollow portion located inside the through-hole conductor.
不織布、または合成繊維を含む樹脂である、 ことを特徴とする請求項１または２に記載の配線基板の
製造方法。3. The method for manufacturing a wiring board according to claim 1, wherein the adhesive layer is paper, glass cloth, glass non-woven fabric, or a resin containing synthetic fibers.
の表面上方に、複数の絶縁層および複数の配線層を含む
ビルドアップ層を形成するビルドアップ工程を有する、 ことを特徴とする請求項１乃至３の何れか一項に記載の
配線基板の製造方法。4. A build-up step of, after the stacking step, forming a build-up layer including a plurality of insulating layers and a plurality of wiring layers above the surfaces of the pair of core substrates. Item 4. A method of manufacturing a wiring board according to any one of Items 1 to 3.
の少なくとも一方は、前記コア基板をそれぞれ複数有す
る一対のパネルを用いて行われる、 ことを特徴とする請求項１乃至４の何れか一項に記載の
配線基板の製造方法。5. At least one of the stacking step and the build-up step is performed using a pair of panels each having a plurality of the core substrates, according to any one of claims 1 to 4. A method for manufacturing a wiring board as described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002128992A JP3725489B2 (en) | 2002-04-30 | 2002-04-30 | Wiring board manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002128992A JP3725489B2 (en) | 2002-04-30 | 2002-04-30 | Wiring board manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003324275A true JP2003324275A (en) | 2003-11-14 |
| JP3725489B2 JP3725489B2 (en) | 2005-12-14 |
Family
ID=29542566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002128992A Expired - Fee Related JP3725489B2 (en) | 2002-04-30 | 2002-04-30 | Wiring board manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3725489B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007180211A (en) * | 2005-12-27 | 2007-07-12 | Ngk Spark Plug Co Ltd | Core substrate for manufacturing wiring board and manufacturing method of wiring board |
| CN114340226A (en) * | 2021-12-29 | 2022-04-12 | 生益电子股份有限公司 | PCB manufacturing method and PCB |
-
2002
- 2002-04-30 JP JP2002128992A patent/JP3725489B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007180211A (en) * | 2005-12-27 | 2007-07-12 | Ngk Spark Plug Co Ltd | Core substrate for manufacturing wiring board and manufacturing method of wiring board |
| CN114340226A (en) * | 2021-12-29 | 2022-04-12 | 生益电子股份有限公司 | PCB manufacturing method and PCB |
| WO2023123904A1 (en) * | 2021-12-29 | 2023-07-06 | 生益电子股份有限公司 | Pcb manufacturing method and pcb |
| CN114340226B (en) * | 2021-12-29 | 2024-05-07 | 生益电子股份有限公司 | PCB manufacturing method and PCB |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3725489B2 (en) | 2005-12-14 |
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