JP2003197849A - Module with built-in component and method of manufacturing the same - Google Patents

Module with built-in component and method of manufacturing the same

Info

Publication number
JP2003197849A
JP2003197849A JP2002301043A JP2002301043A JP2003197849A JP 2003197849 A JP2003197849 A JP 2003197849A JP 2002301043 A JP2002301043 A JP 2002301043A JP 2002301043 A JP2002301043 A JP 2002301043A JP 2003197849 A JP2003197849 A JP 2003197849A
Authority
JP
Japan
Prior art keywords
component
insulating layer
semiconductor
module according
component built
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002301043A
Other languages
Japanese (ja)
Inventor
Toshiyuki Asahi
俊行 朝日
Yasuhiro Sugaya
康博 菅谷
Shingo Komatsu
慎五 小松
Yoshiyuki Yamamoto
義之 山本
Seiichi Nakatani
誠一 中谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002301043A priority Critical patent/JP2003197849A/en
Publication of JP2003197849A publication Critical patent/JP2003197849A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To enable a mounting test and a characteristics test before components are built in and thereby to increase an yield and the overall strength by embedding the components in an electrical insulation layer integrally with a wiring board. <P>SOLUTION: A module with built-in components includes an electrical insulation layer (101), interconnections (102 and 106) integrated on both surfaces of the electrical insulation layer (101), vias (103) for connecting the interconnections (102 and 106), and at least one component (104) selected among electronic components and semiconductors being embedded in the electrical insulation layer (101). Out of the interconnections (102 and 106), at least one interconnection is constituted of the interconnection (106) formed on the surface of a wiring board (109). The component (104) embedded in the electrical insulation layer (101) is mounted on the wiring board integrally with it before embedded. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、回路部品が電気絶
縁層の内部に配置される回路部品内蔵モジュール及びそ
の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit component built-in module in which a circuit component is arranged inside an electrically insulating layer and a method for manufacturing the same.

【０００２】[0002]

【従来の技術】近年の電子機器の高性能化・小型化の流
れの中、回路部品の高密度、高機能化が一層求められて
いる。回路部品を搭載したモジュールにおいても、高密
度、高機能化への対応が要求されている。回路部品を高
密度に実装する方法として、現在、配線板が多層化する
傾向にある。従来のガラスクロス−エポキシ樹脂含浸基
板では、ドリルによる貫通スルーホール構造を用いて多
層化しており、信頼性は高いが、高密度実装には適して
いない。このため、最も回路の高密度化が図れる方法と
して、インナービアによる接続を用いた多層配線板も使
用されている。インナービア接続により、ＬＳＩ間や部
品間の配線パターンを最短距離で接続でき、必要な各層
間のみの接続が可能となり、回路部品の実装性にも優れ
ている。また、配線パターンの微細化も高密度実装に不
可欠な技術であり、ライン アンドスペースが年々小さ
くなってきている。加えて、受動部品を基板内部に形成
した３次元実装が開発されている。2. Description of the Related Art With the recent trend toward higher performance and smaller size of electronic equipment, higher density and higher functionality of circuit components are required. It is also required that the module with circuit parts be equipped with high density and high functionality. As a method for mounting circuit components at a high density, wiring boards are currently tending to have multiple layers. The conventional glass cloth-epoxy resin-impregnated substrate has a multilayer structure using a through-hole structure with a drill and is highly reliable, but is not suitable for high-density mounting. For this reason, as a method for achieving the highest circuit density, a multilayer wiring board using connections by inner vias is also used. By the inner via connection, the wiring patterns between LSIs and parts can be connected in the shortest distance, and only necessary layers can be connected, and the mountability of circuit parts is also excellent. Also, miniaturization of wiring patterns is an essential technology for high-density mounting, and line and space are becoming smaller year by year. In addition, three-dimensional mounting has been developed in which passive components are formed inside the substrate.

【０００３】しかし、受動部品を基板内部に形成するた
めには、材料開発、形成精度、設備投資など課題が多
く、開発スピードも遅くなってしまう。However, in order to form the passive components inside the substrate, there are many problems such as material development, forming accuracy, and capital investment, and the development speed becomes slow.

【０００４】また、本出願人はすでに受動部品を基板内
部に内蔵することを提案している（特許文献１）。Further, the present applicant has already proposed to incorporate a passive component inside the substrate (Patent Document 1).

【０００５】[0005]

【特許文献１】特開平１１−２２０２６２号公報[Patent Document 1] Japanese Patent Laid-Open No. 11-220262

【０００６】[0006]

【発明が解決しようとする課題】しかし、前記特許文献
１の実施例によれば、部品を基板内部に埋め込んだ後に
配線を形成するので、内蔵前に半導体などの部品を実装
検査したり特性検査を行えないという問題があった。ま
た、配線基板を一体化して埋め込まないので、強度があ
まり高くないという問題もあった。However, according to the embodiment of the above-mentioned patent document 1, since the wiring is formed after the components are embedded in the substrate, the components such as semiconductors can be mounted and inspected before the mounting. There was a problem that you can not do. Further, since the wiring board is not integrated and embedded, there is a problem that the strength is not so high.

【０００７】本発明は、前記従来の問題を解決するた
め、内蔵前に半導体などの部品を実装検査したり特性検
査ができ、歩留まりを向上でき、強度を高くでき、生産
性が高く、高密度実装可能な部品内蔵モジュールを提供
することを目的とする。In order to solve the above-mentioned conventional problems, the present invention enables mounting inspection and characteristics inspection of parts such as semiconductors before embedding, yield improvement, high strength, high productivity and high density. An object is to provide a component built-in module that can be mounted.

【０００８】[0008]

【課題を解決するための手段】前記目的を達成するた
め、本発明の部品内臓モジュールは、電気絶縁層と、前
記電気絶縁層の両表面に一体化された配線と、前記配線
間を接続するビアを含み、前記電気絶縁層の内部に、電
子部品及び半導体から選ばれる少なくとも一つの部品が
埋め込まれた部品内蔵モジュールであって、前記配線の
少なくとも一方は、配線基板の表面に形成された配線で
あり、前記電気絶縁層の内部に埋め込まれた部品は、埋
め込まれる前に前記配線基板上に搭載され一体化されて
いることを特徴とする。In order to achieve the above-mentioned object, the component built-in module of the present invention connects an electrical insulating layer, wirings integrated on both surfaces of the electrical insulating layer, and the wirings. A component built-in module including a via, wherein at least one component selected from an electronic component and a semiconductor is embedded in the electrical insulation layer, wherein at least one of the wirings is a wiring formed on a surface of a wiring board. The component embedded inside the electrical insulation layer is mounted and integrated on the wiring board before being embedded.

【０００９】また、本発明の部品内蔵モジュールの製造
方法は、電気絶縁層と、前記電気絶縁層の両表面に一体
化された配線と、前記配線間を接続するビアを含み、前
記電気絶縁層の内部に、電子部品及び半導体から選ばれ
る少なくとも一つの部品が埋め込まれた部品内蔵モジュ
ールの製造方法であって、前記配線の少なくとも一方
は、配線基板の表面に形成された配線で構成し、前記配
線基板に半導体及び電子部品から選ばれる少なくとも一
つの部品を実装し、半硬化状態の熱硬化性樹脂からなる
電気絶縁層の厚さ方向にビアを形成し、前記配線基板を
外側にして前記部品を前記電気絶縁層に埋め込み、前記
電気絶縁層を硬化することを含むことを特徴とする。Further, the method for manufacturing a component built-in module of the present invention includes an electrical insulating layer, wirings integrated on both surfaces of the electrical insulating layer, and vias connecting the wirings. A method for manufacturing a component built-in module, in which at least one component selected from an electronic component and a semiconductor is embedded inside, wherein at least one of the wirings is configured by a wiring formed on a surface of a wiring board, At least one component selected from semiconductors and electronic components is mounted on the wiring board, a via is formed in the thickness direction of the electrical insulating layer made of a thermosetting resin in a semi-cured state, and the wiring board is placed outside and the component is formed. Embedded in the electrical insulation layer and curing the electrical insulation layer.

【００１０】[0010]

【発明の実施の形態】本発明は、電気絶縁層と、前記電
気絶縁層の両主平面の配線パターン及び配線基板から選
ばれる少なくとも一つの配線と、前記配線間を接続する
ビアを含み、前記電気絶縁層の内部に、電子部品及び半
導体から選ばれる少なくとも一つの部品が埋め込まれた
部品内蔵モジュールである。前記配線の少なくとも一つ
は配線基板であり、前記電気絶縁層の内部に埋め込まれ
た部品は、埋め込まれる前に前記配線基板上に搭載され
一体化されている。これにより、内蔵前に半導体などの
部品を実装検査したり特性検査ができる。その結果、歩
留まりを向上できる。また、配線基板を一体化して埋め
込むので、強度を高くできる。また、生産性が高く、高
密度実装可能な部品内蔵モジュールを提供できる。前記
において、部品を埋め込むとは、前記電気絶縁層の内部
に完全に埋没させることをいう。BEST MODE FOR CARRYING OUT THE INVENTION The present invention includes an electrical insulating layer, at least one wiring selected from wiring patterns on both main planes of the electrical insulating layer and a wiring board, and a via connecting the wirings, It is a component built-in module in which at least one component selected from an electronic component and a semiconductor is embedded inside an electrically insulating layer. At least one of the wirings is a wiring board, and the component embedded in the electrical insulation layer is mounted and integrated on the wiring board before being embedded. As a result, it is possible to carry out a mounting inspection and a characteristic inspection of a component such as a semiconductor before embedding. As a result, the yield can be improved. Further, since the wiring board is integrally embedded, the strength can be increased. Further, it is possible to provide a component built-in module having high productivity and capable of high-density mounting. In the above description, embedding a component means completely embedding it inside the electrical insulating layer.

【００１１】本発明においては、前記配線板が両面基板
又は多層配線板であることが好ましい。これにより、複
雑な回路形成が容易となる。In the present invention, the wiring board is preferably a double-sided board or a multilayer wiring board. This facilitates complex circuit formation.

【００１２】また本発明においては、前記電気絶縁層内
部の電子部品及び／又は半導体（以下総称して「部品」
ともいう。）を、前記電気絶縁層の両主平面の配線パタ
ーン及び／又は配線板に実装したことが好ましい。両主
平面に部品を実装し、電気絶縁層に内蔵することによ
り、部品内蔵層がより高密度なモジュールを提供でき
る。Further, in the present invention, electronic parts and / or semiconductors (hereinafter collectively referred to as “parts”) inside the electric insulating layer are provided.
Also called. Is preferably mounted on the wiring patterns and / or the wiring board on both main planes of the electrical insulating layer. By mounting the components on both main planes and embedding them in the electrical insulation layer, it is possible to provide a module with a higher density of the component-embedded layer.

【００１３】また本発明においては、前記部品を前記電
気絶縁層の主平面に対する法線方向において、ずらして
配置したことが好ましい。これにより、実装機の部品実
装間隔より、高密度に部品を配置できる。また、電気絶
縁層の厚みを低減でき、高密度化につながる。Further, in the present invention, it is preferable that the components are arranged so as to be displaced from each other in a direction normal to the main plane of the electrical insulating layer. As a result, components can be arranged at a higher density than the component mounting intervals of the mounting machine. In addition, the thickness of the electrically insulating layer can be reduced, leading to higher density.

【００１４】また、前記電気絶縁層内部に配置し、前記
電気絶縁層の両主平面の配線パターン及び／又は配線板
に実装した部品間にシールド層を挿入したことが好まし
い。これにより、内蔵した部品間の干渉、内蔵した部品
に対する外部からの干渉、内蔵した部品から外部への放
射のいずれか又は全部を低減でき、モジュールの特性を
向上させることができる。Further, it is preferable that a shield layer is disposed inside the electric insulation layer and a shield layer is inserted between wiring patterns on both main planes of the electric insulation layer and / or components mounted on a wiring board. As a result, any or all of interference between built-in components, external interference with the built-in components, and radiation from the built-in components to the outside can be reduced, and the characteristics of the module can be improved.

【００１５】また、前記シールド層が、金属箔配線パタ
ーンであるか、電磁シールド材であることが好ましい。
金属箔配線パターンを用いた場合、配線パターンの形成
と同様の工程でシールド層を形成でき生産が容易であ
る。電磁シールド材を用いた場合、電気絶縁層の材質を
変更するだけで作成でき、工程上の変更もなく干渉を低
減することができる。Further, it is preferable that the shield layer is a metal foil wiring pattern or an electromagnetic shield material.
When the metal foil wiring pattern is used, the shield layer can be formed in the same process as the formation of the wiring pattern, and the production is easy. When an electromagnetic shield material is used, it can be created by simply changing the material of the electric insulating layer, and interference can be reduced without any change in the process.

【００１６】また、前記配線パターン及び／又は配線板
の前記電気絶縁層と反対側の主平面に、部品を実装した
ことが好ましい。これにより、電気絶縁層だけではな
く、反対側の主平面にも部品を実装でき、高密度化が図
れる。Further, it is preferable that a component is mounted on the main surface of the wiring pattern and / or the wiring board opposite to the electric insulating layer. As a result, not only the electrical insulating layer but also the component can be mounted on the main surface on the opposite side, and the density can be increased.

【００１７】また、前記電子部品がディスクリート部品
であることが好ましい。これにより、内蔵する部品を新
規に開発する必要が無く、モジュール自体の開発スピー
ドが向上する。また、既存のディスクリート部品の信頼
性、精度を利用することができ、モジュールの特性が向
上する。前記においてディスクリート部品とは、例えば
インダクタンス、キャパシタンス、抵抗等の汎用のチッ
プ部品をいう。以下において、インダクタンス、キャパ
シタンス及び抵抗を総称して「ＬＣＲ」ともいう。Further, it is preferable that the electronic component is a discrete component. As a result, it is not necessary to newly develop a built-in component, and the development speed of the module itself is improved. Further, the reliability and accuracy of the existing discrete parts can be used, and the characteristics of the module are improved. In the above description, the discrete component refers to a general-purpose chip component such as an inductance, a capacitance and a resistance. In the following, the inductance, capacitance and resistance are collectively referred to as “LCR”.

【００１８】また、前記半導体が半導体ベアチップであ
ることが好ましい。これにより、半導体パッケージと比
較して、より低面積でモジュールを作成でき、高密度な
モジュールを提供できる。The semiconductor is preferably a semiconductor bare chip. As a result, compared to the semiconductor package, it is possible to create a module with a smaller area and provide a high-density module.

【００１９】また、前記半導体ベアチップが前記配線パ
ターン及び／又は配線板にフリップチップボンディング
接続されていることが好ましい。これにより、短配線
化、高密度実装化が図れる。The semiconductor bare chip is preferably flip-chip bonded to the wiring pattern and / or the wiring board. As a result, short wiring and high density mounting can be achieved.

【００２０】また、前記半導体ベアチップが研削及び／
又は研磨されていることが好ましい。これにより、半導
体の厚みを低減でき、モジュールの低背化に効果があ
る。The semiconductor bare chip is ground and / or
Alternatively, it is preferably polished. As a result, the thickness of the semiconductor can be reduced, which is effective in reducing the height of the module.

【００２１】前記製造方法においては、前記電気絶縁層
を硬化する工程後、部品を配線パターン及び／又は配線
板に実装する工程を含むことが好ましい。これにより、
本発明の部品内蔵モジュールを効率よく製造することが
できる。It is preferable that the manufacturing method includes a step of mounting a component on a wiring pattern and / or a wiring board after the step of curing the electric insulating layer. This allows
The component built-in module of the present invention can be efficiently manufactured.

【００２２】また、前記半導体を実装前に半導体ウエハ
で研削及び／又は研磨を行うことが好ましい。これによ
り、半導体の薄型化をウエハで一括に行うことができ、
生産性が向上できる。Further, it is preferable to grind and / or polish a semiconductor wafer before mounting the semiconductor. This makes it possible to reduce the thickness of semiconductors on a wafer all at once,
Productivity can be improved.

【００２３】また、前記半導体を実装後に配線板を固定
及び搬送に用いて研削及び／又は研磨を行うことが好ま
しい。これにより、薄型化した半導体を取り扱うことな
く、本発明の部品内蔵モジュールを製造することができ
る。Further, it is preferable to grind and / or polish by using the wiring board for fixing and carrying after mounting the semiconductor. As a result, the component built-in module of the present invention can be manufactured without handling a thinned semiconductor.

【００２４】また、前記部品を電気絶縁層に埋設する工
程と、前記電気絶縁層を硬化する工程を同時に行うこと
が好ましい。これにより、工程数を低減して、本発明の
部品内蔵モジュールを製造することができる。It is preferable that the step of embedding the component in the electrical insulation layer and the step of curing the electrical insulation layer are performed simultaneously. As a result, the number of steps can be reduced and the component built-in module of the present invention can be manufactured.

【００２５】また、前記シールド層を形成する工程を、
銅箔配線パターンを形成することによって行うことが好
ましい。これにより、本発明の部品内蔵モジュールを効
率よく製造することができる。Further, the step of forming the shield layer includes
It is preferably performed by forming a copper foil wiring pattern. As a result, the component built-in module of the present invention can be efficiently manufactured.

【００２６】また、前記シールド層を形成する工程を、
電磁シールド層を積層することによって行うことが好ま
しい。これにより、本発明の部品内蔵モジュールを効率
よく製造することができる。Further, the step of forming the shield layer includes
It is preferably performed by laminating an electromagnetic shield layer. As a result, the component built-in module of the present invention can be efficiently manufactured.

【００２７】また本発明においては、前記電気絶縁層内
部に部品を対向して配置させてもよい。とくに、高さの
高い部品と低い部品が混在する場合、高さの低い部品を
対向して配置させると、高密度に充填できる。Further, in the present invention, components may be arranged inside the electric insulating layer so as to face each other. In particular, when high-height parts and low-height parts coexist, if the low-height parts are arranged facing each other, high-density filling can be achieved.

【００２８】また、前記電気絶縁層の厚み方向の熱膨張
係数が、ビアの熱膨張係数の１０倍以下としても良い。
このようにすると、部品内蔵モジュールの外側にさらに
部品を搭載する場合、例えばはんだリフロー工程を通過
させても、電気絶縁層の厚み方向の膨脹率があまり大き
くならないので、ビアの導通が破壊されることがない。The coefficient of thermal expansion in the thickness direction of the electrical insulating layer may be 10 times or less than the coefficient of thermal expansion of the via.
With this configuration, when a component is further mounted on the outside of the component built-in module, the expansion coefficient in the thickness direction of the electrical insulating layer does not increase so much even if it passes through the solder reflow process, so that the conduction of the via is destroyed. Never.

【００２９】（実施の形態１）以下、本発明の実施の形
態について図面を参照して説明する。図１は本実施の形
態における部品内蔵モジュールの断面図である。図１に
おいて、部品内蔵モジュールは、電気絶縁層１０１と、
配線パターン１０２と、ビア１０３と、部品１０４と、
はんだ１０５とを有し、さらに配線パターン１０６，１
０８とインナービア１０７を有する両面基板１０９とを
含んでいる。(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a component built-in module according to the present embodiment. In FIG. 1, the component built-in module includes an electrically insulating layer 101,
The wiring pattern 102, the via 103, the component 104,
And a wiring pattern 106, 1
08 and a double-sided substrate 109 having an inner via 107.

【００３０】電気絶縁層１０１は、例えば、絶縁性樹脂
及びフィラと絶縁性樹脂の混合物等を用いることができ
る。電気絶縁層は、樹脂とフィラーを含み、フィラー含
量が５０質量％以上９５質量％以下であることが好まし
い。また、ガラスクロス等の補強材があってもよい。絶
縁性樹脂としては、熱硬化性樹脂や、熱可塑樹脂、光硬
化性樹脂等を用いることができ、耐熱性の高いエポキシ
樹脂やフェノール樹脂、イソシアネート樹脂を用いるこ
とにより、電気絶縁層１０１の耐熱性をあげることがで
きる。また、誘電正接の低いフッ素樹脂例えばポリテト
ラフルオロエチレン（ＰＴＦＥ樹脂）、ＰＰＯ（ポリフ
ェニレンオキサイド）樹脂（ＰＰＥ（ポリフェニレンエ
ーテル）樹脂ともいう）、液晶ポリマーを含むもしくは
それらの樹脂を変性させた樹脂を用いることにより、電
気絶縁層の高周波特性が向上する。電気絶縁層１０１と
して、フィラと絶縁性樹脂の混合物を用いた場合、フィ
ラ及び絶縁性樹脂を選択することによって、電気絶縁層
１０１の線膨張係数、熱伝導度、誘電率などを容易に制
御することができる。たとえば、フィラとしてアルミ
ナ、マグネシア、窒化ホウ素、窒化アルミ、窒化珪素、
ポリテトラフルオロエチレン及び、シリカなどを用いる
ことができる。アルミナ、窒化ホウ素、窒化アルミを用
いることにより、従来のガラス−エポキシ基板より熱伝
導度の高い基板が製作可能となり、内蔵された電子部品
１０４の発熱を効果的に放熱させることができる。ま
た、アルミナはコストが安いという利点もある。シリカ
を用いた場合、誘電率が低い電気絶縁層１０１が得ら
れ、比重も軽いため、携帯電話などの高周波用途として
好ましい。窒化珪素やポリテトラフルオロエチレン、例
えば”テフロン”（デュポン社登録商標）を用いても誘
電率の低い電気絶縁層を形成できる。また、窒化ホウ素
を用いることにより線膨張係数を低減できる。さらに分
散剤、着色剤、カップリング剤又は離型剤を含んでいて
もよい。分散剤によって、絶縁性樹脂中のフィラを均一
性よく分散させることができる。着色剤によって、電気
絶縁層を着色することができるため、自動認識装置の利
用が容易となる。カップリング剤によって、絶縁性樹脂
とフィラとの接着強度を高くすることができるため、電
気絶縁層１０１の絶縁性を向上できる。離型剤によっ
て、金型と混合物との離型性を向上できるため、生産性
を向上できる。For the electric insulating layer 101, for example, an insulating resin and a mixture of a filler and an insulating resin can be used. The electric insulating layer contains a resin and a filler, and the filler content is preferably 50% by mass or more and 95% by mass or less. There may be a reinforcing material such as glass cloth. As the insulating resin, a thermosetting resin, a thermoplastic resin, a photocurable resin, or the like can be used. By using an epoxy resin, a phenol resin, or an isocyanate resin having high heat resistance, the heat resistance of the electric insulating layer 101 can be improved. You can improve your sex. Further, a fluororesin having a low dielectric loss tangent, for example, polytetrafluoroethylene (PTFE resin), PPO (polyphenylene oxide) resin (also referred to as PPE (polyphenylene ether) resin), a resin containing a liquid crystal polymer or a resin obtained by modifying these resins is used. As a result, the high frequency characteristics of the electrical insulating layer are improved. When a mixture of a filler and an insulating resin is used as the electric insulating layer 101, the linear expansion coefficient, the thermal conductivity, the dielectric constant, etc. of the electric insulating layer 101 can be easily controlled by selecting the filler and the insulating resin. be able to. For example, as filler, alumina, magnesia, boron nitride, aluminum nitride, silicon nitride,
Polytetrafluoroethylene, silica, etc. can be used. By using alumina, boron nitride, or aluminum nitride, a substrate having higher thermal conductivity than the conventional glass-epoxy substrate can be manufactured, and the heat generated by the built-in electronic component 104 can be effectively dissipated. Alumina also has the advantage of low cost. When silica is used, the electric insulating layer 101 having a low dielectric constant can be obtained and the specific gravity is also light, so that it is preferable for high frequency applications such as mobile phones. An electrically insulating layer having a low dielectric constant can also be formed by using silicon nitride or polytetrafluoroethylene such as "Teflon" (registered trademark of DuPont). Further, the coefficient of linear expansion can be reduced by using boron nitride. Further, it may contain a dispersant, a coloring agent, a coupling agent or a releasing agent. The filler in the insulating resin can be dispersed with good uniformity by the dispersant. Since the electrically insulating layer can be colored with the colorant, the automatic recognition device can be easily used. Since the adhesive strength between the insulating resin and the filler can be increased by the coupling agent, the insulating property of the electric insulating layer 101 can be improved. The mold release agent can improve the mold releasability between the mold and the mixture, thus improving the productivity.

【００３１】配線パターン１０２は、電気伝導性を有す
る物質からなり、例えば金属箔や導電性樹脂組成物、金
属板を加工したリードフレームを用いることができる。
金属箔やリードフレームを用いることにより、エッチン
グ等により微細な配線パターンの作成が容易となる。ま
た、金属箔においては、離型フィルムを用いた転写等に
よる配線パターンの形成も可能となる。特に銅箔はコス
トも安く、電気伝導性も高いため好ましい。また、離型
フィルム上に配線パターンを形成することにより、配線
パターンが取り扱いやすくなる。また、導電性樹脂組成
物を用いることにより、スクリーン印刷等による、配線
パターンの製作が可能となる。リードフレームを用いる
ことにより、電気抵抗の低い、厚みのある金属を使用で
きる。また、エッチングによる微細パターン化や打ち抜
き加工等の簡易な製造法が使える。また、これらの配線
パターン１０２は表面にメッキ処理をする事により、耐
食性や電気伝導性を向上させることができる。また、配
線パターン１０２の電気絶縁層１０１との接触面を粗化
することで、電気絶縁層１０１との接着性を向上させる
ことができる。また、カプラーやフィルター等を配線パ
ターンで形成することも可能である。配線パターン１０
２は、表層側にも半導体及び／又は電子部品を実装して
もよい。The wiring pattern 102 is made of a material having electrical conductivity, and for example, a metal foil, a conductive resin composition, or a lead frame obtained by processing a metal plate can be used.
By using a metal foil or a lead frame, it is easy to create a fine wiring pattern by etching or the like. In addition, in the metal foil, it is possible to form a wiring pattern by transfer or the like using a release film. In particular, copper foil is preferable because it is inexpensive and has high electric conductivity. Further, by forming the wiring pattern on the release film, the wiring pattern can be easily handled. Further, by using the conductive resin composition, it is possible to manufacture a wiring pattern by screen printing or the like. By using the lead frame, a thick metal having low electric resistance can be used. Further, a simple manufacturing method such as fine patterning by etching or punching can be used. Further, by plating the surface of these wiring patterns 102, corrosion resistance and electric conductivity can be improved. Further, by roughening the contact surface of the wiring pattern 102 with the electric insulating layer 101, the adhesiveness with the electric insulating layer 101 can be improved. It is also possible to form a coupler, a filter, etc. with a wiring pattern. Wiring pattern 10
2, semiconductor and / or electronic components may be mounted on the surface side as well.

【００３２】ビア１０３は、配線パターン１０２間を接
続する機能を有し、たとえば、熱硬化性の導電性物質か
らなる。熱硬化性の導電性物質としては、たとえば、金
属粒子と熱硬化性樹脂とを混合した導電性樹脂組成物を
用いることができる。金属粒子としては、金、銀、銅又
はニッケルなどを用いることができる。金、銀、銅又は
ニッケルは導電性が高いため好ましく、銅は導電性が高
くマイグレーションも少ないため特に好ましい。銅を銀
で被覆した金属粒子を用いても、マイグレーションの少
なさと導電性の高さ、両方の特性を満たすことができ
る。熱硬化性樹脂としては、たとえば、エポキシ樹脂、
フェノール樹脂又はイソシアネート樹脂を用いることが
できる。エポキシ樹脂は、耐熱性が高いため特に好まし
い。また、ビア１０４は、ビアホール形成後、メッキす
ることによっても形成できる。また、金属と半田の組み
合わせ等で形成してもよい。The via 103 has a function of connecting the wiring patterns 102, and is made of, for example, a thermosetting conductive material. As the thermosetting conductive substance, for example, a conductive resin composition obtained by mixing metal particles and a thermosetting resin can be used. As the metal particles, gold, silver, copper or nickel can be used. Gold, silver, copper, or nickel is preferable because it has high conductivity, and copper is particularly preferable because it has high conductivity and less migration. Even when the metal particles in which copper is coated with silver are used, both characteristics of low migration and high conductivity can be satisfied. As the thermosetting resin, for example, epoxy resin,
Phenolic resins or isocyanate resins can be used. Epoxy resins are particularly preferable because they have high heat resistance. The via 104 can also be formed by plating after forming a via hole. Alternatively, it may be formed of a combination of metal and solder.

【００３３】電子部品１０４は、例えば、コンデンサ、
インダクタ、抵抗（ＬＣＲ）等のチップ部品や、ダイオ
ード、サーミスタ、スイッチ等を用いることができる。
ディスクリート部品を内蔵することで、新たに内蔵部品
を開発する必要がなくなる。また、精度や温度特性など
用途に応じた部品を既存の部品を使用でき、信頼性の向
上につながる。また、印刷抵抗や薄膜コンデンサ・イン
ダクタ等を形成しても良い。The electronic component 104 is, for example, a capacitor,
Chip components such as an inductor and a resistor (LCR), a diode, a thermistor, and a switch can be used.
Incorporating discrete components eliminates the need to develop new internal components. In addition, existing parts can be used as parts according to applications such as accuracy and temperature characteristics, which leads to improvement in reliability. Further, a printed resistor, a thin film capacitor, an inductor, etc. may be formed.

【００３４】半田１０５は、配線パターン１０２に電子
部品１０４を実装するために用いる。高温半田を用いた
場合、モジュールをリフローで実装する際の半田の再溶
融を防止できる。また、鉛フリー半田を用いることで環
境への負荷を軽減できる。本実施の形態では半田を用い
たが、導電性接着剤等を用いてもよい。The solder 105 is used to mount the electronic component 104 on the wiring pattern 102. When high temperature solder is used, remelting of the solder when mounting the module by reflow can be prevented. Also, the use of lead-free solder can reduce the load on the environment. Although solder is used in this embodiment, a conductive adhesive or the like may be used.

【００３５】両面基板１０９としては、ガラス織物にエ
ポキシ樹脂を含浸させた基板（ガラス−エポキシ基
板）、アラミド繊維不織布にエポキシ樹脂を含浸させた
基板（アラミド−エポキシ基板）、紙にフェノール樹脂
を含浸させた基板（紙−フェノール基板）、セラミック
ス基板など任意の基板から目的に応じて選択し使用でき
る。As the double-sided substrate 109, a glass fabric impregnated with epoxy resin (glass-epoxy substrate), a aramid fiber nonwoven fabric impregnated with epoxy resin (aramid-epoxy substrate), and paper impregnated with phenol resin. It can be selected and used according to the purpose from arbitrary substrates such as a substrate (paper-phenol substrate) and a ceramic substrate.

【００３６】例えばガラス−エポキシ基板を用いた両面
基板の上に部品を搭載し、検査し、その後、電気的絶縁
層に埋め込んだ部品内蔵モジュール（実施の形態１）
と、基板を用いずに部品を単体で電気的絶縁層に埋め込
み、その後に表面に配線パターンを形成したモジュール
との強度を比較すると、基板の種類、コンポジットのセ
ラミックの種類、量、厚み等によっても異なるが、平均
的には、実施の形態１のほうが曲げ強度は約１．３倍程
度高くなる。For example, a component built-in module in which components are mounted on a double-sided substrate using a glass-epoxy substrate, inspected, and then embedded in an electrically insulating layer (first embodiment).
When comparing the strength with a module in which a component is embedded alone in an electrically insulating layer without using a substrate and then a wiring pattern is formed on the surface, it can be determined by the type of substrate, the type of composite ceramic, the amount, the thickness, etc. However, on the average, the bending strength of the first embodiment is about 1.3 times higher.

【００３７】（実施の形態２）この実施形態２では、図
１に示した部品内蔵モジュールの製造方法の一実施形態
を説明する。実施形態２で用いられる材料は、実施形態
１で説明したものである。図２Ａ−図２Ｄは部品内蔵モ
ジュールの製造工程の一実施形態を示す断面図である。
図２Ａに示すように、未硬化の電気絶縁層２０１にスル
ーホール２０７を形成する。電気絶縁層２０１として
は、絶縁性樹脂やフィラと絶縁性樹脂との混合物等を用
いることができる。最初にフィラと絶縁性樹脂を混合
し、攪拌することによって、ペースト状の絶縁性樹脂混
合物を作製する。絶縁性樹脂混合物には粘度を調整する
ために溶剤を添加しても良い。この絶縁性樹脂混合物を
シート形状に成形することによって電気絶縁層２０１を
形成できる。シート形状に成形する方法としては、例え
ば、ドクターブレード法等を用いることによって、フィ
ルム上に作成することができる。電気絶縁層２０１は、
硬化温度以下で乾燥させることによって、粘着性を低下
させることができる。この熱処理によって、板状の電気
絶縁層の粘着性が失われるため、フィルムとの剥離が容
易になる。半硬化状態（Ｂステージ）にすることによ
り、取り扱いが容易となる。スルーホール２０７の形成
は、たとえば、レーザー加工やドリル加工、パンチング
加工によって作製することができる。レーザー加工は微
細なピッチでビアを形成することができ、削りくずも発
生しないため望ましい。レーザー加工の場合、炭酸ガス
レーザーやＹＡＧレーザー、エキシマレーザー等を用い
ることができる。また、ドリル加工、パンチング加工の
場合、汎用性のある既存の設備でのスルーホール形成が
容易である。未硬化状態の電気絶縁層２０１を用いるこ
とで加工がしやすくなる。(Second Embodiment) In the second embodiment, an embodiment of a method of manufacturing the component built-in module shown in FIG. 1 will be described. The materials used in the second embodiment are the same as those described in the first embodiment. 2A to 2D are cross-sectional views showing an embodiment of a manufacturing process of a component built-in module.
As shown in FIG. 2A, through holes 207 are formed in the uncured electric insulation layer 201. As the electric insulating layer 201, an insulating resin, a mixture of a filler and an insulating resin, or the like can be used. First, the filler and the insulating resin are mixed and stirred to prepare a paste-like insulating resin mixture. A solvent may be added to the insulating resin mixture to adjust the viscosity. The electrically insulating layer 201 can be formed by molding this insulating resin mixture into a sheet shape. As a method of forming into a sheet shape, for example, a doctor blade method or the like can be used to form on a film. The electrical insulation layer 201 is
By drying below the curing temperature, the tackiness can be reduced. Due to this heat treatment, the plate-like electric insulating layer loses its adhesiveness, so that it can be easily peeled off from the film. The semi-cured state (B stage) facilitates handling. The through hole 207 can be formed by, for example, laser processing, drill processing, or punching processing. Laser processing is desirable because vias can be formed with a fine pitch and no shavings are generated. In the case of laser processing, a carbon dioxide gas laser, a YAG laser, an excimer laser or the like can be used. Further, in the case of drilling or punching, it is easy to form through holes in existing equipment having general versatility. The use of the uncured electric insulating layer 201 facilitates processing.

【００３８】別にキャリア２０６上に配線パターン２０
２を形成したものを準備する。配線パターン２０２は、
エッチング、印刷といった方法を用いて形成することが
できる。特にエッチングでは、フォトリソ工法など微細
な配線パターンの形成法を利用できる。キャリアとして
は、ＰＥＴ（ポリエチレンテレフタレート）やＰＰＳ
（ポリフェニレンサルファイト）の様な樹脂フィルムの
他、銅箔、アルミ箔の様な金属箔等を用いることができ
る。キャリア２０６を用いることにより、配線パターン
２０２の取り扱いが容易となる。また、配線パターン２
０２とキャリア２０６の間に配線パターン２０２をはが
しやすくするために剥離層があってもよい。Separately, the wiring pattern 20 is formed on the carrier 206.
Prepare what formed 2. The wiring pattern 202 is
It can be formed using a method such as etching or printing. Particularly in etching, a method for forming a fine wiring pattern such as a photolithography method can be used. As a carrier, PET (polyethylene terephthalate) or PPS
Besides a resin film such as (polyphenylene sulfite), a metal foil such as a copper foil or an aluminum foil can be used. By using the carrier 206, the wiring pattern 202 can be easily handled. Also, the wiring pattern 2
A peeling layer may be provided between the carrier 02 and the carrier 206 to facilitate peeling of the wiring pattern 202.

【００３９】配線パターン２０８，２１０とその間を接
続するインナービア２０９を有する両面配線基板２１１
上の配線パターン２０８に部品２０４を半田２０５によ
る実装し、その後、実装検査および特性検査から選ばれ
る少なくとも一つの検査を完了しておく。配線パターン
２１０の下側には保護フィルム２１２を被覆しておいて
も良い。Double-sided wiring board 211 having wiring patterns 208, 210 and inner vias 209 connecting between them.
The component 204 is mounted on the upper wiring pattern 208 by the solder 205, and then at least one inspection selected from the mounting inspection and the characteristic inspection is completed. The lower side of the wiring pattern 210 may be covered with a protective film 212.

【００４０】次に、図２Ａで作成したスルーホール２０
７に導電性ビアペーストを充填する。導電性ビアペース
トは導電性粉末と樹脂の混合物、たとえば金、銀、銅、
ニッケル等の金属粉やカ−ボン粉と熱硬化性樹脂や光硬
化性樹脂の混合物を用いることができる。銅を用いた場
合は導電性が高く、マイグレショーンも少ないため望ま
しい。また、粉末を銅でコートした導電性粉末を用いて
もよい。樹脂としては、熱硬化性樹脂、例えば、エポキ
シ樹脂、フェノール樹脂、イソシアネート樹脂、ポリフ
ェニレンエーテル等を用いることができる。エポキシ樹
脂は耐熱性が高く特に望ましい。また、光硬化性の樹脂
も用いることができる。ビアペーストの充填には、印刷
や注入による方法を用いることができる。特に印刷の場
合、配線パターンの形成も行うことができる。ビア２０
３を形成することで、配線パターン２０２と２０８間の
接続が可能となる。また、電気絶縁層２０１に内蔵する
電子部品２０４のスペースを形成しておいてもよい。ス
ペースを形成することによってビア２０３が変形するこ
とを抑制できる。Next, the through hole 20 created in FIG. 2A.
7 is filled with a conductive via paste. Conductive via paste is a mixture of conductive powder and resin, such as gold, silver, copper,
A mixture of a metal powder such as nickel or carbon powder and a thermosetting resin or a photocurable resin can be used. When copper is used, it is desirable because it has high conductivity and less migration. Moreover, you may use the electroconductive powder which coat | covered the powder with copper. As the resin, a thermosetting resin such as epoxy resin, phenol resin, isocyanate resin, polyphenylene ether, etc. can be used. Epoxy resins are highly desirable because of their high heat resistance. Further, a photocurable resin can also be used. A method of printing or pouring can be used for filling the via paste. Particularly in the case of printing, it is possible to form a wiring pattern. Via 20
By forming 3, the wiring patterns 202 and 208 can be connected. In addition, a space for the electronic component 204 built in the electric insulating layer 201 may be formed. By forming the space, the via 203 can be suppressed from being deformed.

【００４１】配線パターン２０８，２１０とその間を接
続するインナービア２０９を有する両面配線基板２１１
上の配線パターン２０８に電子部品２０４を実装する方
法としては、半田２０５による半田実装（クリーム半田
の印刷や半田ボール）の他、導電性接着剤、たとえば、
金、銀、銅、銀−パラジウム合金などを熱硬化性樹脂で
混練したものも使用できる。また、実装した電子部品２
０４と両面配線基板２１１の間に、封止樹脂を注入して
もよい。封止樹脂の注入によって、後の工程で電子部品
２０４を電気絶縁層２０１に埋設する際に、隙間ができ
ることを防止することができる。封止樹脂には通常のフ
リップチップボンディングに使用されるアンダーフィル
樹脂を用いることができる。実装後、実装状態をチェッ
クすることで、リペアや不良の原因解析を行うことがで
きるようになる。Double-sided wiring board 211 having wiring patterns 208, 210 and inner vias 209 connecting between them.
As a method of mounting the electronic component 204 on the upper wiring pattern 208, in addition to solder mounting by solder 205 (printing of cream solder or solder balls), a conductive adhesive such as
A material obtained by kneading gold, silver, copper, a silver-palladium alloy or the like with a thermosetting resin can also be used. Also, the mounted electronic component 2
A sealing resin may be injected between 04 and the double-sided wiring board 211. By injecting the sealing resin, it is possible to prevent a gap from being formed when the electronic component 204 is embedded in the electrical insulating layer 201 in a later step. As the sealing resin, an underfill resin used for ordinary flip chip bonding can be used. After mounting, it is possible to analyze the cause of repairs and defects by checking the mounting status.

【００４２】導電性ビアペーストが充填されたビア２０
３を有する電気絶縁層２０１を中央に配置し、上側にキ
ャリヤーフィルム２０６上に形成した配線パターン２０
２を配置し、下側には電子部品２０４を実装した両面基
板２１１を配置し、これらを図２Ｂのように位置あわせ
して積層する。Via 20 filled with conductive via paste
The wiring pattern 20 is formed by disposing the electrically insulating layer 201 having the number 3 in the center and forming the electrically insulating layer 201 on the carrier film 206 on the upper side.
2 is arranged, the double-sided board 211 on which the electronic component 204 is mounted is arranged on the lower side, and these are aligned and laminated as shown in FIG. 2B.

【００４３】図２Ｂの積層後、図２Ｃに示すように、加
圧することによって、電子部品２０４を電気絶縁層２０
１に埋設する事ができる。絶縁性樹脂に熱硬化樹脂を用
いた場合、加圧後、加熱することによって、電気絶縁層
２０１中の熱硬化性樹脂を硬化させ、電子部品２０４が
埋設された板状の電気絶縁層２０１が形成できる。加熱
は、熱硬化性樹が硬化する温度以上の温度で行う。この
工程によって、電気絶縁層２０１と電子部品２０４とが
機械的に強固に接着する。なお、加熱によって熱硬化性
樹脂を硬化させる際に、加熱しながら１００g/mm2〜２k
g/mm2の圧力で加圧することによって、半導体装置の機
械的強度を向上させることができる。また、シート形状
の電気絶縁層を用いずに、粉末やペレット状に加工した
後に、金型に溶融して流すこともできる。また、粉末の
まま流し込んだ後に、溶融成形することもできる。絶縁
性樹脂層を注入する方法としては、トランスファーモー
ルドや射出成形を用いることができる。After the lamination of FIG. 2B, as shown in FIG. 2C, the electronic component 204 is pressed by applying pressure to the electrical insulation layer 20.
Can be buried in 1. When a thermosetting resin is used as the insulating resin, the thermosetting resin in the electric insulating layer 201 is cured by applying pressure and then heating, so that the plate-like electric insulating layer 201 in which the electronic component 204 is embedded is formed. Can be formed. The heating is performed at a temperature equal to or higher than the temperature at which the thermosetting resin hardens. Through this step, the electrical insulating layer 201 and the electronic component 204 are mechanically and firmly bonded together. In addition, when the thermosetting resin is cured by heating, 100 g / mm 2 to 2k while heating.
By applying a pressure of g / mm 2 , the mechanical strength of the semiconductor device can be improved. Alternatively, the sheet-shaped electric insulation layer may be processed into powder or pellets, and then melted and flown into a mold. Alternatively, the powder may be poured as it is and then melt-molded. As a method for injecting the insulating resin layer, transfer molding or injection molding can be used.

【００４４】電気絶縁層２０１の硬化後、キャリア２０
６を剥離し、電子部品２０４を内蔵した電気絶縁層２０
１となり、実施形態１で説明したように、両面基板２１
１を一体化した半導体装置が形成できる。After curing the electrically insulating layer 201, the carrier 20
6 is peeled off, and an electric insulating layer 20 containing an electronic component 204 is built in.
1 and becomes the double-sided substrate 21 as described in the first embodiment.
A semiconductor device in which 1 is integrated can be formed.

【００４５】（実施の形態３）実施形態３では、部品内
蔵モジュールの一実施の形態を説明する。以下、本発明
の実施の形態について図３を参照して説明する。本実施
の形態における部品内蔵モジュールに関しては、半導体
３０６、バンプ３０７、３層配線板３０８に関する点以
外は、上述した実施形態１と同様である。したがって、
実施の形態３で用いられる材料は、特に説明のない限り
実施形態１、２と同様である。図３において、部品内蔵
モジュールは、電気絶縁層３０１と、配線パターン３０
２と、ビア３０３と、電子部品３０４、導電性接着剤３
０５、半導体３０６、バンプ３０７、配線板３０８を有
している。(Embodiment 3) In Embodiment 3, an embodiment of a component built-in module will be described. Hereinafter, an embodiment of the present invention will be described with reference to FIG. The component built-in module according to the present embodiment is the same as that of the first embodiment described above, except for the semiconductor 306, the bump 307, and the three-layer wiring board 308. Therefore,
The materials used in the third embodiment are the same as those in the first and second embodiments unless otherwise specified. In FIG. 3, the component built-in module includes an electrical insulating layer 301 and a wiring pattern 30.
2, via 303, electronic component 304, conductive adhesive 3
05, a semiconductor 306, bumps 307, and a wiring board 308.

【００４６】半導体３０６は電子部品３０４と同様に配
線板３０８に実装されている。半導体３０６を電気絶縁
層３０１に内蔵することで、モジュールの高機能化が図
れる。半導体３０６は、たとえば、トランジスタ、Ｉ
Ｃ、ＬＳＩなどの半導体素子が用いられる。半導体３０
６は、パッケージでも、半導体ベアチップでもよい。ま
た、半導体３０６は封止樹脂を用いて、半導体３０６も
しくは、半導体３０６とバンプ３０７、配線板３０８の
接続部の少なくとも一部を封止しても良い。封止樹脂の
注入によって、半導体３０６を電気絶縁層３０１に埋設
する際に、半導体３０３と配線板３０８との間に隙間が
できることを防止することができる。封止樹脂には通常
のフリップチップボンディングに使用されるアンダーフ
ィル樹脂を用いることができる。配線板３０８と半導体
３０６との接続には、たとえばフリップチップボンディ
ングとして、導電性接着剤、異方性導電フィルム（ＡＣ
Ｆ）、非導電性フィルム（ＮＣＦ）とバンプが用いられ
る。また、チップサイズパッケージ（ＣＳＰ）を用いる
ことで、実装が容易となる。The semiconductor 306 is mounted on the wiring board 308 similarly to the electronic component 304. By incorporating the semiconductor 306 in the electrical insulation layer 301, the functionality of the module can be enhanced. The semiconductor 306 is, for example, a transistor, I
Semiconductor elements such as C and LSI are used. Semiconductor 30
6 may be a package or a semiconductor bare chip. Alternatively, the semiconductor 306 may be sealed with a sealing resin to seal at least a part of the semiconductor 306 or a connecting portion between the semiconductor 306, the bump 307, and the wiring board 308. The injection of the sealing resin can prevent a gap from being formed between the semiconductor 303 and the wiring board 308 when the semiconductor 306 is embedded in the electrical insulating layer 301. As the sealing resin, an underfill resin used for ordinary flip chip bonding can be used. For connecting the wiring board 308 and the semiconductor 306, a conductive adhesive or an anisotropic conductive film (AC
F), non-conductive film (NCF) and bumps are used. Moreover, the use of a chip size package (CSP) facilitates mounting.

【００４７】バンプ３０７は半導体３０６と配線板３０
８とを接続する。たとえば、金や銅、半田等の金属を用
いることができる。バンプ３０７はワイヤーボンディン
グや、メッキ、印刷等により形成できる。The bumps 307 are the semiconductor 306 and the wiring board 30.
8 is connected. For example, a metal such as gold, copper or solder can be used. The bumps 307 can be formed by wire bonding, plating, printing or the like.

【００４８】配線板３０８は、一般的な配線板であるガ
ラスエポキシ基板やセラミック基板からなる、両面基
板、ビルドアップ基板やインナービア接続の多層板等
で、電気絶縁層と配線パターン及びビアから構成されて
いる。電気絶縁層は、絶縁性樹脂やフィラと絶縁性樹脂
との混合物、セラミックの他、ガラスクロス等の補強剤
が入っていてもよい。また、実施の形態１、２と同じ材
料であってもよい。配線パターンやビアに関しても同様
である。電気絶縁層３０１と同じ材料を用いることで熱
膨張率等が同じ値になり、信頼性が向上する。また、電
気絶縁層に埋め込む前に、配線板３０８と半導体３０６
および電子部品３０４の実装状態をチェックしておく。
これにより、製品の歩留まりが高くなり、かつリペアや
不良の原因解析を行うことができる。電子部品３０４と
半導体３０６を両方実装後にチェックした場合、半導体
３０６の動作を確認でき有効である。配線板３０８によ
って、複雑な回路への適応や、半導体の再配線等が容易
になり、複雑な機能のモジュールに適した構造となる。The wiring board 308 is a double-sided board, a build-up board or a multilayer board with inner via connection, which is a general wiring board made of a glass epoxy board or a ceramic board, and is composed of an electric insulating layer, a wiring pattern and vias. Has been done. The electrically insulating layer may contain a reinforcing agent such as glass cloth in addition to the insulating resin, the mixture of the filler and the insulating resin, and the ceramic. Further, the same material as in the first and second embodiments may be used. The same applies to wiring patterns and vias. By using the same material as the electric insulating layer 301, the coefficient of thermal expansion and the like have the same value, and the reliability is improved. In addition, before the wiring board 308 and the semiconductor 306 are embedded in the electrically insulating layer.
Also, the mounting state of the electronic component 304 is checked.
As a result, the yield of products is increased, and the cause analysis of repairs and defects can be performed. When both the electronic component 304 and the semiconductor 306 are checked after mounting, the operation of the semiconductor 306 can be confirmed, which is effective. The wiring board 308 facilitates adaptation to a complicated circuit, rewiring of a semiconductor, and the like, and has a structure suitable for a module having a complicated function.

【００４９】なお、本実施の形態においては、配線板の
配線パターンを３層としたが、層数を限定するものでは
なく、任意の層数を用いることができる。In this embodiment, the wiring pattern of the wiring board has three layers, but the number of layers is not limited and any number of layers can be used.

【００５０】例えばガラス−エポキシ基板を用いた３層
基板の上に部品を搭載し、検査し、その後、電気的絶縁
層に埋め込んだ部品内蔵モジュール（実施の形態３）
と、基板を用いずに部品を単体で電気的絶縁層に埋め込
み、その後に表面に配線パターンを形成したモジュール
との強度を比較すると、基板の種類、コンポジットのセ
ラミックの種類、量、厚み等によっても異なるが、平均
的には、実施の形態３のほうが曲げ強度は約１．３倍以
上高くなる。For example, a component built-in module in which components are mounted on a three-layer substrate using a glass-epoxy substrate, inspected, and then embedded in an electrically insulating layer (third embodiment).
When comparing the strength with a module in which a component is embedded alone in an electrically insulating layer without using a substrate and then a wiring pattern is formed on the surface, it can be determined by the type of substrate, the type of composite ceramic, the amount, the thickness, etc. However, on the average, the bending strength of the third embodiment is about 1.3 times or more higher.

【００５１】（実施の形態４）実施形態４では、部品内
蔵モジュールの一実施形態を説明する。以下、本発明の
実施の形態について図４を参照して説明する。本実施の
形態における部品内蔵モジュールに関しては、両面に３
層配線板４０８を用い、電子部品３０４と半導体３０６
を対向して配置した以外は、上述した実施形態１〜３と
同様である。したがって、本実施の形態において、特に
説明のない物については、実施の形態１〜３と同様と
し、同じ呼称の構成部材及び製造法については特に説明
のない限り同様の機能を持つ。(Embodiment 4) In Embodiment 4, an embodiment of a component built-in module will be described. Hereinafter, an embodiment of the present invention will be described with reference to FIG. Regarding the component built-in module according to the present embodiment, 3
Using the layer wiring board 408, the electronic component 304 and the semiconductor 306
Is the same as the above-described first to third embodiments except that they are arranged to face each other. Therefore, in the present embodiment, components that are not particularly described are the same as those in the first to third embodiments, and constituent members having the same names and manufacturing methods have the same functions unless otherwise described.

【００５２】配線板４０８は、実施の形態３と異なり、
上下両方に配置することで、複雑な回路への適応や、半
導体の再配線等が容易になり、複雑な機能のモジュール
に適した構造となる。また、通常のモジュール作成にお
ける配線板に半導体及び電子部品を実装する工程後に半
導体及び電子部品を内蔵する工程を付加するだけで、高
密度な部品内蔵モジュールを形成できる。The wiring board 408 differs from the third embodiment in that
By arranging them both above and below, adaptation to a complicated circuit, rewiring of a semiconductor, etc. become easy, and a structure suitable for a module having a complicated function is obtained. Further, a high density component built-in module can be formed only by adding a step of embedding the semiconductor and the electronic component after the step of mounting the semiconductor and the electronic component on the wiring board in the usual module production.

【００５３】（実施の形態５）実施形態５では、部品内
蔵モジュールの一実施形態を説明する。以下、本発明の
実施の形態について図５を参照して説明する。本実施の
形態における部品内蔵モジュールに関しては、表層に実
装した電子部品５１０、半導体５０６と、部品内蔵層に
関する点以外は、上述した実施形態１〜４と同様であ
る。したがって、本実施の形態において、特に説明のな
い物については、実施の形態１〜４と同じとし、同じ呼
称の構成部材及び製造法については特に説明のない限り
同様の機能を持つ。(Fifth Embodiment) In the fifth embodiment, an embodiment of a component built-in module will be described. Hereinafter, an embodiment of the present invention will be described with reference to FIG. The component built-in module according to the present embodiment is the same as the first to fourth embodiments described above, except for the electronic component 510 and the semiconductor 506 mounted on the surface layer and the component built-in layer. Therefore, in the present embodiment, the components not particularly described are the same as those in the first to fourth embodiments, and the components having the same names and the manufacturing method have the same functions unless otherwise described.

【００５４】電気絶縁層５０１内の電子部品５０４は、
実施の形態４と同様に通常のモジュール作成における実
装工程で実装されるが、電子部品５０４を実装するマウ
ンタの性能上、どうしても、電子部品と電子部品の間
に、間隔を設ける必要がある。本実施の形態において
は、対向する配線板５０８に部品の実装間隔を考慮し
て、電子部品５０４の位置をずらして配置している。こ
れにより、同一面積に実装できる部品点数が増大すると
共に、内蔵層の厚みを薄くでき、より高密度実装に適し
た構造にすることができる。５０９はＮＣＦである。The electronic component 504 in the electrical insulation layer 501 is
Although it is mounted in the mounting process in the normal module creation as in the fourth embodiment, it is necessary to provide a space between the electronic components in terms of the performance of the mounter mounting the electronic component 504. In this embodiment, the electronic components 504 are arranged on the opposing wiring boards 508 in a shifted manner in consideration of the mounting intervals of the components. As a result, the number of components that can be mounted on the same area is increased, the thickness of the built-in layer can be reduced, and a structure suitable for higher density mounting can be obtained. 509 is an NCF.

【００５５】表層実装された、電子部品５１０、半導体
５０６は、通常のモジュール作成と同じ工程で実装で
き、実装面を増やすことで、より高密度に実装でき、多
機能なモジュールに適した構造となる。The electronic components 510 and the semiconductors 506 mounted on the surface layer can be mounted in the same process as the normal module production, and by increasing the mounting surface, they can be mounted at a higher density and have a structure suitable for a multifunctional module. Become.

【００５６】（実施の形態６）実施形態６では、部品内
蔵モジュールの一実施形態を説明する。以下、本発明の
実施の形態について図６を参照して説明する。本実施の
形態における部品内蔵モジュールに関しては、表層実装
の電子部品６１０，６１２、及び半導体６１１，６１３
と、部品内蔵層に関する点以外は、上述した実施形態１
〜５と同様である。したがって、本実施の形態におい
て、特に説明のない物については、実施の形態１〜５と
同じとし、同じ呼称の構成部材及び製造法については特
に説明のない限り同様の機能を持つ。(Embodiment 6) In Embodiment 6, an embodiment of a component built-in module will be described. Hereinafter, an embodiment of the present invention will be described with reference to FIG. As for the component built-in module according to the present embodiment, surface-layer mounted electronic components 610 and 612 and semiconductors 611 and 613 are provided.
And Embodiment 1 described above except for the point regarding the component built-in layer
The same as ~ 5. Therefore, in the present embodiment, the components that are not particularly described are the same as those in the first to fifth embodiments, and the components having the same names and the manufacturing method have the same functions unless otherwise described.

【００５７】電気絶縁層６０１内の電子部品６０４、半
導体６０６は、実施の形態４、５と同様に通常のモジュ
ール作成における実装工程で実装されるが、半導体６０
６には、フリップチップ実装を行う際に、再配線を行う
ためのスペースが必要なため、どうしても、近接には電
子部品を配置しにくい。本実施の形態においては、対向
する配線板６０８に電子部品６０４を実装することで、
半導体６０６の近接に配置することを可能にしている。
これにより、同一面積に実装できる部品点数を増やすこ
とができ、より高密度実装に適した構造にすることがで
きる。６０９は封止樹脂である。The electronic component 604 and the semiconductor 606 in the electrical insulating layer 601 are mounted in the mounting process in the normal module making as in the fourth and fifth embodiments.
6 requires a space for rewiring when flip-chip mounting is performed, so that it is difficult to place electronic components in the vicinity. In the present embodiment, by mounting the electronic component 604 on the opposing wiring board 608,
It is possible to arrange the semiconductor 606 close to the semiconductor 606.
As a result, the number of components that can be mounted on the same area can be increased, and a structure suitable for higher density mounting can be obtained. Reference numeral 609 is a sealing resin.

【００５８】表層実装された、電子部品６１０、半導体
６０６は、通常のモジュール作成と同じ工程で実装でき
る。両表層面に実装することで、より高密度に実装で
き、多機能なモジュールに適した構造となる。The electronic component 610 and the semiconductor 606, which are surface-layer mounted, can be mounted in the same process as a normal module production. By mounting on both surface layers, higher density mounting can be achieved, and the structure is suitable for multi-functional modules.

【００５９】（実施の形態７）この実施形態７では、図
６に示した部品内蔵モジュールの製造方法の一実施形態
を説明する。以下、本発明の実施の形態について図７Ａ
−Ｃを参照して説明する。実施形態７で用いられる材料
は、特に説明のない物については、上述の実施の形態と
同じとし、同じ呼称の構成部材及び製造法については特
に説明のない限り同様の機能を持つ。図７Ａ−図７Ｃは
部品内蔵モジュールの製造工程の一実施形態を示す断面
図である。図７Ａに示すように、半導体７０６、電子部
品７０４を実装した配線板７０８、ビア７０３及び、空
隙７１０を形成した電気絶縁層７０１を位置あわせして
積層する。配線板７０８は実装後、実装チェックし、リ
ペアをしてもよい。電気絶縁層７０１に形成する空隙７
１０は内蔵する半導体７０６、電子部品７０４の体積と
同じかそれ以下にすることによって、内蔵時に隙間がで
きることを防止できる。(Embodiment 7) In Embodiment 7, an embodiment of a method of manufacturing the component built-in module shown in FIG. 6 will be described. An embodiment of the present invention will be described below with reference to FIG. 7A.
It will be described with reference to -C. The materials used in the seventh embodiment are the same as those in the above-described embodiments unless otherwise specified, and the components having the same names and the manufacturing method have the same functions unless otherwise described. 7A to 7C are cross-sectional views showing an embodiment of the manufacturing process of the component built-in module. As shown in FIG. 7A, the semiconductor 706, the wiring board 708 on which the electronic component 704 is mounted, the via 703, and the electrical insulating layer 701 in which the void 710 is formed are aligned and stacked. After mounting the wiring board 708, mounting check may be performed and repair may be performed. Voids 7 formed in the electric insulation layer 701
By setting the volume of the semiconductor 10 to be equal to or less than the volume of the semiconductor 706 and the electronic component 704, it is possible to prevent the formation of a gap during the incorporation.

【００６０】次に図７Ｂに示すように、積層後、加圧す
ることによって、半導体７０６、電子部品７０４を電気
絶縁層７０１に埋設する事ができる。埋設後、加熱し、
電気絶縁層７０１を硬化させる。また、配線パターン７
０２間をビア７０３で接続する。Next, as shown in FIG. 7B, the semiconductor 706 and the electronic component 704 can be embedded in the electrical insulating layer 701 by applying pressure after stacking. After burying, heat,
The electric insulation layer 701 is cured. Also, the wiring pattern 7
02 are connected by a via 703.

【００６１】電気絶縁層７０１を硬化後、図７Ｃに示す
ように、表層に半導体７１１，７１３及び電子部品７１
４，７１２を実装することによって、部品内蔵モジュー
ルを提供できる。After the electrical insulating layer 701 is cured, as shown in FIG. 7C, the semiconductors 711 and 713 and the electronic component 71 are formed on the surface layer.
A component built-in module can be provided by mounting 4,712.

【００６２】（実施の形態８）実施形態８では、部品内
蔵モジュールの一実施形態を説明する。以下、本発明の
実施の形態について図８を参照して説明する。本実施の
形態における部品内蔵モジュールに関しては、部品内蔵
層に関する点以外は、上述した実施形態１〜７と同様で
ある。したがって、本実施の形態において、特に説明の
ない物については、実施の形態１〜７と同じとし、同じ
呼称の構成部材及び製造法については特に説明のない限
り同様の機能を持つ。(Embodiment 8) In Embodiment 8, an embodiment of a component built-in module will be described. Hereinafter, an embodiment of the present invention will be described with reference to FIG. The component built-in module according to the present embodiment is the same as the above-described first to seventh embodiments except for the component built-in layer. Therefore, in the present embodiment, the components that are not particularly described are the same as those in the first to seventh embodiments, and the components having the same names and the manufacturing method have the same functions unless otherwise described.

【００６３】電気絶縁層８０１内の電子部品８０４と半
導体８０６は、通常のモジュール作成における実装工程
で実装されるが、配線板８０８に両面実装することによ
り、部品内蔵層を増やすことが容易となる。すなわち、
３層配線板８０８の上側には配線パターン８０２を介し
て電子部品８１０、半導体８１１を接続し、３層配線板
８０８の下側にも電子部品を埋め込んだ電気絶縁層を接
続し、その表面に電子部品８１２を接続した。The electronic component 804 and the semiconductor 806 in the electric insulation layer 801 are mounted in a mounting process in a normal module production, but by mounting both surfaces on the wiring board 808, it becomes easy to increase the component built-in layer. . That is,
An electronic component 810 and a semiconductor 811 are connected to the upper side of the three-layer wiring board 808 via a wiring pattern 802, and an electrical insulating layer in which the electronic components are embedded is also connected to the lower side of the three-layer wiring board 808, and the surface thereof is connected. The electronic component 812 was connected.

【００６４】これにより、同一面積に実装できる部品点
数を増やすことができ、より高密度実装に適した構造に
することができる。As a result, the number of components that can be mounted on the same area can be increased, and a structure suitable for higher density mounting can be obtained.

【００６５】（実施の形態９）実施形態９では、部品内
蔵モジュールの一実施形態を説明する。以下、本発明の
実施の形態について図９を参照して説明する。本実施の
形態における部品内蔵モジュールに関しては、半導体の
薄形化に関する点以外は、上述した実施形態１〜８と同
様である。したがって、本実施の形態において、特に説
明のない物については、実施の形態１〜８と同じとし、
同じ呼称の構成部材及び製造法については特に説明のな
い限り同様の機能を持つ。(Embodiment 9) In Embodiment 9, an embodiment of a component built-in module will be described. Hereinafter, an embodiment of the present invention will be described with reference to FIG. The component built-in module according to the present embodiment is the same as the above-described first to eighth embodiments, except for the point of thinning the semiconductor. Therefore, in this embodiment, unless otherwise specified, the same as in the first to eighth embodiments,
Constituent members having the same names and manufacturing methods have similar functions unless otherwise specified.

【００６６】半導体９０６を薄形化することによって、
部品内蔵モジュールの厚みを低減できる。薄形化は半導
体ウエハを研磨後、実装する方法や、半導体９０６を配
線板９０８に実装後、研削／研磨する方法を用いること
ができる。前者の場合、半導体９０６をウエハ単位で加
工できるため生産性に利点がある。後者の場合、薄形化
した半導体９０６を取り扱う必要がなくなるため作業性
が向上する。なお、半導体９０６は表層実装だけではな
く、内部にあってもよい。By thinning the semiconductor 906,
The thickness of the component built-in module can be reduced. For thinning, a method of mounting a semiconductor wafer after polishing, or a method of mounting a semiconductor 906 on a wiring board 908 and then grinding / polishing can be used. In the former case, the semiconductor 906 can be processed in wafer units, which is advantageous in productivity. In the latter case, the workability is improved because it is not necessary to handle the thinned semiconductor 906. It should be noted that the semiconductor 906 may not only be mounted on the surface layer but may be inside.

【００６７】（実施の形態１０）この実施形態１０で
は、部品内蔵モジュールの一実施形態を説明する。以
下、本発明の実施の形態について図１０を参照して説明
する。本実施の形態における部品内蔵モジュールに関し
ては、シールド電極を形成する点以外は、上述した実施
形態１〜９と同様である。したがって、本実施の形態に
おいて、特に説明のない物については、実施の形態１〜
９と同じとし、同じ呼称の構成部材及び製造法について
は特に説明のない限り同様の機能を持つ。１００９はＡ
ＣＦである。(Embodiment 10) In Embodiment 10, an embodiment of a component built-in module will be described. Hereinafter, an embodiment of the present invention will be described with reference to FIG. The component built-in module according to the present embodiment is the same as the above-described first to ninth embodiments except that a shield electrode is formed. Therefore, in the present embodiment, unless otherwise specified, the first to third embodiments
9 has the same function, and the components having the same names and manufacturing methods have the same functions unless otherwise specified. 1009 is A
It is CF.

【００６８】シールド電極１０１０は、配線パターン１
００２と同様の材料・工程で形成することができる。シ
ールド電極１０１０を形成することによって、内蔵した
半導体１００６や電子部品１００４間の電磁波の干渉を
低減させることができる。シールド電極１０１０をグラ
ンド電位にすることにより、モジュールの安定化が図れ
る。なお、シールド電極は１層に限定するものではな
い。The shield electrode 1010 is the wiring pattern 1
It can be formed with the same material and process as 002. By forming the shield electrode 1010, it is possible to reduce the interference of electromagnetic waves between the built-in semiconductor 1006 and the electronic component 1004. The module can be stabilized by setting the shield electrode 1010 to the ground potential. The shield electrode is not limited to one layer.

【００６９】（実施の形態１１）この実施形態１１で
は、部品内蔵モジュールの一実施形態を説明する。以
下、本発明の実施の形態について図１１を参照して説明
する。本実施の形態における部品内蔵モジュールに関し
ては、電磁シールド層１１１０を形成する点以外は、上
述した実施形態１〜１０と同様である。したがって、本
実施の形態において、特に説明のない物については、実
施の形態１〜１０と同じとし、同じ呼称の構成部材及び
製造法については特に説明のない限り同様の機能を持
つ。(Eleventh Embodiment) In the eleventh embodiment, an embodiment of a component built-in module will be described. Hereinafter, an embodiment of the present invention will be described with reference to FIG. The component built-in module according to the present embodiment is the same as the above-described first to tenth embodiments except that the electromagnetic shield layer 1110 is formed. Therefore, in the present embodiment, the components not particularly described are the same as those in the first to tenth embodiments, and the components having the same names and the manufacturing method have the same functions unless otherwise described.

【００７０】電磁シールド層１１１０は、電気絶縁層１
１０１のフィラを変更するだけで内蔵した半導体１１０
６や電子部品１１０４間の電磁波の干渉を低減させるこ
とができる。フィラとしては、透磁率の複素成分が高
く、電波を吸収（熱に変換）する材料を用いることがで
きる。例えば、フェライトの粉末などを用いることがで
きる。電気絶縁層１１０１と同じ工程で、シールド機能
を追加できる。なお、電磁シールド層は１層に限定する
物ではない。The electromagnetic shield layer 1110 is the electrical insulation layer 1
Built-in semiconductor 110 just by changing the filler of 101
It is possible to reduce the interference of electromagnetic waves between the electronic components 6 and the electronic components 1104. As the filler, a material having a high magnetic permeability complex component and absorbing radio waves (converting to heat) can be used. For example, ferrite powder or the like can be used. A shield function can be added in the same process as the electrical insulating layer 1101. The electromagnetic shield layer is not limited to one layer.

【００７１】（実施の形態１２）この実施形態１２で
は、部品内蔵モジュールの一実施形態を説明する。以
下、本発明の実施の形態について図１２を参照して説明
する。本実施の形態における部品内蔵モジュールに関し
ては、電気絶縁層１２０１内の電子部品１２０４ａ、１
２０４ｂに関する点以外は、上述した実施形態１〜１１
と同様である。したがって、本実施の形態において、特
に説明のない物については、実施の形態１〜１１と同じ
とし、同じ呼称の構成部材及び製造法については特に説
明のない限り同様の機能を持つ。(Embodiment 12) In Embodiment 12, an embodiment of a component built-in module will be described. Hereinafter, an embodiment of the present invention will be described with reference to FIG. Regarding the component built-in module according to the present embodiment, the electronic components 1204 a, 1
Embodiments 1 to 11 described above except for the point relating to 204b
Is the same as. Therefore, in the present embodiment, components that are not particularly described are the same as those in the first to eleventh embodiments, and constituent members having the same names and manufacturing methods have the same functions unless otherwise described.

【００７２】電気絶縁層１２０１内の、電子部品１２０
４ａ、１２０４ｂは、実施の形態４と同様に通常のモジ
ュール作成における実装工程で実装されるが、例えば、
コンデンサの容量等により、電子部品のサイズが均一で
ないことが多い。本実施の形態においては、電子部品１
２０４ａ，１２０４ｂの高さの違いを有効に利用して、
実装密度を向上している。図１２の様に高さの低い電子
部品１２０４ａの部品を対向して実装し、通常では無駄
になる電子部品１２０４ａの上部スペースを有効に利用
し、より高密度実装に適した構造にすることができる。Electronic component 120 in electrical insulation layer 1201
4a and 1204b are mounted in the mounting process in the normal module creation as in the fourth embodiment.
In many cases, the size of electronic components is not uniform due to the capacity of capacitors. In the present embodiment, the electronic component 1
Effectively utilizing the difference in height between 204a and 1204b,
The packaging density is improved. As shown in FIG. 12, it is possible to mount the electronic parts 1204a having a low height so as to face each other, effectively use the upper space of the electronic parts 1204a that would normally be wasted, and make a structure suitable for higher density mounting. it can.

【００７３】表層実装された、電子部品１２０４、半導
体１２０６は、通常のモジュール作成と同じ工程で実装
でき、実装面を増やすことで、より高密度に実装でき、
多機能なモジュールに適した構造となる。The electronic components 1204 and semiconductors 1206 mounted on the surface layer can be mounted in the same process as in the normal module production, and can be mounted at a higher density by increasing the mounting surface.
The structure is suitable for multi-functional modules.

【００７４】[0074]

【実施例】以下実施例を用いて本発明をさらに具体的に
説明する。EXAMPLES The present invention will be described in more detail with reference to the following examples.

【００７５】（実施例１）本実施例においては、電気絶
縁層を以下の工程で作製した。熱硬化性の液状エポキシ
樹脂と、ＳｉＯ2をフィラとし、フィラを質量比７０％
の割合で秤量し、攪拌混合機によって、混合ペーストを
作製した。作製した混合ペーストをポリエチレンテレフ
タレート（ＰＥＴ）の離型フィルム（厚み：７５μｍ）
上にドクターブレード法によって、７００μｍ厚のシー
ト形状に加工した。シート状に加工した後、１０５℃の
乾燥工程を経て未硬化状態の電気絶縁層とした。液状エ
ポキシ樹脂とフィラの質量比は、シートの形状を保持で
きる９６％（フィラの質量比）以下で選択できる。シー
トの厚みは、乾燥工程が行いやすい２００μｍ以下が望
ましいが、内蔵する部品の高さに応じて、厚いシートを
形成するか、シート形成後、積層することによって所望
の厚さを得ることができる。Example 1 In this example, an electrical insulating layer was produced by the following steps. Thermosetting liquid epoxy resin and SiO 2 are used as filler, and the filler is 70% by mass.
Was weighed and the mixed paste was prepared with a stirring mixer. The prepared mixed paste is a release film of polyethylene terephthalate (PET) (thickness: 75 μm)
The sheet was processed into a sheet having a thickness of 700 μm by the doctor blade method. After being processed into a sheet, a uncured electrical insulating layer was obtained through a drying process at 105 ° C. The mass ratio of the liquid epoxy resin and the filler can be selected to be 96% (mass ratio of the filler) or less that can maintain the shape of the sheet. The thickness of the sheet is preferably 200 μm or less, which facilitates the drying process, but a desired thickness can be obtained by forming a thick sheet or stacking the sheets after forming them, depending on the height of the components to be incorporated. .

【００７６】次いで、インナービアに対応する位置に、
炭酸ガスレーザーを用いてスルーホール（直径φ１５０
μｍ）を形成した。スルーホール形成後、銅紛（粒子
径：７μｍ未満）と熱硬化性エポキシ樹脂の混合物であ
るビアペーストを印刷充填した。印刷充填時にはスキー
ジを用い、ＰＥＴフィルムをマスクとした。スルーホー
ル径は、小さいほうが高密度実装に適しており、６００
μｍ以下のサイズを実用的に用いることができる。Next, at the position corresponding to the inner via,
Through hole (diameter φ150 using carbon dioxide laser)
μm) was formed. After the through holes were formed, a via paste, which was a mixture of copper powder (particle diameter: less than 7 μm) and a thermosetting epoxy resin, was printed and filled. A squeegee was used for printing and filling, and a PET film was used as a mask. The smaller the through hole diameter, the more suitable for high-density mounting.
A size of μm or less can be practically used.

【００７７】上記工程と平行して、ＰＥＴキャリアフィ
ルム（厚み：７５μｍ）に接着剤により貼り付けた１５
μｍ厚の銅箔（片面粗化）に、フォトレジストフィルム
をラミネータにより貼り付け、紫外線露光、現像、塩化
第２鉄を用いたエッチングにより、配線パターンを形成
した。配線設計ルールとして、最小Ｌ/Ｓ（ライン／ス
ペース）を１００／１００（μｍ）とした。Ｌ／Ｓも小
さいほうが高密度実装に適しており、半導体ベアチップ
を実装する場合２００／２００μｍ以下が妥当である。In parallel with the above steps, a PET carrier film (thickness: 75 μm) was attached with an adhesive 15
A photoresist film was attached to a copper foil (one surface roughened) having a thickness of μm by a laminator, and a wiring pattern was formed by ultraviolet exposure, development, and etching using ferric chloride. As a wiring design rule, the minimum L / S (line / space) was set to 100/100 (μm). A smaller L / S is suitable for high-density mounting, and when mounting a semiconductor bare chip, 200/200 μm or less is appropriate.

【００７８】配線パターンに電子部品及び／又は半導体
を実装した。電子部品の実装には、導電性接着剤を用い
た。導電性接着剤をスクリーン版（メッシュ：＃４００
／インチ）で配線パターン上に塗布し、１００５サイズ
の電子部品を配置後、乾燥機（温度：１５０℃）で硬化
した。電子部品としては、構成するモジュールに応じ
て、ＬＣＲ等のチップ部品と、サーミスタやダイオード
を用いた。内蔵する電子部品のサイズも小さいほうが高
密度実装に適しており、１．６ｍｍ以下（３２１６サイ
ズ）が望ましい。半導体の実装は、パッケージの場合、
電子部品と同様に導電性接着剤を用いた。また、ベアチ
ップの場合、金バンプを形成し、フリップチップ実装し
た。また、配線板にも同様に電子部品及び／又は半導体
を実装した。配線板の場合、電子部品の実装には、はん
だ実装を用いた。Electronic parts and / or semiconductors were mounted on the wiring pattern. A conductive adhesive was used for mounting the electronic components. Conductive adhesive screen plate (mesh: # 400
/ Inch) on the wiring pattern, and after arranging a 1005 size electronic component, it was cured by a dryer (temperature: 150 ° C.). As the electronic components, chip components such as LCR, thermistors and diodes were used according to the modules to be configured. The smaller the size of the built-in electronic component is, the more suitable it is for high-density mounting, and 1.6 mm or less (3216 size) is desirable. When mounting a semiconductor,
A conductive adhesive was used as in the case of electronic parts. In the case of a bare chip, gold bumps were formed and flip chip mounting was performed. Similarly, electronic components and / or semiconductors were mounted on the wiring board. In the case of a wiring board, solder mounting was used for mounting electronic components.

【００７９】実装した電子部品は、外観検査を行い、実
装ミス（部品外れや部品立ち）が生じた箇所はリペアし
た。実装した半導体も電気的接続チェックにより実装状
態を確認した。その後、回路ブロックの機能検査を行
い、半導体自体の特性も確認した。特性不良の箇所は部
品の交換を行った。The mounted electronic parts were subjected to a visual inspection, and the places where mounting mistakes (part removal or part standing) occurred were repaired. The mounted state of the mounted semiconductor was also confirmed by an electrical connection check. After that, the functional inspection of the circuit block was performed, and the characteristics of the semiconductor itself were also confirmed. Parts with defective characteristics were replaced.

【００８０】上記工程で作製した、電気絶縁層と電子部
品及び／又は半導体を実装した配線パターンを認識マー
クを基準に位置合わせし、積層し、加圧（５ＭＰａ）し
た。加圧によって、電気絶縁層と電子部品及び／又は半
導体を電気絶縁層に埋設した。埋設後、同じ圧力で加圧
しながら、温度：２００℃、時間：２hrs加熱し、電気
絶縁層を硬化した。電気絶縁層の硬化と同時に配線パタ
ーンも転写された。The wiring pattern on which the electric insulating layer and the electronic component and / or the semiconductor were manufactured in the above process was aligned with the recognition mark as a reference, laminated and pressed (5 MPa). The electric insulating layer and the electronic component and / or the semiconductor were embedded in the electric insulating layer by applying pressure. After the embedding, the electrical insulating layer was cured by heating at a temperature of 200 ° C. for a time of 2 hrs while applying the same pressure. The wiring pattern was transferred at the same time when the electric insulating layer was cured.

【００８１】電気絶縁層の硬化後、ＰＥＴキャリアを剥
離し部品内蔵モジュールを形成した。この部品内蔵モジ
ュールは、表層に、電子部品及び／又は半導体を実装す
るスペースを有し、内部にも電子部品及び／又は半導体
を配置しており、本実施例の部品内蔵モジュールと通常
の２次元（表面）実装品とを同じ面積で比較すると、本
実施例のモジュールは約２倍の部品を実装できる。逆
に、通常の２次元（表面）実装品と同一数の部品を実装
する場合は、本実施例のモジュールは約半分のサイズで
すむ。After curing the electric insulation layer, the PET carrier was peeled off to form a component built-in module. This component built-in module has a space for mounting an electronic component and / or a semiconductor on the surface layer, and the electronic component and / or the semiconductor are also arranged inside. Comparing with the (surface) mounted product in the same area, the module of this embodiment can mount about twice as many parts. On the contrary, when mounting the same number of components as a normal two-dimensional (surface) mounting product, the module of this embodiment requires about half the size.

【００８２】（実施例２）本実施例においては、図１２
に示すような構造で試料を作製した。電子部品を内蔵し
た電気絶縁層の上下に配線板を配置した構造であり、ビ
アで上下の配線板間を接続している。電子部品は０６０
３サイズのチップ部品を用いた。電気絶縁層はＳｉＯ2
をフィラとし、質量比を調整することで熱膨張係数を変
化させた試料を作製した。電気絶縁層の厚みは４００μ
ｍである。配線板はガラスエポキシ基板（Ａ基板）と、
電気絶縁層と同じ材料で形成した配線板（Ｂ基板）を用
いた。配線板の厚みは４００μｍである。ビアは銅粉
と、樹脂の混合物である。ビアと電気絶縁層（電気絶縁
層のみ）、構造体の電気絶縁層の熱膨張率を表１に示
す。(Embodiment 2) In this embodiment, FIG.
A sample was prepared with a structure as shown in. This is a structure in which wiring boards are arranged above and below an electrically insulating layer containing electronic components, and vias connect the upper and lower wiring boards. Electronic parts are 060
Three size chip parts were used. The electrical insulation layer is SiO 2
Was used as the filler, and the mass ratio was adjusted to prepare samples with different thermal expansion coefficients. The thickness of the electrical insulation layer is 400μ
m. The wiring board is a glass epoxy board (A board),
A wiring board (B substrate) formed of the same material as the electrical insulating layer was used. The thickness of the wiring board is 400 μm. The via is a mixture of copper powder and resin. Table 1 shows the coefficient of thermal expansion of the via, the electric insulating layer (only the electric insulating layer), and the electric insulating layer of the structure.

【００８３】[0083]

【表１】 配線板としてガラスエポキシ基板（Ａ基板）と電気絶縁
層と同じ材料で形成した基板（Ｂ基板）とでは構造体と
なった時の熱膨張率が異なっている。電気絶縁層及び、
Ｂ基板は補強材が入っていないため、ＸＹＺ方向に等方
的な熱膨張率を示すが、ガラスエポキシ基板はガラスク
ロスが入っているためＸＹ方向とＺ方向の熱膨張率がか
なり異なる。前記Ａ基板の熱膨張率はＸＹ方向が１０ｐ
ｐｍ、Ｚ方向が１５０ｐｐｍの材料であった。構造体と
なった場合、電気絶縁層は配線板と固着しているためＸ
Ｙ方向はヤング率の高い配線板（Ａ基板）に強制的に固
定されてしまう。そのため、ＸＹ方向にのびることがで
きず、Ｚ方向の熱膨張率が増加してしまう。同じ材料で
あるＢ基板を配線板に用いた場合は当然、熱膨張率は変
化していない。作製したサンプルを熱サイクル試験（−
５０℃〜２７０℃）にかけた時のビアの抵抗値（オープ
ン数）を調べた（表２）。[Table 1] The glass epoxy substrate (A substrate) as a wiring board and the substrate (B substrate) formed of the same material as the electrical insulating layer have different thermal expansion coefficients when they are structured. Electrical insulation layer and
Since the B substrate does not contain a reinforcing material, it shows an isotropic thermal expansion coefficient in the XYZ directions, but the glass epoxy substrate contains glass cloth, and therefore the thermal expansion coefficients in the XY direction and the Z direction are considerably different. The thermal expansion coefficient of the A substrate is 10 p in the XY directions.
The material had a pm and Z direction of 150 ppm. When it becomes a structure, the electric insulation layer is fixed to the wiring board, so X
The Y direction is forcibly fixed to the wiring board (A substrate) having a high Young's modulus. Therefore, it cannot extend in the XY directions, and the coefficient of thermal expansion in the Z direction increases. When the B substrate made of the same material is used for the wiring board, the coefficient of thermal expansion does not change. Thermal cycle test (-
The resistance value (open number) of the via when subjected to 50 ° C. to 270 ° C.) was examined (Table 2).

【００８４】[0084]

【表２】 実験の結果、試料Ｎｏ．９のサンプルに多くのオープン
が発生した。これは、ビアの熱膨張率と電気絶縁層の熱
膨張率の差によるものと考えられる。電気絶縁層が同じ
材料であっても、構造体に成ったときの熱膨張率の差が
ビアの信頼性に影響を与えており、熱膨張率の比を１０
倍以内にすることで信頼性の高い部品内蔵モジュールを
提供できる。[Table 2] As a result of the experiment, the sample No. Numerous opens occurred in 9 samples. It is considered that this is due to the difference between the coefficient of thermal expansion of the via and the coefficient of thermal expansion of the electrical insulating layer. Even if the electrical insulating layers are made of the same material, the difference in the coefficient of thermal expansion when the structure is formed affects the reliability of the via, and the coefficient of thermal expansion is 10%.
By setting the ratio within twice, it is possible to provide a highly reliable module with built-in components.

【００８５】[0085]

【発明の効果】以上説明したとおり、本発明によれば、
電気絶縁層と、前記電気絶縁層の両主平面に形成した配
線パターンと、前記配線パターン間を接続するビア及
び、前記配線パターンに実装した電子部品及び／又は半
導体を前記電気絶縁層の内部に配置した部品内蔵モジュ
ールとすることにより、電子部品及び／又は半導体を電
気絶縁層に内蔵し、厚みが薄くて高密度に実装した部品
内蔵モジュールを提供できる。As described above, according to the present invention,
An electrical insulating layer, a wiring pattern formed on both main planes of the electrical insulating layer, a via connecting the wiring patterns, and an electronic component and / or a semiconductor mounted on the wiring pattern are provided inside the electrical insulating layer. By using the arranged component built-in module, it is possible to provide a component built-in module in which electronic components and / or semiconductors are built in the electrical insulating layer and which is thin and densely mounted.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施形態１における部品内蔵モジュー
ルの断面図。FIG. 1 is a sectional view of a component built-in module according to a first embodiment of the present invention.

【図２】Ａ〜Ｅは本発明実施形態２における部品内蔵モ
ジュールの製造工程の断面図。2A to 2E are cross-sectional views of the manufacturing process of the component built-in module according to the second embodiment of the present invention.

【図３】本発明の実施形態３における部品内蔵モジュー
ルの断面図。FIG. 3 is a sectional view of a component built-in module according to a third embodiment of the present invention.

【図４】本発明の実施形態４における部品内蔵モジュー
ルの断面図。FIG. 4 is a sectional view of a component built-in module according to a fourth embodiment of the present invention.

【図５】本発明の実施形態５における部品内蔵モジュー
ルの断面図。FIG. 5 is a sectional view of a component built-in module according to a fifth embodiment of the present invention.

【図６】本発明の実施形態６における部品内蔵モジュー
ルの製造工程の断面図。FIG. 6 is a sectional view of a manufacturing process of a component built-in module according to a sixth embodiment of the present invention.

【図７】Ａ〜Ｃは本発明の実施形態７における部品内蔵
モジュールの断面図。7A to 7C are cross-sectional views of a component built-in module according to a seventh embodiment of the present invention.

【図８】本発明の実施形態８における部品内蔵モジュー
ルの断面図。FIG. 8 is a sectional view of a component built-in module according to an eighth embodiment of the present invention.

【図９】本発明の実施形態９における部品内蔵モジュー
ルの断面図。FIG. 9 is a sectional view of a component built-in module according to a ninth embodiment of the present invention.

【図１０】本発明の実施形態１０における部品内蔵モジ
ュールの断面図。FIG. 10 is a sectional view of a component built-in module according to a tenth embodiment of the present invention.

【図１１】本発明の実施形態１１における部品内蔵モジ
ュールの製造工程の断面図。FIG. 11 is a sectional view of the manufacturing process of the component built-in module according to the eleventh embodiment of the present invention.

【図１２】本発明の実施形態１２における部品内蔵モジ
ュールの製造工程断面図。FIG. 12 is a sectional view of a manufacturing process of the component built-in module according to the twelfth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

101,201,301 電気絶縁層 102,202,302 配線パターン 103,203,303 ビア 104,204,304,612 電子部品 105,205,305 半田 106,108 配線パターン 107 インナービア 109,211 両面基板 206 キャリア 207 ビアホール 306,611,613 半導体 307 バンプ 308,408,508,608,7088,808,908 配線基板 509 ＮＣＦ 609 封止樹脂 710 空隙 1009 ＡＣＦ 1010 シールド電極 1110 電磁シールド層 101,201,301 Electrical insulation layer 102,202,302 Wiring pattern 103,203,303 via 104,204,304,612 Electronic components 105,205,305 solder 106,108 Wiring pattern 107 Inner via 109,211 double-sided board 206 career 207 beer hall 306,611,613 Semiconductor 307 bump 308,408,508,608,7088,808,908 Wiring board 509 NCF 609 Sealing resin 710 void 1009 ACF 1010 Shield electrode 1110 Electromagnetic shield layer

フロントページの続き (72)発明者 小松 慎五 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 山本 義之 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 中谷 誠一 大阪府門真市大字門真1006番地 松下電器 産業株式会社内Continued front page    (72) Inventor Shingo Komatsu             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Yoshiyuki Yamamoto             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Seiichi Nakatani             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd.

Claims (18)

【特許請求の範囲】[Claims] 【請求項１】 電気絶縁層と、 前記電気絶縁層の両表面に一体化された配線と、前記配
線間を接続するビアを含み、 前記電気絶縁層の内部に、電子部品及び半導体から選ば
れる少なくとも一つの部品が埋め込まれた部品内蔵モジ
ュールであって、 前記配線の少なくとも一方は、配線基板の表面に形成さ
れた配線であり、 前記電気絶縁層の内部に埋め込まれた部品は、埋め込ま
れる前に前記配線基板上に搭載され一体化されているこ
とを特徴とする部品内蔵モジュール。1. An electric insulating layer, wirings integrated on both surfaces of the electric insulating layer, and vias connecting the wirings, and the inside of the electric insulating layer is selected from electronic components and semiconductors. A component built-in module in which at least one component is embedded, wherein at least one of the wirings is a wiring formed on a surface of a wiring board, and the component embedded inside the electrical insulating layer is before being embedded. A module with a built-in component, which is mounted on and integrated with the wiring board. 【請求項２】 さらに、前記配線基板の外側主平面に電
子部品及び半導体から選ばれる少なくとも一つの部品を
実装した請求項１に記載の部品内蔵モジュール。2. The component built-in module according to claim 1, further comprising at least one component selected from an electronic component and a semiconductor mounted on an outer main plane of the wiring board. 【請求項３】 前記配線基板が両面配線基板および多層
配線板から選ばれる少なくとも一つの基板である請求項
１に記載の部品内蔵モジュール。3. The component built-in module according to claim 1, wherein the wiring board is at least one board selected from a double-sided wiring board and a multilayer wiring board. 【請求項４】 前記部品を前記電気絶縁層内部に埋め込
む前に実装検査および特性検査から選ばれる少なくとも
一つの検査を完了しておく請求項１に記載の部品内蔵モ
ジュール。4. The component built-in module according to claim 1, wherein at least one inspection selected from a mounting inspection and a characteristic inspection is completed before embedding the component inside the electric insulating layer. 【請求項５】 前記部品を前記電気絶縁層の断面方向に
ずらして配置した請求項１に記載の部品内蔵モジュー
ル。5. The component built-in module according to claim 1, wherein the components are arranged so as to be displaced in a cross-sectional direction of the electric insulating layer. 【請求項６】 前記電気絶縁層内部に配置し、前記電気
絶縁層の両主平面の配線基板に実装した部品の少なくと
も一つの間にシールド層を挿入した請求項１に記載の部
品内蔵モジュール。6. The component built-in module according to claim 1, wherein a shield layer is inserted inside at least one of the components mounted inside the electrical insulation layer and mounted on the wiring boards on both main planes of the electrical insulation layer. 【請求項７】 前記シールド層が、金属箔配線パターン
であるか、又は電磁シールド材である請求項６に記載の
部品内蔵モジュール。7. The component built-in module according to claim 6, wherein the shield layer is a metal foil wiring pattern or an electromagnetic shield material. 【請求項８】 前記電子部品がディスクリート部品であ
る請求項１に記載の部品内蔵モジュール。8. The component built-in module according to claim 1, wherein the electronic component is a discrete component. 【請求項９】 前記半導体が半導体ベアチップである請
求項１に記載の部品内蔵モジュール。9. The component built-in module according to claim 1, wherein the semiconductor is a semiconductor bare chip. 【請求項１０】 前記半導体ベアチップが前記配線にフ
リップチップボンディング接続されている請求項９に記
載の部品内蔵モジュール。10. The component built-in module according to claim 9, wherein the semiconductor bare chip is flip-chip bonded to the wiring. 【請求項１１】 前記半導体ベアチップが研削又は研磨
加工されている請求項９に記載の部品内蔵モジュール。11. The component built-in module according to claim 9, wherein the semiconductor bare chip is ground or polished. 【請求項１２】 前記電気絶縁層内部に前記部品を対向
して配置させた請求項１に記載の部品内蔵モジュール。12. The component built-in module according to claim 1, wherein the components are arranged facing each other inside the electrical insulating layer. 【請求項１３】 前記電気絶縁層の厚み方向の熱膨張係
数が、ビアの熱膨張係数の１０倍以下である請求項１に
記載の部品内蔵モジュール。13. The component built-in module according to claim 1, wherein the thermal expansion coefficient of the electrical insulating layer in the thickness direction is 10 times or less the thermal expansion coefficient of the via. 【請求項１４】 前記電気絶縁層は、樹脂とフィラーを
含み、フィラー含量が５０質量％以上９５質量％以下で
ある請求項１に記載の部品内蔵モジュール。14. The component built-in module according to claim 1, wherein the electrical insulation layer contains a resin and a filler, and the filler content is 50% by mass or more and 95% by mass or less. 【請求項１５】 請求項１〜１４のいずれかに記載の部
品内蔵モジュールの製造方法であって、 電気絶縁層の両表面に一体化された配線のうち、少なく
とも一方の側は配線基板の表面に形成された配線で構成
し、 前記配線基板に半導体及び電子部品から選ばれる少なく
とも一つの部品を実装し、 半硬化状態の熱硬化性樹脂からなる電気絶縁層の厚さ方
向にビアを形成し、 前記配線基板を外側にして前記部品を前記電気絶縁層に
埋め込み、 前記電気絶縁層を硬化することを含む部品内蔵モジュー
ルの製造方法。15. The method of manufacturing a component built-in module according to claim 1, wherein at least one side of the wirings integrated on both surfaces of the electric insulating layer is the surface of the wiring board. And at least one component selected from a semiconductor and an electronic component is mounted on the wiring board, and a via is formed in the thickness direction of the electrically insulating layer made of a thermosetting resin in a semi-cured state. A method for manufacturing a component built-in module, comprising: embedding the component in the electrical insulation layer with the wiring board facing outside, and curing the electrical insulation layer. 【請求項１６】 前記半導体を実装前に半導体ウエハで
研削又は研磨する請求項１５に記載の部品内蔵モジュー
ルの製造方法。16. The method for manufacturing a component built-in module according to claim 15, wherein the semiconductor is ground or polished with a semiconductor wafer before mounting. 【請求項１７】 前記半導体を実装後に前記半導体を研
削又は研磨する請求項１５に記載の部品内蔵モジュール
の製造方法。17. The method of manufacturing a component built-in module according to claim 15, wherein after the semiconductor is mounted, the semiconductor is ground or polished. 【請求項１８】 前記前記半導体及び電子部品から選ば
れる少なくとも一つを前記電気絶縁層に埋設するととも
に、前記電気絶縁層の硬化を同時に行う請求項１５に記
載の部品内蔵モジュールの製造方法。18. The method of manufacturing a component built-in module according to claim 15, wherein at least one selected from the semiconductor and the electronic component is embedded in the electrical insulating layer, and the electrical insulating layer is simultaneously cured.
JP2002301043A 2001-10-18 2002-10-15 Module with built-in component and method of manufacturing the same Pending JP2003197849A (en)

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