JP2007335584A - Composite substrate - Google Patents

Composite substrate Download PDF

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JP2007335584A
JP2007335584A JP2006164842A JP2006164842A JP2007335584A JP 2007335584 A JP2007335584 A JP 2007335584A JP 2006164842 A JP2006164842 A JP 2006164842A JP 2006164842 A JP2006164842 A JP 2006164842A JP 2007335584 A JP2007335584 A JP 2007335584A
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resin layer
substrate
layer
thermal expansion
expansion coefficient
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JP5165859B2 (en
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Ichiei Higo
一詠 肥後
Koichiro Shimogami
晃一郎 下上
Yukihiro Kimura
幸広 木村
Shigeru Taga
茂 多賀
Satoshi Hirano
訓 平野
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable composite substrate having no interlayer peeling, no bonding failure between a substrate and a resin layer as an intermediate layer and no crack etc., and no dimensional deviation in a via hole conductor formed on the resin layer as the intermediate layer and in the shape or positional accuracy of a thermal via. <P>SOLUTION: The composite substrate 1 is provided with a multilayer resin layer 4 consisting of a first resin layer 7 including a thermoplastic resin, and a second resin layer 8 provided on at least one surface of the first resin layer 7 and including a thermosetting resin; a first substrate or electric element 2 provided on one main surface of the multilayer resin layer 4; and a second substrate or electric element 3 having a thermal expansion coefficient different from that of the first substrate or electric element 2, and provided on the other main surface of the multilayer resin layer 4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、熱膨張係数が互いに異なる複数の基板又は電気素子を積層してなる複合基板に関する。   The present invention relates to a composite substrate formed by laminating a plurality of substrates or electrical elements having different thermal expansion coefficients.

近年、パーソナルコンピュター、デジタル家電などの電気製品分野などにおいて、製品の小型化、高機能化、高付加価値化が益々進んでいる。それに伴い異種材料の基板同士、または異種材料の電気素子同士を接合してなる複合基板が実用化されている。しかし、このような複合基板は、熱膨張係数が互いに異なるため、異種材料界面に応力が集中して層間剥離、反り、クラック等が発生し易い。   In recent years, in the field of electrical products such as personal computers and digital home appliances, miniaturization, high functionality, and high added value of products have been increasing. Accordingly, composite substrates formed by bonding substrates of different materials or electrical elements of different materials have been put into practical use. However, since such composite substrates have different thermal expansion coefficients, stress is concentrated on the interface between different materials, and delamination, warpage, cracks, and the like are likely to occur.

そこで、異種材料層間に合成樹脂で構成された中間層を挟み、熱プレスで積層一体化した構造が提案されている(例えば、特許文献1参照)。   Thus, a structure in which an intermediate layer made of a synthetic resin is sandwiched between different material layers and laminated and integrated by hot pressing has been proposed (for example, see Patent Document 1).

しかしながら、中間層を構成する合成樹脂として、例えば熱硬化性樹脂を単独で用いた場合や熱可塑性樹脂を単独で用いた場合には、中間層に形成された電気導通用のビアホール導体や放熱用のサーマルビアの形状及び位置精度保持性と、基板、電気素子等の反り及びパターン凹凸への追随性を両立させることは難しく、その結果、位置ズレ、ビア形状崩れ等による導通不良、反り及びパターン凹凸追随性不足による接着不良等を招きやすいといった問題がある。
特開平9−55336号公報
However, as a synthetic resin constituting the intermediate layer, for example, when a thermosetting resin is used alone or when a thermoplastic resin is used alone, a via-hole conductor for electrical conduction formed in the intermediate layer or a heat-dissipating material is used. It is difficult to achieve both the shape and position accuracy retention of thermal vias, the warpage of substrates, electrical elements, etc., and the ability to follow pattern irregularities. As a result, poor conduction, warpage, and pattern due to misalignment, via shape deformation, etc. There is a problem in that adhesion failure or the like due to lack of unevenness is easily caused.
JP-A-9-55336

本発明は、上記問題に鑑みてなされたもので、その目的は、基板と中間層である樹脂層との間で、層間剥離、接着不良、クラック等がなく、更に、中間層である樹脂層に形成されたビアホール導体やサーマルビアの形状や位置精度に寸法ズレの少ない、信頼性に優れた複合基板を提供することにある。   The present invention has been made in view of the above problems, and the object thereof is that there is no delamination, poor adhesion, cracks, etc. between the substrate and the resin layer as the intermediate layer, and the resin layer as the intermediate layer. It is an object of the present invention to provide a composite substrate having excellent reliability with little dimensional deviation in the shape and positional accuracy of via-hole conductors and thermal vias formed on the substrate.

本発明の複合基板は、熱可塑性樹脂を含む第1の樹脂層とこの第1の樹脂層の少なくとも片面に設けられた熱硬化性樹脂を含む第2の樹脂層からなる多層樹脂層と、前記多層樹脂層の一方の主面に設けられた第1の基板又は電気素子と、前記第1の基板又は電気素子とは異なる熱膨張係数を有し、前記多層樹脂層の他方の主面に設けられた第2の基板又は電気素子とを具備することを特徴とする。   The composite substrate of the present invention comprises a multilayer resin layer comprising a first resin layer containing a thermoplastic resin and a second resin layer containing a thermosetting resin provided on at least one surface of the first resin layer, The first substrate or electric element provided on one main surface of the multilayer resin layer has a different thermal expansion coefficient from that of the first substrate or electric element, and is provided on the other main surface of the multilayer resin layer. And a second substrate or an electric element.

上記構成の場合、上記多層樹脂層が、第1の基板又は電気素子と第2の基板又は電気素子を接着する役目を果たしており、その上記多層樹脂層は、流動性が悪いが、ビア形状及び位置精度を保持できる熱可塑性樹脂を含むコアの役目をする第1の樹脂層と、この第1の樹脂層の少なくとも片面に設けられた流動性が良く接合物のパターン凹凸、反りに追従することができる熱硬化性樹脂を含むコート層である第2の樹脂層からなっている。   In the case of the above configuration, the multilayer resin layer serves to bond the first substrate or electrical element and the second substrate or electrical element, and the multilayer resin layer has poor fluidity, The first resin layer serving as a core containing a thermoplastic resin capable of maintaining positional accuracy, and the fluidity provided on at least one surface of the first resin layer is good, and follows the pattern irregularities and warpage of the joint. It consists of the 2nd resin layer which is a coat layer containing the thermosetting resin which can do.

このため、基板又は電気素子と直接接着する樹脂層は、コート層である流れ性及び接着性の良い熱硬化性樹脂を含む樹脂層なので、第1及び第2の基板又は電気素子の回路パターンの凹凸、反り等に対して優れた追随性を発揮し、層間剥離、接着不良等を抑制することができる。さらに、多層樹脂層のコア層が熱可塑性樹脂を含む樹脂層のため、電気導通用のビアホール導体や放熱用のサーマルビアを形成した場合に所望のビア形状及び位置精度を保持することができる。   For this reason, the resin layer that directly adheres to the substrate or the electric element is a resin layer containing a thermosetting resin having good flowability and adhesiveness, which is a coating layer. Therefore, the circuit pattern of the first and second substrates or electric elements is It exhibits excellent followability with respect to unevenness, warpage, etc., and can suppress delamination, adhesion failure, and the like. Furthermore, since the core layer of the multilayer resin layer is a resin layer containing a thermoplastic resin, a desired via shape and positional accuracy can be maintained when a via hole conductor for electrical conduction or a thermal via for heat dissipation is formed.

また、第1の基板又は電気素子、又は第2の基板又は電気素子のどちらか一方が、パターン凹凸が比較的少ない場合は、基板又は電気素子と直接接着する樹脂層は、コア層である熱可塑性樹脂を含む樹脂層でもよい。言い換えれば、コア層である熱可塑性樹脂を含む樹脂層に、コート層である熱硬化性樹脂を含む樹脂層が片面に設けられた構成であってもよい。上記の構成により、信頼性に優れた複合基板を提供することができる。   In addition, when either the first substrate or the electric element or the second substrate or the electric element has relatively few pattern irregularities, the resin layer directly bonded to the substrate or the electric element is a heat which is a core layer. A resin layer containing a plastic resin may be used. In other words, the resin layer containing the thermoplastic resin as the core layer may be provided with the resin layer containing the thermosetting resin as the coating layer on one side. With the above configuration, a composite substrate having excellent reliability can be provided.

以下、本発明を実施するための形態について、図面を参照して説明する。なお、以下では本発明の実施形態を図面に基づいて述べるが、それらの図面は図解のために提供されるものであり、本発明はそれらの図面に限定されるものではない。図1は、本発明の第1の実施形態に係る複合基板を模式的に示す断面図である。   Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In addition, although embodiment of this invention is described below based on drawing, those drawings are provided for illustration and this invention is not limited to those drawings. FIG. 1 is a cross-sectional view schematically showing a composite substrate according to the first embodiment of the present invention.

図1に示すように、第1の実施形態の複合基板1は、第1の基板として例えばLTCC(Low Temperature Co-fired Ceramic:低温焼成セラミックス)基板2等のセラミック基板と、第2の基板としてこのLTCC基板2とは異なる熱膨張係数を有する例えばアルミナ基板3等のセラミック基板と、これら異種材料のセラミック基板の間に介在してなる多層樹脂層4とを備える。   As shown in FIG. 1, the composite substrate 1 according to the first embodiment includes a ceramic substrate such as an LTCC (Low Temperature Co-fired Ceramic) substrate 2 as a first substrate, and a second substrate. For example, a ceramic substrate such as an alumina substrate 3 having a thermal expansion coefficient different from that of the LTCC substrate 2 and a multilayer resin layer 4 interposed between the ceramic substrates of different materials are provided.

LTCC基板2及びアルミナ基板3は、それぞれ内部配線としてビアホール導体(不図示)を有し、このビアホール導体と電気的に接続するようにその表面には回路パターン5が形成されている。これら回路パターン5は、多層樹脂層4をその厚さ方向に貫通するビアホール導体6と電気的に接続される。   The LTCC substrate 2 and the alumina substrate 3 each have a via hole conductor (not shown) as an internal wiring, and a circuit pattern 5 is formed on the surface so as to be electrically connected to the via hole conductor. These circuit patterns 5 are electrically connected to via-hole conductors 6 that penetrate the multilayer resin layer 4 in the thickness direction.

多層樹脂層4は、LTCC基板2とアルミナ基板3とを接着する樹脂接着剤層である。また、多層樹脂層4は、第1の樹脂層として厚さ50〜100μmのコア層と、このコア層の少なくとも片面、本実施形態では両面に設けられたコート層である第2の樹脂層とを備えている。コート層8の厚さは、上記コア層7の厚さの1/40〜1/5、好ましくは5〜10μmの範囲である。コート層8である第2の樹脂層をコア層7である第1の樹脂層の厚さに対して上記範囲にすることで、コア層7である熱可塑性樹脂の影響が支配的となり、寸法安定性が確保され、ビア形状の保持も可能となる。   The multilayer resin layer 4 is a resin adhesive layer that bonds the LTCC substrate 2 and the alumina substrate 3 together. The multilayer resin layer 4 includes a core layer having a thickness of 50 to 100 μm as a first resin layer, and a second resin layer that is a coat layer provided on at least one side of the core layer, in this embodiment, both sides. It has. The thickness of the coat layer 8 is 1/40 to 1/5, preferably 5 to 10 μm, of the thickness of the core layer 7. By making the second resin layer that is the coat layer 8 within the above range with respect to the thickness of the first resin layer that is the core layer 7, the influence of the thermoplastic resin that is the core layer 7 becomes dominant, and the dimensions Stability is ensured and the via shape can be maintained.

第1の樹脂層であるコア層7としては、熱可塑性樹脂を含んでいればよく、多層樹脂層4の体積収縮(寸法変化)を抑制してビアホール導体6の所望の形状と位置精度を保持できる点から、例えばポリエーテルエーテルケトン樹脂と、ポリエーテルイミド樹脂と、無機フィラーとを配合調整した熱可塑性樹脂組成物が好ましい。配合例としては、例えばポリエーテルエーテルケトン樹脂70〜20重量%と、ポリエーテルイミド樹脂30〜80重量%からなる樹脂100重量部に対して、無機フィラーの配合量が5〜65重量部であることが好ましい。このように構成されたコア層7は、基板間に挟まれ加熱加圧して積層一体化された場合に、良好な電気的導通を付与することができる。また、このコア層7は、層平面方向(XY方向)の50℃〜150℃での熱膨張係数が、−10〜30×10−6/℃であり、かつ、厚さ方向(Z方向)の熱膨張係数が、多層樹脂層4に形成されたビアホール導体6の熱膨張係数以上であることが好ましい。このような熱膨張係数の範囲にすることで、本実施形態の異種材料のセラミック基板2、3を接合してなる複合基板1を作製した場合に、多層樹脂層4と各セラミック基板2,3の界面に集中する応力を緩和することができる。また、多層樹脂層4内のコア層7とコート層8との界面に集中する応力も緩和することができる。 The core layer 7 as the first resin layer only needs to contain a thermoplastic resin, and the volumetric shrinkage (dimensional change) of the multilayer resin layer 4 is suppressed and the desired shape and positional accuracy of the via-hole conductor 6 are maintained. From the point which can be performed, the thermoplastic resin composition which mix | blended and adjusted, for example, polyetheretherketone resin, polyetherimide resin, and an inorganic filler is preferable. As a blending example, for example, the blending amount of the inorganic filler is 5 to 65 parts by weight with respect to 100 parts by weight of the resin composed of 70 to 20% by weight of polyetheretherketone resin and 30 to 80% by weight of polyetherimide resin. It is preferable. The core layer 7 configured as described above can provide good electrical conduction when sandwiched between substrates and heated and pressed to be integrated. The core layer 7 has a thermal expansion coefficient of −10 to 30 × 10 −6 / ° C. in the layer plane direction (XY direction) at 50 ° C. to 150 ° C., and the thickness direction (Z direction). The thermal expansion coefficient is preferably equal to or higher than the thermal expansion coefficient of the via-hole conductor 6 formed in the multilayer resin layer 4. By setting the thermal expansion coefficient within such a range, when the composite substrate 1 formed by joining the ceramic substrates 2 and 3 of different materials of the present embodiment is manufactured, the multilayer resin layer 4 and the ceramic substrates 2 and 3 are formed. The stress concentrated on the interface can be relaxed. Moreover, the stress concentrated on the interface between the core layer 7 and the coat layer 8 in the multilayer resin layer 4 can be relaxed.

第2の樹脂層であるコート層8は、本実施形態ではコア層7の両面に設けられ、被接着物であるセラミック基板2、3表面に形成された回路パターン5の凹凸等に対して優れた追随性を発揮し、層間剥離、接着不良等を抑制することができる。コート層8としては、熱硬化性樹脂を含んでいればよく、高耐熱性を発揮し、優れた流れ性及び接着性を有する点から、例えばポリイミド樹脂、変性エポキシ樹脂、BCB樹脂、PPE樹脂、シアネート系樹脂等が好ましい。このように構成されたコート層8は、層平面方向(XY方向)及び厚さ方向(Z方向)の50℃〜150℃での熱膨張係数が10〜60×10−6/℃の範囲であることが好ましい。このような熱膨張係数の範囲にすることで、熱膨張係数の異なるセラミック基板同士を接合した場合に、多層樹脂層4と各セラミック基板2,3の界面に集中する応力を緩和するとともに、多層樹脂層4内のコア層7とコート層8との界面に集中する応力を緩和することができる。また、上記のような熱硬化性樹脂単体では熱膨張係数が大きくなるため、フィラーを含有させることで低熱膨張化を図る方法が一般的に用いられる。この場合、フィラー含有量の増加は樹脂の流れ性を低下させる要因となるが、上記の熱膨張係数の範囲内であれば、流動性を損なうことなく、良好なパターン追随性が得られる。 The coating layer 8 as the second resin layer is provided on both surfaces of the core layer 7 in this embodiment, and is excellent for the unevenness of the circuit pattern 5 formed on the surface of the ceramic substrate 2 and 3 as an adherend. In addition, it is possible to suppress delamination, adhesion failure, and the like. The coating layer 8 only needs to contain a thermosetting resin, exhibit high heat resistance, and have excellent flowability and adhesiveness. For example, polyimide resin, modified epoxy resin, BCB resin, PPE resin, Cyanate resins and the like are preferable. The coat layer 8 thus configured has a coefficient of thermal expansion of 10 to 60 × 10 −6 / ° C. at 50 ° C. to 150 ° C. in the layer plane direction (XY direction) and the thickness direction (Z direction). Preferably there is. By setting the thermal expansion coefficient in such a range, when ceramic substrates having different thermal expansion coefficients are joined together, stress concentrated on the interface between the multilayer resin layer 4 and the ceramic substrates 2 and 3 is alleviated. The stress concentrated on the interface between the core layer 7 and the coat layer 8 in the resin layer 4 can be relaxed. In addition, since the thermal expansion coefficient of the thermosetting resin alone as described above is large, a method of reducing the thermal expansion by incorporating a filler is generally used. In this case, an increase in the filler content causes a decrease in the flowability of the resin, but a good pattern followability can be obtained without impairing the fluidity as long as the thermal expansion coefficient is within the above range.

第1の樹脂層であるコア層7と第2の樹脂層であるコート層8からなる、多層樹脂層4の熱膨張係数としては、コート層8とコア層7とを含む全体として層平面方向の50℃〜150℃での熱膨張係数が3〜25×10−6/℃であり、かつ、厚さ方向の熱膨張係数がビアホール導体6の熱膨張係数以上であることが好ましい。このような熱膨張係数の範囲にすることで、異種材料のセラミック基板2,3同士を接合した場合に、多層樹脂層4と各セラミック基板2,3の界面に集中する応力を緩和することができる。 The thermal expansion coefficient of the multilayer resin layer 4 composed of the core layer 7 that is the first resin layer and the coat layer 8 that is the second resin layer is the layer plane direction as a whole including the coat layer 8 and the core layer 7. The thermal expansion coefficient at 50 ° C. to 150 ° C. is 3 to 25 × 10 −6 / ° C., and the thermal expansion coefficient in the thickness direction is preferably equal to or greater than the thermal expansion coefficient of the via-hole conductor 6. By setting the thermal expansion coefficient within such a range, stresses concentrated at the interface between the multilayer resin layer 4 and the ceramic substrates 2 and 3 can be alleviated when the ceramic substrates 2 and 3 of different materials are joined to each other. it can.

このような多層樹脂層4の製造方法としては、例えば押出キャスト法等で得られたフィルム状のコア層7の両面に、ポリイミド樹脂等からなるフィルム状のコート層8を設けて熱プレス機で加熱加圧する方法、ワニス状樹脂を塗布する方法等が挙げられる。   As a method for producing such a multilayer resin layer 4, for example, a film-like coat layer 8 made of polyimide resin or the like is provided on both surfaces of a film-like core layer 7 obtained by an extrusion casting method or the like. Examples thereof include a method of heating and pressing, a method of applying a varnish-like resin, and the like.

なお、第1の基板としてLTCC基板2を使用し、第2の基板としてアルミナ基板3を用いて説明したが、これら基板を構成する材料は適宜変更可能である。すなわち、本実施形態において、第1の基板及び第2の基板の25℃〜300℃での熱膨張係数の絶対値の差は、10×10−6/℃以内であることがより好ましい。構成する材料としては、例えば窒化ケイ素、酸化イットリウム、窒化物アルミニウム、炭化ケイ素等の公知のセラミック材料が例示され、1種単独又は2種以上を含有した複合材料を使用してもよい。また、異種材料のセラミック基板の数も限られるものではなく、3個もしくはそれ以上であってもよい。 In addition, although the LTCC board | substrate 2 was used as a 1st board | substrate and the alumina board | substrate 3 was used as a 2nd board | substrate, it demonstrated, The material which comprises these board | substrates can be changed suitably. That is, in the present embodiment, the difference between the absolute values of the thermal expansion coefficients at 25 ° C. to 300 ° C. between the first substrate and the second substrate is more preferably within 10 × 10 −6 / ° C. Examples of the constituent material include known ceramic materials such as silicon nitride, yttrium oxide, aluminum nitride, and silicon carbide, and a single material or a composite material containing two or more materials may be used. Further, the number of different types of ceramic substrates is not limited, and may be three or more.

また、第1の基板及び第2の基板は、セラミック基板以外に、樹脂基板(例えば、FPC基板、エポキシ系ビルドアップ基板など)、ガラス基板等の絶縁基板(石英ガラス基板等)、金属基板(アルミベースの基板、銅ベースの基板、メタル単体など)、シリコン基板、さらには電気素子(例えばインダクタ素子、コンデンサ素子等の受動素子、半導体素子等の能動素子)を適用することもできる。   In addition to the ceramic substrate, the first substrate and the second substrate include a resin substrate (for example, an FPC substrate, an epoxy buildup substrate), an insulating substrate such as a glass substrate (quartz glass substrate, etc.), a metal substrate ( An aluminum-based substrate, a copper-based substrate, a single metal, or the like), a silicon substrate, or an electric element (for example, a passive element such as an inductor element or a capacitor element or an active element such as a semiconductor element) can also be applied.

上述した本実施形態の複合基板1は、例えば以下のようにして製造される。   The composite substrate 1 of the present embodiment described above is manufactured, for example, as follows.

まず、成形、焼成したアルミナ基板3(厚さ1.0mm、20mm角、25℃〜300℃での熱膨張係数6.8×10−6/℃)とLTCC基板2(厚さ1.0mm、20mm角、25℃〜300℃での熱膨張係数5.9×10−6/℃)を用意する。なお、これらの基板2、3には、内部にビアホール導体を形成し、その表面に回路パターン5として例えばAg、W、Cu粉末等を含む導体ペーストをパターン印刷して形成しておく。 First, the molded and fired alumina substrate 3 (thickness 1.0 mm, 20 mm square, thermal expansion coefficient 6.8 × 10 −6 / ° C. at 25 ° C. to 300 ° C.) and LTCC substrate 2 (thickness 1.0 mm, A thermal expansion coefficient of 5.9 × 10 −6 / ° C. at 20 mm square and 25 ° C. to 300 ° C. is prepared. In these substrates 2 and 3, via hole conductors are formed inside, and a conductive paste containing, for example, Ag, W, Cu powder or the like is formed as a circuit pattern 5 on the surface thereof by pattern printing.

次に、多層樹脂層4(厚さ50μm)に、例えば炭酸ガスレーザー等のレーザー加工、パンチング加工もしくはドリル加工等でビアホールを形成し、このビアホールに導電性ペーストをスクリーン印刷、圧入、ディスペンサ等で充填して、電気導通用のビアホール導体6を形成する。導電性ペーストは、Ag,Cu,Sn粉末等に液状樹脂、可塑剤、硬化剤等を加えてペースト化したものであり、無溶剤系が好ましい。   Next, via holes are formed in the multilayer resin layer 4 (thickness 50 μm) by, for example, laser processing such as a carbon dioxide laser, punching processing or drill processing, and conductive paste is screen printed, press-fitted, dispenser, etc. The via-hole conductor 6 for electrical conduction is formed by filling. The conductive paste is obtained by adding a liquid resin, a plasticizer, a curing agent, or the like to Ag, Cu, Sn powder or the like, and is preferably a solventless system.

続いて、アルミナ基板3とLTCC基板2との間に多層樹脂層4を挟み、例えば275℃、5MPa、30分のプレス条件で真空加熱プレス機により加熱加圧して積層一体化する。   Subsequently, the multilayer resin layer 4 is sandwiched between the alumina substrate 3 and the LTCC substrate 2 and laminated and integrated by heating and pressurizing with a vacuum heating press machine, for example, at 275 ° C., 5 MPa for 30 minutes.

以上説明したように、本実施形態によれば、コア層7の両面に熱硬化性樹脂からなるコート層8を設けた多層樹脂層4を用いて熱膨張係数の異なるセラミック基板2,3を接合することにより、多層樹脂層4に形成された所望のビア形状と位置精度を保持して良好な層間導通が得られ、コート層8がセラミック基板2,3表面に形成された回路パターン5の凹凸に対して良好な追随性を発揮するため、基板2,3と多層樹脂層4の間で層間剥離、接着不良、クラック等のない信頼性に優れた複合基板1を提供することができる。また、予め成形、焼成し、パターン形成された異種材料のセラミック基板2,3間に多層樹脂層4を挟んで熱プレスすることにより、比較的低温での接合が可能であり、熱膨張係数の差による異種材料界面の応力集中を緩和することができる。   As described above, according to the present embodiment, the ceramic substrates 2 and 3 having different thermal expansion coefficients are joined using the multilayer resin layer 4 in which the coat layer 8 made of a thermosetting resin is provided on both surfaces of the core layer 7. By doing so, the desired via shape and positional accuracy formed in the multilayer resin layer 4 can be maintained and good interlayer conduction can be obtained, and the unevenness of the circuit pattern 5 in which the coat layer 8 is formed on the surfaces of the ceramic substrates 2 and 3 Therefore, it is possible to provide the composite substrate 1 having excellent reliability without delamination, adhesion failure, cracks, etc. between the substrates 2 and 3 and the multilayer resin layer 4. In addition, the multilayer resin layer 4 is sandwiched between the ceramic substrates 2 and 3 that are pre-molded, fired, and patterned, and then heat-pressed to enable bonding at a relatively low temperature. Stress concentration at the interface between different materials due to the difference can be reduced.

次に、第2の実施形態に係る複合基板について図2を用いて説明する。図2は、第2の実施形態に係る複合基板を模式的に示す断面図である。本実施形態の複合基板21は、上述した第1の実施形態において、樹脂接着材4のコート層8がコア材7の片面に設けられる点が異なる。なお、第1の実施形態と同一の構成部分には、同一の符号を付してその説明を簡略又は省略する。   Next, a composite substrate according to a second embodiment will be described with reference to FIG. FIG. 2 is a cross-sectional view schematically showing a composite substrate according to the second embodiment. The composite substrate 21 of this embodiment is different from the first embodiment described above in that the coating layer 8 of the resin adhesive 4 is provided on one side of the core material 7. In addition, the same code | symbol is attached | subjected to the component same as 1st Embodiment, and the description is simplified or abbreviate | omitted.

図2に示すように、第2の実施形態の複合基板21は、多層樹脂層4のコート層8がコア層7の片面に設けられている。コート層8は、多層樹脂層4との接合面となるセラミック基板2、3に形成された回路パターン5に凹凸の差が少なく、ほぼフラットに近い場合には設けなくてもよい。   As shown in FIG. 2, in the composite substrate 21 of the second embodiment, the coat layer 8 of the multilayer resin layer 4 is provided on one side of the core layer 7. The coat layer 8 may be omitted when the circuit pattern 5 formed on the ceramic substrates 2 and 3 that are to be bonded to the multilayer resin layer 4 has little unevenness and is almost flat.

したがって、本実施形態によれば、コア層7に熱硬化性樹脂からなるコート層8を設けた多層樹脂層4を用いて異種材料のセラミック基板2,3を接合することにより、上記第1の実施形態と同様に、良好な層間導通を得られ、層間剥離、反り、クラックを防止して信頼性に優れた複合基板21を提供することができる。また、コア層7の片面にコート層8を有する多層樹脂層4を用いることにより、セラミック基板2,3表面に形成された回路パターン5の凹凸の差に応じて、多層樹脂層4の接合面を選択することができる。   Therefore, according to the present embodiment, the first substrate is formed by bonding the ceramic substrates 2 and 3 of different materials using the multilayer resin layer 4 in which the core layer 7 is provided with the coat layer 8 made of a thermosetting resin. Similar to the embodiment, it is possible to provide a composite substrate 21 that can obtain good interlayer conduction and can prevent delamination, warpage, and cracks and has excellent reliability. Further, by using the multilayer resin layer 4 having the coat layer 8 on one side of the core layer 7, the bonding surface of the multilayer resin layer 4 can be selected depending on the unevenness of the circuit pattern 5 formed on the surfaces of the ceramic substrates 2 and 3. Can be selected.

次に、第3の実施形態に係る複合基板について図3を用いて説明する。図3は、第3の実施形態に係る複合基板を模式的に示す断面図である。本実施形態の複合基板31は、上述した第1の実施形態において、異種材料のセラミック基板2,3に加えて、フレキシブルプリント(FPC)基板32を積層、接合する点が異なる。なお、第1の実施形態と同一の構成部分には、同一の符号を付してその説明を簡略又は省略する。   Next, a composite substrate according to a third embodiment will be described with reference to FIG. FIG. 3 is a cross-sectional view schematically showing a composite substrate according to the third embodiment. The composite substrate 31 of this embodiment is different from the first embodiment described above in that a flexible print (FPC) substrate 32 is laminated and bonded in addition to the ceramic substrates 2 and 3 of different materials. In addition, the same code | symbol is attached | subjected to the component same as 1st Embodiment, and the description is simplified or abbreviate | omitted.

図3に示すように、第3の実施形態の複合基板31は、LTCC基板2、FPC基板32及びアルミナ基板3の間に多層樹脂層4をそれぞれ挟み、これらを加熱加圧して積層一体化したものである。多層樹脂層4は、本実施形態では、コア層7の両面にコート層8を設けたものである。FPC基板32は、その内部にビアホール導体(不図示)を有し、このビアホール導体と電気的に接続された回路パターン5がFPC基板32の表面に引き出されている。この回路パターン5は、FPC基板32の両面に設けられた多層樹脂層4のビアホール導体6と電気的に接続されている。   As shown in FIG. 3, in the composite substrate 31 of the third embodiment, the multilayer resin layer 4 is sandwiched between the LTCC substrate 2, the FPC substrate 32, and the alumina substrate 3, and these are heated and pressed to be laminated and integrated. Is. In the present embodiment, the multilayer resin layer 4 is obtained by providing the coat layer 8 on both surfaces of the core layer 7. The FPC board 32 has a via-hole conductor (not shown) inside, and a circuit pattern 5 electrically connected to the via-hole conductor is drawn out to the surface of the FPC board 32. This circuit pattern 5 is electrically connected to the via-hole conductor 6 of the multilayer resin layer 4 provided on both surfaces of the FPC board 32.

したがって、本実施形態によれば、コア層7の両面に熱硬化性樹脂からなるコート層8を設けた多層樹脂層4を用いて異種材料のセラミック基板2,3とFPC基板32を接合することにより、上述した実施形態と同様に、層間剥離、反り、クラックを防止し、信頼性に優れた複合基板31を提供することができる。また、比較的低温での接合が可能であるため、接合可能な基板の種類が増え、被接着物の選択の自由度を高めることができる。なお、異種材料のセラミック基板2,3を用いたが、その間にFPC基板32を挟んで積層する本実施形態では、同種材料からなるセラミック基板を用いることもできる。   Therefore, according to the present embodiment, the ceramic substrates 2 and 3 of different materials and the FPC substrate 32 are bonded using the multilayer resin layer 4 in which the coat layer 8 made of thermosetting resin is provided on both surfaces of the core layer 7. Thus, as in the above-described embodiment, delamination, warpage, and cracks can be prevented, and the composite substrate 31 having excellent reliability can be provided. In addition, since bonding at a relatively low temperature is possible, the types of substrates that can be bonded are increased, and the degree of freedom in selecting an object to be bonded can be increased. Although the ceramic substrates 2 and 3 of different materials are used, in this embodiment in which the FPC substrate 32 is sandwiched between them, ceramic substrates made of the same kind of material can be used.

(その他の実施形態)
なお、本発明の実施形態は上記の実施形態に限られず拡張、変更可能であり、拡張、変更した実施形態も本発明の技術的範囲に含まれる。
(Other embodiments)
The embodiments of the present invention are not limited to the above-described embodiments, and can be expanded and modified. The expanded and modified embodiments are also included in the technical scope of the present invention.

上記実施形態では、2個又は3個の異種材料からなる基板を接着した構造について説明したが、基板の積層数はこれに限られるものではなく、4個もしくはそれ以上であってもよい。   In the above-described embodiment, the structure in which two or three substrates made of different materials are bonded has been described. However, the number of stacked substrates is not limited to this, and may be four or more.

また、上記実施形態では、多層樹脂層4のコア層7としてポリエーテルエーテルケトン樹脂とポリエーテルイミド樹脂と無機フィラーから構成された樹脂フィルムを用いたが、これに限定されるものではない。例えば異種材料のセラミック基板を接着、接合する場合には、コア層7が熱可塑性樹脂を含む材料であり、好ましくは、コア層7の層平面方向の50℃〜150℃での熱膨張係数が、−10〜30×10−6/℃であり、かつ、厚さ方向の熱膨張係数がビアホール導体6の熱膨張係数以上である樹脂材料およびフィラーであればよい。また、熱可塑性樹脂としては、ポリエーテルエーテルケトン樹脂、ポリエーテルイミド樹脂以外に、例えば熱可塑性ポリイミド、液晶ポリマー等が挙げられる。 Moreover, in the said embodiment, although the resin film comprised from polyetheretherketone resin, polyetherimide resin, and an inorganic filler was used as the core layer 7 of the multilayer resin layer 4, it is not limited to this. For example, when bonding and joining ceramic substrates of different materials, the core layer 7 is a material containing a thermoplastic resin, and preferably has a thermal expansion coefficient at 50 ° C. to 150 ° C. in the layer plane direction of the core layer 7. -10 to 30 × 10 −6 / ° C. and a resin material and filler that have a thermal expansion coefficient in the thickness direction that is equal to or greater than the thermal expansion coefficient of the via-hole conductor 6. Moreover, as a thermoplastic resin, a thermoplastic polyimide, a liquid crystal polymer, etc. are mentioned other than polyetheretherketone resin and polyetherimide resin, for example.

また、上記実施形態では、被接着物となるセラミック基板として、LTCC基板2、アルミナ基板3を用いたが、これ以外に、高誘電率を有する誘電体セラミックス基板を適用することもできる。誘電体セラミックス基板としては、例えばチタン酸バリウム、チタン酸ストロンチウム、チタン酸カルシウム、チタン酸鉛又はこれらの混合物が挙げられる。   Moreover, in the said embodiment, although the LTCC board | substrate 2 and the alumina board | substrate 3 were used as a ceramic board | substrate used as a to-be-adhered thing, the dielectric material ceramic board | substrate which has a high dielectric constant is also applicable besides this. Examples of the dielectric ceramic substrate include barium titanate, strontium titanate, calcium titanate, lead titanate, or a mixture thereof.

また、基板以外に、被接着物には電気素子として、例えばインダクタ素子、コンデンサ素子等の受動素子、半導体素子等の能動素子を適用することもできる。ここで、図4にインダクタ素子42とコンデンサ素子43とを多層樹脂層4を介して接合した複合基板を示す。図4に示す複合基板41は、例えば、予め、成形、焼成されたインダクタ素子42とコンデンサ素子43とを、その間に多層樹脂層4を挟んで熱プレスし、積層一体化することによって得られる。   In addition to the substrate, for example, a passive element such as an inductor element or a capacitor element or an active element such as a semiconductor element can be applied as an electrical element to the adherend. Here, FIG. 4 shows a composite substrate in which the inductor element 42 and the capacitor element 43 are joined via the multilayer resin layer 4. The composite substrate 41 shown in FIG. 4 is obtained by, for example, pre-molding and firing an inductor element 42 and a capacitor element 43, which are hot-pressed with the multilayer resin layer 4 interposed therebetween, and laminated and integrated.

また、多層樹脂層4には、電気導通用のビアホール導体6以外に、被接着物の種類、用途に応じて放熱用のサーマルビアを形成することができ、上記ビアホール導体6と併用することもできる。ここで、図5に、例えば半導体素子等の発熱素子52から発生した熱を放熱するサーマルビア53を多層樹脂層4に形成した複合基板の一例を示す。この複合基板51においては、半導体素子等の発熱素子52が、多層樹脂層4のサーマルビア53形成部の上面に設けられる。発熱素子52から発生した熱は、サーマルビア53を経由して多層樹脂層4の裏面に設けられた金属基板54に伝熱される。   In addition to the via hole conductor 6 for electrical conduction, a thermal via for heat dissipation can be formed in the multilayer resin layer 4 in accordance with the type and application of the object to be bonded. it can. Here, FIG. 5 shows an example of a composite substrate in which a thermal via 53 for radiating heat generated from a heating element 52 such as a semiconductor element is formed in the multilayer resin layer 4. In the composite substrate 51, a heating element 52 such as a semiconductor element is provided on the upper surface of the thermal via 53 forming portion of the multilayer resin layer 4. The heat generated from the heating element 52 is transferred to the metal substrate 54 provided on the back surface of the multilayer resin layer 4 via the thermal via 53.

上記実施形態では、被接着物としてその表面に回路パターン5が形成されたセラミック基板2,3、FPC基板32を使用し、また、多層樹脂層4としてビアホール導体6が形成された樹脂接着材を用いて説明したが、これに限定されない。例えば、ビアホール導体6をもたない多層樹脂層4を用いて、内部や表面に回路を有さない異種材料の基板を接着することもできる。   In the above embodiment, the ceramic substrates 2 and 3 having the circuit pattern 5 formed on the surface thereof and the FPC substrate 32 are used as the adherend, and the resin adhesive having the via-hole conductor 6 formed as the multilayer resin layer 4 is used. However, the present invention is not limited to this. For example, a multi-layer resin layer 4 having no via-hole conductor 6 can be used to bond a substrate made of a different material having no circuit inside or on the surface.

本発明の一実施形態に係る複合基板の構成を模式的に示す断面図。Sectional drawing which shows typically the structure of the composite substrate which concerns on one Embodiment of this invention. 本発明の別の実施形態に係る複合基板の構成を模式的に示す断面図。Sectional drawing which shows typically the structure of the composite substrate which concerns on another embodiment of this invention. 本発明のさらに別の実施形態に係る複合基板の構成を模式的に示す断面図。Sectional drawing which shows typically the structure of the composite substrate which concerns on another embodiment of this invention. 本発明のさらに別の実施形態に係る複合基板の構成を模式的に示す断面図。Sectional drawing which shows typically the structure of the composite substrate which concerns on another embodiment of this invention. 本発明のさらに別の実施形態に係る複合基板の構成を模式的に示す断面図。Sectional drawing which shows typically the structure of the composite substrate which concerns on another embodiment of this invention.

符号の説明Explanation of symbols

1、21、31,41,51…複合基板、2…LTCC基板、3…アルミナ基板、4…多層樹脂層、5…回路パターン、6…ビアホール導体、7…コア層、8…コート層、32…FPC基板、52…発熱素子、53…サーマルビア、54…金属基板。   1, 21, 31, 41, 51... Composite substrate, 2... LTCC substrate, 3... Alumina substrate, 4 ... Multilayer resin layer, 5 ... Circuit pattern, 6 ... Via-hole conductor, 7 ... Core layer, 8 ... Coat layer, 32 ... FPC board, 52 ... heat generating element, 53 ... thermal via, 54 ... metal board.

Claims (6)

熱可塑性樹脂を含む第1の樹脂層とこの第1の樹脂層の少なくとも片面に設けられた熱硬化性樹脂を含む第2の樹脂層からなる多層樹脂層と、
前記多層樹脂層の一方の主面に設けられた第1の基板又は電気素子と、
前記第1の基板又は電気素子とは異なる熱膨張係数を有し、前記多層樹脂層の他方の主面に設けられた第2の基板又は電気素子と
を具備することを特徴とする複合基板。
A multilayer resin layer comprising a first resin layer containing a thermoplastic resin and a second resin layer containing a thermosetting resin provided on at least one surface of the first resin layer;
A first substrate or electrical element provided on one main surface of the multilayer resin layer;
A composite substrate comprising a second substrate or an electric element having a thermal expansion coefficient different from that of the first substrate or the electric element and provided on the other main surface of the multilayer resin layer.
前記多層樹脂層は、前記第1の基板又は電気素子と前記第2の基板又は電気素子とを電気的に接続する厚さ方向に貫通されたビアホール導体または、前記第1の基板又は電気素子と前記第2の基板又は電気素子との間の熱のみを伝導するサーマルビアのうち少なくともいずれか一方を有することを特徴とする請求項1に記載の複合基板。   The multilayer resin layer includes a via-hole conductor penetrating in a thickness direction for electrically connecting the first substrate or electrical element and the second substrate or electrical element, or the first substrate or electrical element. The composite substrate according to claim 1, further comprising at least one of thermal vias that conduct only heat between the second substrate and the electric element. 前記多層樹脂層の第2の樹脂層の厚さは、前記第1の樹脂層の厚さの1/40〜1/5であることを特徴とする請求項1又は2に記載の複合基板。   The thickness of the 2nd resin layer of the said multilayer resin layer is 1/40-1/5 of the thickness of the said 1st resin layer, The composite substrate of Claim 1 or 2 characterized by the above-mentioned. 前記多層樹脂層の第1の樹脂層の層平面方向の50℃〜150℃での熱膨張係数が、−10〜30×10−6/℃であり、かつ、厚さ方向の熱膨張係数が前記ビアホール導体または前記サーマルビアのうち少なくともいずれか一方の熱膨張係数以上であることを特徴とする請求項2又は3に記載の複合基板。 The thermal expansion coefficient at 50 ° C. to 150 ° C. in the layer plane direction of the first resin layer of the multilayer resin layer is −10 to 30 × 10 −6 / ° C., and the thermal expansion coefficient in the thickness direction is 4. The composite substrate according to claim 2, wherein the composite substrate has a thermal expansion coefficient equal to or greater than at least one of the via-hole conductor and the thermal via. 前記多層樹脂層の第2の樹脂層の層平面方向及び厚さ方向の50℃〜150℃での熱膨張係数が、10〜60×10−6/℃であることを特徴とする請求項1乃至4のいずれか1項に記載の複合基板。 2. The thermal expansion coefficient at 50 ° C. to 150 ° C. in the layer plane direction and thickness direction of the second resin layer of the multilayer resin layer is 10 to 60 × 10 −6 / ° C. 5. The composite substrate according to any one of items 1 to 4. 前記多層樹脂層の層平面方向の50℃〜150℃での熱膨張係数が、全体として3〜25×10−6/℃であり、かつ、厚さ方向の熱膨張係数が前記ビアホール導体または前記サーマルビアのうち少なくともいずれか一方の熱膨張係数以上であることを特徴とする請求項2乃至5のいずれか1項に記載の複合基板。 The thermal expansion coefficient at 50 ° C. to 150 ° C. in the layer plane direction of the multilayer resin layer is 3 to 25 × 10 −6 / ° C. as a whole, and the thermal expansion coefficient in the thickness direction is the via-hole conductor or the The composite substrate according to claim 2, wherein the composite substrate has a thermal expansion coefficient equal to or greater than at least one of the thermal vias.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015104168A (en) * 2013-11-21 2015-06-04 アスモ株式会社 Motor pump
WO2018131465A1 (en) * 2017-01-16 2018-07-19 富士通株式会社 Circuit board, circuit board manufacturing method, and electronic device
US10499506B2 (en) 2016-03-11 2019-12-03 Murata Manufacturing Co., Ltd. Composite substrate and method for manufacturing composite substrate

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01214031A (en) * 1988-02-22 1989-08-28 Canon Inc Electric circuit device
JPH05291723A (en) * 1992-04-08 1993-11-05 Ricoh Co Ltd Electrical connection structure and connection method between substrates
WO1998047331A1 (en) * 1997-04-16 1998-10-22 Kabushiki Kaisha Toshiba Wiring board, wiring board fabrication method, and semiconductor package
JP2003197849A (en) * 2001-10-18 2003-07-11 Matsushita Electric Ind Co Ltd Module with built-in component and method of manufacturing the same
JP2005236256A (en) * 2003-09-12 2005-09-02 Matsushita Electric Ind Co Ltd Connector sheet, wiring board and manufacturing method of connector sheet and wiring board

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01214031A (en) * 1988-02-22 1989-08-28 Canon Inc Electric circuit device
JPH05291723A (en) * 1992-04-08 1993-11-05 Ricoh Co Ltd Electrical connection structure and connection method between substrates
WO1998047331A1 (en) * 1997-04-16 1998-10-22 Kabushiki Kaisha Toshiba Wiring board, wiring board fabrication method, and semiconductor package
JP2003197849A (en) * 2001-10-18 2003-07-11 Matsushita Electric Ind Co Ltd Module with built-in component and method of manufacturing the same
JP2005236256A (en) * 2003-09-12 2005-09-02 Matsushita Electric Ind Co Ltd Connector sheet, wiring board and manufacturing method of connector sheet and wiring board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015104168A (en) * 2013-11-21 2015-06-04 アスモ株式会社 Motor pump
US10499506B2 (en) 2016-03-11 2019-12-03 Murata Manufacturing Co., Ltd. Composite substrate and method for manufacturing composite substrate
WO2018131465A1 (en) * 2017-01-16 2018-07-19 富士通株式会社 Circuit board, circuit board manufacturing method, and electronic device
JP2018116951A (en) * 2017-01-16 2018-07-26 富士通株式会社 Circuit board, manufacturing method for the same, and electronic equipment
US11057996B2 (en) 2017-01-16 2021-07-06 Fujitsu Interconnect Technologies Limited Circuit board, method of manufacturing circuit board, and electronic device

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